Lines Matching +full:interrupts +full:- +full:extended
1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * DS1685/DS1687-series RTC chips.
8 * include larger, battery-backed NV-SRAM, burst-mode access, and an RTC
11 * Copyright (C) 2011-2014 Joshua Kinard <kumba@gentoo.org>.
12 * Copyright (C) 2009 Matthias Fuchs <matthias.fuchs@esd-electronics.com>.
15 * DS1685/DS1687 3V/5V Real-Time Clocks, 19-5215, Rev 4/10.
16 * DS17x85/DS17x87 3V/5V Real-Time Clocks, 19-5222, Rev 4/10.
17 * DS1689/DS1693 3V/5V Serialized Real-Time Clocks, Rev 112105.
18 * Application Note 90, Using the Multiplex Bus RTC Extended Features.
29 * struct ds1685_priv - DS1685 private data structure.
38 * @prepare_poweroff: pointer to platform pre-poweroff function.
40 * @post_ram_clear: pointer to platform post ram-clear function.
59 * struct ds1685_rtc_platform_data - platform data structure.
60 * @plat_prepare_poweroff: platform-specific pre-poweroff function.
61 * @plat_wake_alarm: platform-specific wake alarm function.
62 * @plat_post_ram_clear: platform-specific post ram-clear function.
65 * registers, or uses one or more of the extended interrupts and needs special
87 #define RTC_SECS 0x00 /* Seconds 00-59 */
88 #define RTC_SECS_ALARM 0x01 /* Alarm Seconds 00-59 */
89 #define RTC_MINS 0x02 /* Minutes 00-59 */
90 #define RTC_MINS_ALARM 0x03 /* Alarm Minutes 00-59 */
91 #define RTC_HRS 0x04 /* Hours 01-12 AM/PM || 00-23 */
92 #define RTC_HRS_ALARM 0x05 /* Alarm Hours 01-12 AM/PM || 00-23 */
93 #define RTC_WDAY 0x06 /* Day of Week 01-07 */
94 #define RTC_MDAY 0x07 /* Day of Month 01-31 */
95 #define RTC_MONTH 0x08 /* Month 01-12 */
96 #define RTC_YEAR 0x09 /* Year 00-99 */
97 #define RTC_CENTURY 0x48 /* Century 00-99 */
98 #define RTC_MDAY_ALARM 0x49 /* Alarm Day of Month 01-31 */
104 #define RTC_SECS_BCD_MASK 0x7f /* - x x x x x x x */
105 #define RTC_MINS_BCD_MASK 0x7f /* - x x x x x x x */
106 #define RTC_HRS_12_BCD_MASK 0x1f /* - - - x x x x x */
107 #define RTC_HRS_24_BCD_MASK 0x3f /* - - x x x x x x */
108 #define RTC_MDAY_BCD_MASK 0x3f /* - - x x x x x x */
109 #define RTC_MONTH_BCD_MASK 0x1f /* - - - x x x x x */
115 #define RTC_SECS_BIN_MASK 0x3f /* - - x x x x x x */
116 #define RTC_MINS_BIN_MASK 0x3f /* - - x x x x x x */
117 #define RTC_HRS_12_BIN_MASK 0x0f /* - - - - x x x x */
118 #define RTC_HRS_24_BIN_MASK 0x1f /* - - - x x x x x */
119 #define RTC_MDAY_BIN_MASK 0x1f /* - - - x x x x x */
120 #define RTC_MONTH_BIN_MASK 0x0f /* - - - - x x x x */
121 #define RTC_YEAR_BIN_MASK 0x7f /* - x x x x x x x */
126 #define RTC_WDAY_MASK 0x07 /* - - - - - x x x */
140 #define RTC_EXT_CTRL_4A 0x4a /* Extended Control Register 4A */
141 #define RTC_EXT_CTRL_4B 0x4b /* Extended Control Register 4B */
151 #define RTC_CTRL_A_RS2 BIT(2) /* Rate-Selection Bit 2 */
152 #define RTC_CTRL_A_RS3 BIT(3) /* Rate-Selection Bit 3 */
153 #define RTC_CTRL_A_RS1 BIT(1) /* Rate-Selection Bit 1 */
154 #define RTC_CTRL_A_RS0 BIT(0) /* Rate-Selection Bit 0 */
161 #define RTC_CTRL_B_PIE BIT(6) /* Periodic-Interrupt Enable */
162 #define RTC_CTRL_B_AIE BIT(5) /* Alarm-Interrupt Enable */
163 #define RTC_CTRL_B_UIE BIT(4) /* Update-Ended Interrupt-Enable */
164 #define RTC_CTRL_B_SQWE BIT(3) /* Square-Wave Enable */
166 #define RTC_CTRL_B_2412 BIT(1) /* 12-Hr/24-Hr Mode */
177 #define RTC_CTRL_C_IRQF BIT(7) /* Interrupt-Request Flag */
178 #define RTC_CTRL_C_PF BIT(6) /* Periodic-Interrupt Flag */
179 #define RTC_CTRL_C_AF BIT(5) /* Alarm-Interrupt Flag */
180 #define RTC_CTRL_C_UF BIT(4) /* Update-Ended Interrupt Flag */
194 * Bit names in Extended Control Register 4A.
200 * On the DS17x85/DS17x87, BIT(5) is Burst-Mode Enable (BME), and allows
201 * access to the extended NV-SRAM by automatically incrementing the address
205 #define RTC_CTRL_4A_INCR BIT(6) /* Increment-in-Progress Status */
206 #define RTC_CTRL_4A_PAB BIT(3) /* Power-Active Bar Control */
207 #define RTC_CTRL_4A_RF BIT(2) /* RAM-Clear Flag */
208 #define RTC_CTRL_4A_WF BIT(1) /* Wake-Up Alarm Flag */
211 #define RTC_CTRL_4A_BME BIT(5) /* Burst-Mode Enable */
217 * Bit names in Extended Control Register 4B.
222 #define RTC_CTRL_4B_RCE BIT(4) /* RAM Clear-Enable */
223 #define RTC_CTRL_4B_PRS BIT(3) /* PAB Reset-Select */
224 #define RTC_CTRL_4B_RIE BIT(2) /* RAM Clear-Interrupt Enable */
225 #define RTC_CTRL_4B_WIE BIT(1) /* Wake-Up Alarm-Interrupt Enable */
226 #define RTC_CTRL_4B_KSE BIT(0) /* Kickstart Interrupt-Enable */
234 * to become available, including Extended Control Registers 4A & 4B.
244 #define RTC_BANK1_RAM_DATA_PORT 0x53 /* Extended RAM Data Port */
248 * Model-specific registers in Bank 1.
254 * DS1685/DS1687 - Extended NV-SRAM address (LSB only).
255 * DS1689/DS1693 - Vcc, Vbat, Pwr Cycle Counters & Customer-specific S/N.
256 * DS17x85/DS17x87 - Extended NV-SRAM addresses (MSB & LSB) & Write counter.
259 #define RTC_BANK1_RAM_ADDR 0x50 /* NV-SRAM Addr */
267 #define RTC_BANK1_UNIQ_SN 0x60 /* Customer-specific S/N */
269 #define RTC_BANK1_RAM_ADDR_LSB 0x50 /* NV-SRAM Addr (LSB) */
270 #define RTC_BANK1_RAM_ADDR_MSB 0x51 /* NV-SRAM Addr (MSB) */
290 * Periodic Interrupt Rates / Square-Wave Output Frequency
292 * Periodic rates are selected by setting the RS3-RS0 bits in Control
293 * Register A and enabled via either the E32K bit in Extended Control
296 * E32K overrides the settings of RS3-RS0 and outputs a frequency of 32768Hz
298 * the 1-of-16 decoder is only able to divide the base 32768Hz signal into 13
302 * When E32K is set to a logic 1, periodic interrupts are disabled and reading
303 * /dev/rtc will return -EINVAL. This also applies if the periodic interrupt
306 * Not currently used by the rtc-ds1685 driver because the RTC core removed
307 * support for hardware-generated periodic-interrupts in favour of
308 * hrtimer-generated interrupts. But these defines are kept around for use
310 * hardware-generated periodic interrupts are ever added back.
327 #define RTC_SQW_32768HZ 32768 /* 1 - - - - */
333 * - 50 bytes of NVRAM are available just past the clock registers.
334 * - 64 additional bytes are available in Bank0.
336 * Extended, battery-backed NV-SRAM:
337 * - DS1685/DS1687 - 128 bytes.
338 * - DS1689/DS1693 - 0 bytes.
339 * - DS17285/DS17287 - 2048 bytes.
340 * - DS17485/DS17487 - 4096 bytes.
341 * - DS17885/DS17887 - 8192 bytes.