Home
last modified time | relevance | path

Searched +full:hs +full:- +full:usb +full:- +full:if (Results 1 – 25 of 157) sorted by relevance

1234567

/Linux-v6.1/drivers/net/can/usb/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
2 menu "CAN USB interfaces"
3 depends on USB
12 tristate "EMS CPC-USB/ARM7 CAN/USB interface"
14 This driver is for the one channel CPC-USB/ARM7 CAN/USB interface
15 from EMS Dr. Thomas Wuensche (http://www.ems-wuensche.de).
18 tristate "esd electronics gmbh CAN/USB interfaces"
20 This driver adds supports for several CAN/USB interfaces
24 - esd CAN-USB/2
25 - esd CAN-USB/Micro
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/phy/
Dqcom,usb-hs-phy.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,usb-hs-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm's USB HS PHY binding description
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
12 if:
16 const: qcom,usb-hs-phy-apq8064
22 reset-names:
31 reset-names:
[all …]
Dtransmit-amplitude.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/transmit-amplitude.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 Binding describing the peak-to-peak transmit amplitude for common PHYs
14 - Marek Behún <kabel@kernel.org>
17 tx-p2p-microvolt:
19 Transmit amplitude voltages in microvolts, peak-to-peak. If this property
21 'tx-p2p-microvolt-names' property must be provided and contain
24 tx-p2p-microvolt-names:
[all …]
Dphy-stm32-usbphyc.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/phy-stm32-usbphyc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 USB HS PHY controller binding
22 |_ PHY port#2 ----| |________________
27 - Amelie Delaunay <amelie.delaunay@foss.st.com>
31 const: st,stm32mp1-usbphyc
42 "#address-cells":
45 "#size-cells":
[all …]
Dnvidia,tegra20-usb-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra20-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra USB PHY
10 - Dmitry Osipenko <digetx@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Thierry Reding <thierry.reding@gmail.com>
17 - items:
18 - enum:
[all …]
Drenesas,rcar-gen2-usb-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/renesas,rcar-gen2-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car Gen2 USB PHY
10 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
15 - enum:
16 - renesas,usb-phy-r8a7742 # RZ/G1H
17 - renesas,usb-phy-r8a7743 # RZ/G1M
18 - renesas,usb-phy-r8a7744 # RZ/G1N
[all …]
Dsocionext,uniphier-usb3hs-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/socionext,uniphier-usb3hs-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier USB3 High-Speed (HS) PHY
12 Although the controller includes High-Speed PHY and Super-Speed PHY,
13 this describes about High-Speed PHY.
16 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
21 - socionext,uniphier-pro5-usb3-hsphy
22 - socionext,uniphier-pxs2-usb3-hsphy
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/clock/
Drenesas,rcar-usb2-clock-sel.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: "http://devicetree.org/schemas/clock/renesas,rcar-usb2-clock-sel.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
7 title: Renesas R-Car USB 2.0 clock selector
10 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
13 If you connect an external clock to the USB_EXTAL pin only, you should set
15 If you connect an oscillator to both the USB_XTAL and USB_EXTAL, this module
19 Case 1: An external clock connects to R-Car SoC
20 +----------+ +--- R-Car ---------------------+
[all …]
/Linux-v6.1/drivers/phy/qualcomm/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
6 tristate "Atheros AR71XX/9XXX USB PHY driver"
8 default y if USB_EHCI_HCD_PLATFORM || USB_OHCI_HCD_PLATFORM
12 Enable this to support the USB PHY on Atheros AR71XX/9XXX SoCs.
32 tristate "Qualcomm IPQ4019 USB PHY driver"
36 Support for the USB PHY-s on Qualcomm IPQ40xx SoC-s.
59 with controllers such as PCIe, UFS, and USB on Qualcomm chips.
67 Enable this to support the HighSpeed QUSB2 PHY transceiver for USB
68 controllers on Qualcomm chips. This driver supports the high-speed
70 USB IPs on MSM SOCs.
[all …]
Dphy-qcom-snps-femto-v2.c1 // SPDX-License-Identifier: GPL-2.0
83 "vdda-pll", "vdda33", "vdda18",
111 * struct qcom_snps_hsphy - snps hs phy attributes
114 * @base: iomapped memory space for snps hs phy
121 * @phy_initialized: if PHY has been initialized correctly
154 dev_dbg(&hsphy->phy->dev, "Suspend QCOM SNPS PHY\n"); in qcom_snps_hsphy_suspend()
156 if (hsphy->mode == PHY_MODE_USB_HOST) { in qcom_snps_hsphy_suspend()
157 /* Enable auto-resume to meet remote wakeup timing */ in qcom_snps_hsphy_suspend()
158 qcom_snps_hsphy_write_mask(hsphy->base, in qcom_snps_hsphy_suspend()
163 qcom_snps_hsphy_write_mask(hsphy->base, in qcom_snps_hsphy_suspend()
[all …]
/Linux-v6.1/drivers/usb/host/
Dehci-xilinx-of.c1 // SPDX-License-Identifier: GPL-2.0+
3 * EHCI HCD (Host Controller Driver) for USB.
9 * Based on "ehci-ppc-of.c" by Valentine Barshak <vbarshak@ru.mvista.com>
10 * and "ehci-ppc-soc.c" by Stefan Roese <sr@denx.de>
11 * and "ohci-ppc-of.c" by Sylvain Munaut <tnt@246tNt.com>
23 * ehci_xilinx_port_handed_over - hand the port out if failed to enable it
27 * This function is used as a place to tell the user that the Xilinx USB host
28 * controller does support LS devices. And in an HS only configuration, it
34 * the USB bus. In those cases, the messages printed here are not helpful.
40 dev_warn(hcd->self.controller, "port %d cannot be enabled\n", portnum); in ehci_xilinx_port_handed_over()
[all …]
/Linux-v6.1/drivers/usb/cdns3/
Dcdns3-gadget.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2018-2019 Cadence.
6 * Copyright (C) 2017-2018 NXP
14 #include <linux/usb/gadget.h>
15 #include <linux/dma-direction.h>
18 * USBSS-DEV register interface.
23 * struct cdns3_usb_regs - device controller registers.
29 * @usb_ien: USB Interrupt Enable.
30 * @usb_ists: USB Interrupt Status.
53 * @buf_addr: Address for On-chip Buffer operations.
[all …]
DKconfig2 tristate "Cadence USB Support"
3 depends on USB_SUPPORT && (USB || USB_GADGET) && HAS_DMA
4 select USB_XHCI_PLATFORM if USB_XHCI_HCD
7 Say Y here if your system has a Cadence USBSS or USBSSP
8 dual-role controller.
9 It supports: dual-role switch, Host-only, and Peripheral-only.
14 if USB_CDNS_SUPPORT
17 tristate "Cadence USB3 Dual-Role Controller"
20 Say Y here if your system has a Cadence USB3 dual-role controller.
21 It supports: dual-role switch, Host-only, and Peripheral-only.
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/usb/
Dmediatek,mtu3.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/usb/mediatek,mtu3.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Chunfeng Yun <chunfeng.yun@mediatek.com>
14 - $ref: "usb-drd.yaml"
23 - enum:
24 - mediatek,mt2712-mtu3
25 - mediatek,mt8173-mtu3
26 - mediatek,mt8183-mtu3
[all …]
Dsnps,dwc3.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/usb/snps,dwc3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Felipe Balbi <balbi@kernel.org>
14 be presented as a standalone DT node with an optional vendor-specific
18 - $ref: usb-drd.yaml#
19 - if:
25 - dr_mode
27 $ref: usb.yaml#
[all …]
Dqcom,dwc3.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/qcom,dwc3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SuperSpeed DWC3 USB SoC controller
10 - Wesley Cheng <quic_wcheng@quicinc.com>
15 - enum:
16 - qcom,ipq4019-dwc3
17 - qcom,ipq6018-dwc3
18 - qcom,ipq8064-dwc3
[all …]
Dci-hdrc-usb2.txt1 * USB2 ChipIdea USB controller for ci13xxx
4 - compatible: should be one of:
5 "fsl,imx23-usb"
6 "fsl,imx27-usb"
7 "fsl,imx28-usb"
8 "fsl,imx6q-usb"
9 "fsl,imx6sl-usb"
10 "fsl,imx6sx-usb"
11 "fsl,imx6ul-usb"
12 "fsl,imx7d-usb"
[all …]
Dehci-omap.txt1 OMAP HS USB EHCI controller
3 This device is usually the child of the omap-usb-host
4 Documentation/devicetree/bindings/mfd/omap-usb-host.txt
8 - compatible: should be "ti,ehci-omap"
9 - reg: should contain one register range i.e. start and length
10 - interrupts: description of the interrupt line
14 - phys: list of phandles to PHY nodes.
15 This property is required if at least one of the ports are in
19 Documentation/devicetree/bindings/mfd/omap-usb-host.txt
24 compatible = "ti,ehci-omap";
/Linux-v6.1/Documentation/devicetree/bindings/connector/
Dusb-connector.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/connector/usb-connector.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: USB Connector
10 - Rob Herring <robh@kernel.org>
13 A USB connector node represents a physical USB connector. It should be a child
14 of a USB interface controller or a separate node when it is attached to both
15 MUX and USB interface controller.
20 - enum:
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/mfd/
Domap-usb-host.txt1 OMAP HS USB Host
5 - compatible: should be "ti,usbhs-host"
6 - reg: should contain one register range i.e. start and length
7 - ti,hwmods: must contain "usb_host_hs"
11 - num-ports: number of USB ports. Usually this is automatically detected
15 - portN-mode: String specifying the port mode for port N, where N can be
16 from 1 to 3. If the port mode is not specified, that port is treated
18 "ehci-phy",
19 "ehci-tll",
20 "ehci-hsic",
[all …]
/Linux-v6.1/drivers/usb/gadget/legacy/
Daudio.c1 // SPDX-License-Identifier: GPL-2.0+
3 * audio.c -- Audio gadget driver
13 #include <linux/usb/composite.h>
15 #define DRIVER_DESC "Linux USB Audio Gadget"
23 /* Playback(USB-IN) Default Stereo - Fl/Fr */
39 /* Playback bInterval for HS/SS (1-4: fixed, 0: auto) */
43 "Playback bInterval for HS/SS (1-4: fixed, 0: auto)");
45 /* Capture(USB-OUT) Default Stereo - Fl/Fr */
61 /* capture bInterval for HS/SS (1-4: fixed, 0: auto) */
65 "Capture bInterval for HS/SS (1-4: fixed, 0: auto)");
[all …]
/Linux-v6.1/drivers/usb/gadget/
Dconfig.c1 // SPDX-License-Identifier: GPL-2.0+
3 * usb/gadget/config.c -- simplify building config descriptors
16 #include <linux/usb/ch9.h>
17 #include <linux/usb/gadget.h>
18 #include <linux/usb/composite.h>
19 #include <linux/usb/otg.h>
22 * usb_descriptor_fillbuf - fill buffer with descriptors
28 * negative error code if they can't all be copied. Useful when
39 if (!src) in usb_descriptor_fillbuf()
40 return -EINVAL; in usb_descriptor_fillbuf()
[all …]
/Linux-v6.1/drivers/usb/dwc2/
Dpci.c1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * pci.c - DesignWare HS OTG Controller PCI driver
5 * Copyright (C) 2004-2013 Synopsys, Inc.
20 #include <linux/usb.h>
22 #include <linux/usb/hcd.h>
23 #include <linux/usb/ch11.h>
25 #include <linux/usb/usb_phy_generic.h>
29 static const char dwc2_driver_name[] = "dwc2-pci";
37 * dwc2_pci_remove() - Provides the cleanup entry points for the DWC_otg PCI
46 platform_device_unregister(glue->dwc2); in dwc2_pci_remove()
[all …]
Dgadget.c1 // SPDX-License-Identifier: GPL-2.0
11 * S3C USB2.0 High-speed / OtG driver
19 #include <linux/dma-mapping.h>
27 #include <linux/usb/ch9.h>
28 #include <linux/usb/gadget.h>
29 #include <linux/usb/phy.h>
30 #include <linux/usb/composite.h>
65 if (dir_in) in index_to_ep()
66 return hsotg->eps_in[ep_index]; in index_to_ep()
68 return hsotg->eps_out[ep_index]; in index_to_ep()
[all …]
/Linux-v6.1/drivers/usb/dwc3/
Ddwc3-qcom.c1 // SPDX-License-Identifier: GPL-2.0
4 * Inspired by dwc3-of-simple.c
20 #include <linux/usb/of.h>
23 #include <linux/usb/hcd.h>
24 #include <linux/usb.h>
27 /* USB QSCRATCH Hardware registers */
122 if (enable) { in dwc3_qcom_vbus_override_enable()
123 dwc3_qcom_setbits(qcom->qscratch_base, QSCRATCH_SS_PHY_CTRL, in dwc3_qcom_vbus_override_enable()
125 dwc3_qcom_setbits(qcom->qscratch_base, QSCRATCH_HS_PHY_CTRL, in dwc3_qcom_vbus_override_enable()
128 dwc3_qcom_clrbits(qcom->qscratch_base, QSCRATCH_SS_PHY_CTRL, in dwc3_qcom_vbus_override_enable()
[all …]

1234567