1 // SPDX-License-Identifier: GPL-2.0
83 	"vdda-pll", "vdda33", "vdda18",
111  * struct qcom_snps_hsphy - snps hs phy attributes
114  * @base: iomapped memory space for snps hs phy
121  * @phy_initialized: if PHY has been initialized correctly
154 	dev_dbg(&hsphy->phy->dev, "Suspend QCOM SNPS PHY\n");  in qcom_snps_hsphy_suspend()
156 	if (hsphy->mode == PHY_MODE_USB_HOST) {  in qcom_snps_hsphy_suspend()
157 		/* Enable auto-resume to meet remote wakeup timing */  in qcom_snps_hsphy_suspend()
158 		qcom_snps_hsphy_write_mask(hsphy->base,  in qcom_snps_hsphy_suspend()
163 		qcom_snps_hsphy_write_mask(hsphy->base,  in qcom_snps_hsphy_suspend()
168 	clk_disable_unprepare(hsphy->cfg_ahb_clk);  in qcom_snps_hsphy_suspend()
176 	dev_dbg(&hsphy->phy->dev, "Resume QCOM SNPS PHY, mode\n");  in qcom_snps_hsphy_resume()
178 	ret = clk_prepare_enable(hsphy->cfg_ahb_clk);  in qcom_snps_hsphy_resume()
179 	if (ret) {  in qcom_snps_hsphy_resume()
180 		dev_err(&hsphy->phy->dev, "failed to enable cfg ahb clock\n");  in qcom_snps_hsphy_resume()
191 	if (!hsphy->phy_initialized)  in qcom_snps_hsphy_runtime_suspend()
202 	if (!hsphy->phy_initialized)  in qcom_snps_hsphy_runtime_resume()
214 	hsphy->mode = mode;  in qcom_snps_hsphy_set_mode()
219 	{ -272, 0 },
230 	{ -2090, 7 },
231 	{ -1560, 6 },
232 	{ -1030, 5 },
233 	{ -530, 4 },
241 	{ -660, 0 },
242 	{ -440, 1 },
243 	{ -220, 2 },
272 	{ -4100, 3 },
279 	{ -31000, 1 },
285 	{ -2300000, 3 },
292 	{ -1053, 15 },
293 	{ -557, 7 },
301 		"qcom,hs-disconnect-bp",
308 		"qcom,squelch-detector-bp",
315 		"qcom,hs-amplitude-bp",
322 		"qcom,pre-emphasis-duration-bp",
329 		"qcom,pre-emphasis-amplitude-bp",
336 		"qcom,hs-rise-fall-time-bp",
343 		"qcom,hs-crossover-voltage-microvolt",
350 		"qcom,hs-output-impedance-micro-ohms",
357 		"qcom,ls-fs-output-impedance-bp",
371 	dev_vdbg(&phy->dev, "%s(): Initializing SNPS HS phy\n", __func__);  in qcom_snps_hsphy_init()
373 	ret = regulator_bulk_enable(ARRAY_SIZE(hsphy->vregs), hsphy->vregs);  in qcom_snps_hsphy_init()
374 	if (ret)  in qcom_snps_hsphy_init()
377 	ret = clk_prepare_enable(hsphy->cfg_ahb_clk);  in qcom_snps_hsphy_init()
378 	if (ret) {  in qcom_snps_hsphy_init()
379 		dev_err(&phy->dev, "failed to enable cfg ahb clock, %d\n", ret);  in qcom_snps_hsphy_init()
383 	ret = reset_control_assert(hsphy->phy_reset);  in qcom_snps_hsphy_init()
384 	if (ret) {  in qcom_snps_hsphy_init()
385 		dev_err(&phy->dev, "failed to assert phy_reset, %d\n", ret);  in qcom_snps_hsphy_init()
391 	ret = reset_control_deassert(hsphy->phy_reset);  in qcom_snps_hsphy_init()
392 	if (ret) {  in qcom_snps_hsphy_init()
393 		dev_err(&phy->dev, "failed to de-assert phy_reset, %d\n", ret);  in qcom_snps_hsphy_init()
397 	qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_CFG0,  in qcom_snps_hsphy_init()
400 	qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_UTMI_CTRL5,  in qcom_snps_hsphy_init()
402 	qcom_snps_hsphy_write_mask(hsphy->base,  in qcom_snps_hsphy_init()
405 	qcom_snps_hsphy_write_mask(hsphy->base,  in qcom_snps_hsphy_init()
408 	qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_REFCLK_CTRL,  in qcom_snps_hsphy_init()
410 	qcom_snps_hsphy_write_mask(hsphy->base,  in qcom_snps_hsphy_init()
413 	qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_HS_PHY_CTRL1,  in qcom_snps_hsphy_init()
416 	for (i = 0; i < ARRAY_SIZE(hsphy->update_seq_cfg); i++) {  in qcom_snps_hsphy_init()
417 		if (hsphy->update_seq_cfg[i].need_update)  in qcom_snps_hsphy_init()
418 			qcom_snps_hsphy_write_mask(hsphy->base,  in qcom_snps_hsphy_init()
419 					hsphy->update_seq_cfg[i].offset,  in qcom_snps_hsphy_init()
420 					hsphy->update_seq_cfg[i].mask,  in qcom_snps_hsphy_init()
421 					hsphy->update_seq_cfg[i].value);  in qcom_snps_hsphy_init()
424 	qcom_snps_hsphy_write_mask(hsphy->base,  in qcom_snps_hsphy_init()
428 	qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_HS_PHY_CTRL2,  in qcom_snps_hsphy_init()
432 	qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_UTMI_CTRL0,  in qcom_snps_hsphy_init()
435 	qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON0,  in qcom_snps_hsphy_init()
438 	qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_UTMI_CTRL5,  in qcom_snps_hsphy_init()
441 	qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_HS_PHY_CTRL2,  in qcom_snps_hsphy_init()
444 	qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_CFG0,  in qcom_snps_hsphy_init()
447 	hsphy->phy_initialized = true;  in qcom_snps_hsphy_init()
452 	clk_disable_unprepare(hsphy->cfg_ahb_clk);  in qcom_snps_hsphy_init()
454 	regulator_bulk_disable(ARRAY_SIZE(hsphy->vregs), hsphy->vregs);  in qcom_snps_hsphy_init()
463 	reset_control_assert(hsphy->phy_reset);  in qcom_snps_hsphy_exit()
464 	clk_disable_unprepare(hsphy->cfg_ahb_clk);  in qcom_snps_hsphy_exit()
465 	regulator_bulk_disable(ARRAY_SIZE(hsphy->vregs), hsphy->vregs);  in qcom_snps_hsphy_exit()
466 	hsphy->phy_initialized = false;  in qcom_snps_hsphy_exit()
479 	{ .compatible	= "qcom,sm8150-usb-hs-phy", },
480 	{ .compatible	= "qcom,usb-snps-hs-5nm-phy", },
482 		.compatible	= "qcom,usb-snps-hs-7nm-phy",
485 	{ .compatible	= "qcom,usb-snps-femto-v2-phy",	},
507 	for (i = 0; i < map.table_size - 1; i++) {  in qcom_snps_hsphy_override_param_update_val()
508 		if (map.param_table[i].value == dt_val)  in qcom_snps_hsphy_override_param_update_val()
512 	seq_entry->need_update = true;  in qcom_snps_hsphy_override_param_update_val()
513 	seq_entry->offset = map.reg_offset;  in qcom_snps_hsphy_override_param_update_val()
514 	seq_entry->mask = map.param_mask;  in qcom_snps_hsphy_override_param_update_val()
515 	seq_entry->value = map.param_table[i].reg_val << __ffs(map.param_mask);  in qcom_snps_hsphy_override_param_update_val()
520 	struct device_node *node = dev->of_node;  in qcom_snps_hsphy_read_override_param_seq()
526 	if (!cfg)  in qcom_snps_hsphy_read_override_param_seq()
533 		if (ret)  in qcom_snps_hsphy_read_override_param_seq()
537 					&hsphy->update_seq_cfg[i]);  in qcom_snps_hsphy_read_override_param_seq()
538 		dev_dbg(&hsphy->phy->dev, "Read param: %s dt_val: %d reg_val: 0x%x\n",  in qcom_snps_hsphy_read_override_param_seq()
539 			cfg[i].prop_name, val, hsphy->update_seq_cfg[i].value);  in qcom_snps_hsphy_read_override_param_seq()
546 	struct device *dev = &pdev->dev;  in qcom_snps_hsphy_probe()
554 	if (!hsphy)  in qcom_snps_hsphy_probe()
555 		return -ENOMEM;  in qcom_snps_hsphy_probe()
557 	hsphy->base = devm_platform_ioremap_resource(pdev, 0);  in qcom_snps_hsphy_probe()
558 	if (IS_ERR(hsphy->base))  in qcom_snps_hsphy_probe()
559 		return PTR_ERR(hsphy->base);  in qcom_snps_hsphy_probe()
561 	hsphy->ref_clk = devm_clk_get(dev, "ref");  in qcom_snps_hsphy_probe()
562 	if (IS_ERR(hsphy->ref_clk))  in qcom_snps_hsphy_probe()
563 		return dev_err_probe(dev, PTR_ERR(hsphy->ref_clk),  in qcom_snps_hsphy_probe()
566 	hsphy->phy_reset = devm_reset_control_get_exclusive(&pdev->dev, NULL);  in qcom_snps_hsphy_probe()
567 	if (IS_ERR(hsphy->phy_reset)) {  in qcom_snps_hsphy_probe()
569 		return PTR_ERR(hsphy->phy_reset);  in qcom_snps_hsphy_probe()
572 	num = ARRAY_SIZE(hsphy->vregs);  in qcom_snps_hsphy_probe()
574 		hsphy->vregs[i].supply = qcom_snps_hsphy_vreg_names[i];  in qcom_snps_hsphy_probe()
576 	ret = devm_regulator_bulk_get(dev, num, hsphy->vregs);  in qcom_snps_hsphy_probe()
577 	if (ret)  in qcom_snps_hsphy_probe()
590 	if (IS_ERR(generic_phy)) {  in qcom_snps_hsphy_probe()
595 	hsphy->phy = generic_phy;  in qcom_snps_hsphy_probe()
602 	if (!IS_ERR(phy_provider))  in qcom_snps_hsphy_probe()
603 		dev_dbg(dev, "Registered Qcom-SNPS HS phy\n");  in qcom_snps_hsphy_probe()
613 		.name	= "qcom-snps-hs-femto-v2-phy",
621 MODULE_DESCRIPTION("Qualcomm SNPS FEMTO USB HS PHY V2 driver");