Lines Matching +full:hs +full:- +full:usb +full:- +full:if
1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/qcom,dwc3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SuperSpeed DWC3 USB SoC controller
10 - Wesley Cheng <quic_wcheng@quicinc.com>
15 - enum:
16 - qcom,ipq4019-dwc3
17 - qcom,ipq6018-dwc3
18 - qcom,ipq8064-dwc3
19 - qcom,ipq8074-dwc3
20 - qcom,msm8953-dwc3
21 - qcom,msm8994-dwc3
22 - qcom,msm8996-dwc3
23 - qcom,msm8998-dwc3
24 - qcom,qcs404-dwc3
25 - qcom,sc7180-dwc3
26 - qcom,sc7280-dwc3
27 - qcom,sc8280xp-dwc3
28 - qcom,sdm660-dwc3
29 - qcom,sdm670-dwc3
30 - qcom,sdm845-dwc3
31 - qcom,sdx55-dwc3
32 - qcom,sdx65-dwc3
33 - qcom,sm4250-dwc3
34 - qcom,sm6115-dwc3
35 - qcom,sm6125-dwc3
36 - qcom,sm6350-dwc3
37 - qcom,sm6375-dwc3
38 - qcom,sm8150-dwc3
39 - qcom,sm8250-dwc3
40 - qcom,sm8350-dwc3
41 - qcom,sm8450-dwc3
42 - const: qcom,dwc3
48 "#address-cells":
51 "#size-cells":
56 power-domains:
63 - cfg_noc:: System Config NOC clock.
64 - core:: Master/Core clock, has to be >= 125 MHz for SS operation and >=
65 60MHz for HS operation.
66 - iface:: System bus AXI clock.
67 - sleep:: Sleep clock, used for wakeup when USB3 core goes into low
69 - mock_utmi:: Mock utmi clock needed for ITP/SOF generation in host
74 clock-names:
78 assigned-clocks:
80 - description: Phandle and clock specifier of MOCK_UTMI_CLK.
81 - description: Phandle and clock specifoer of MASTER_CLK.
83 assigned-clock-rates:
85 - description: Must be 19.2MHz (19200000).
86 - description: Must be >= 60 MHz in HS mode, >= 125 MHz in SS mode.
93 interconnect-names:
95 - const: usb-ddr
96 - const: apps-usb
102 interrupt-names:
106 qcom,select-utmi-as-pipe-clk:
108 If present, disable USB3 pipe_clk requirement.
110 HS/FS/LS modes are supported.
113 wakeup-source: true
118 "^usb@[0-9a-f]+$":
122 wakeup-source: false
125 - compatible
126 - reg
127 - "#address-cells"
128 - "#size-cells"
129 - ranges
130 - power-domains
131 - clocks
132 - clock-names
133 - interrupts
134 - interrupt-names
137 - if:
142 - qcom,ipq4019-dwc3
147 clock-names:
149 - const: core
150 - const: sleep
151 - const: mock_utmi
153 - if:
158 - qcom,ipq8064-dwc3
163 - description: Master/Core clock, has to be >= 125 MHz
164 for SS operation and >= 60MHz for HS operation.
165 clock-names:
167 - const: core
169 - if:
174 - qcom,msm8953-dwc3
175 - qcom,msm8996-dwc3
176 - qcom,msm8998-dwc3
177 - qcom,sc7180-dwc3
178 - qcom,sc7280-dwc3
179 - qcom,sdm670-dwc3
180 - qcom,sdm845-dwc3
181 - qcom,sdx55-dwc3
182 - qcom,sm6350-dwc3
187 clock-names:
189 - const: cfg_noc
190 - const: core
191 - const: iface
192 - const: sleep
193 - const: mock_utmi
195 - if:
200 - qcom,ipq6018-dwc3
206 clock-names:
208 - items:
209 - const: core
210 - const: sleep
211 - const: mock_utmi
212 - items:
213 - const: cfg_noc
214 - const: core
215 - const: sleep
216 - const: mock_utmi
218 - if:
223 - qcom,ipq8074-dwc3
228 clock-names:
230 - const: cfg_noc
231 - const: core
232 - const: sleep
233 - const: mock_utmi
235 - if:
240 - qcom,msm8994-dwc3
241 - qcom,qcs404-dwc3
246 clock-names:
248 - const: core
249 - const: iface
250 - const: sleep
251 - const: mock_utmi
253 - if:
258 - qcom,sc8280xp-dwc3
263 clock-names:
265 - const: cfg_noc
266 - const: core
267 - const: iface
268 - const: sleep
269 - const: mock_utmi
270 - const: noc_aggr
271 - const: noc_aggr_north
272 - const: noc_aggr_south
273 - const: noc_sys
275 - if:
280 - qcom,sdm660-dwc3
285 clock-names:
287 - const: cfg_noc
288 - const: core
289 - const: iface
290 - const: sleep
291 - const: mock_utmi
292 - const: bus
294 - if:
299 - qcom,sm6115-dwc3
300 - qcom,sm6125-dwc3
301 - qcom,sm8150-dwc3
302 - qcom,sm8250-dwc3
303 - qcom,sm8450-dwc3
308 clock-names:
310 - const: cfg_noc
311 - const: core
312 - const: iface
313 - const: sleep
314 - const: mock_utmi
315 - const: xo
317 - if:
322 - qcom,sm8350-dwc3
328 clock-names:
331 - const: cfg_noc
332 - const: core
333 - const: iface
334 - const: sleep
335 - const: mock_utmi
336 - const: xo
338 - if:
343 - qcom,ipq4019-dwc3
344 - qcom,ipq6018-dwc3
345 - qcom,ipq8064-dwc3
346 - qcom,ipq8074-dwc3
347 - qcom,msm8994-dwc3
348 - qcom,qcs404-dwc3
349 - qcom,sc7180-dwc3
350 - qcom,sdm670-dwc3
351 - qcom,sdm845-dwc3
352 - qcom,sdx55-dwc3
353 - qcom,sdx65-dwc3
354 - qcom,sm4250-dwc3
355 - qcom,sm6125-dwc3
356 - qcom,sm6350-dwc3
357 - qcom,sm8150-dwc3
358 - qcom,sm8250-dwc3
359 - qcom,sm8350-dwc3
360 - qcom,sm8450-dwc3
365 - description: The interrupt that is asserted
367 - description: The interrupt that is asserted
369 - description: Wakeup event on DM line.
370 - description: Wakeup event on DP line.
371 interrupt-names:
373 - const: hs_phy_irq
374 - const: ss_phy_irq
375 - const: dm_hs_phy_irq
376 - const: dp_hs_phy_irq
378 - if:
383 - qcom,msm8953-dwc3
384 - qcom,msm8996-dwc3
385 - qcom,msm8998-dwc3
386 - qcom,sm6115-dwc3
391 interrupt-names:
393 - const: hs_phy_irq
394 - const: ss_phy_irq
396 - if:
401 - qcom,sdm660-dwc3
407 interrupt-names:
410 - const: hs_phy_irq
411 - const: ss_phy_irq
413 - if:
418 - qcom,sc7280-dwc3
424 interrupt-names:
427 - const: hs_phy_irq
428 - const: dp_hs_phy_irq
429 - const: dm_hs_phy_irq
430 - const: ss_phy_irq
432 - if:
437 - qcom,sc8280xp-dwc3
442 interrupt-names:
444 - const: pwr_event
445 - const: dp_hs_phy_irq
446 - const: dm_hs_phy_irq
447 - const: ss_phy_irq
452 - |
453 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
454 #include <dt-bindings/interrupt-controller/arm-gic.h>
455 #include <dt-bindings/interrupt-controller/irq.h>
457 #address-cells = <2>;
458 #size-cells = <2>;
460 usb@a6f8800 {
461 compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
464 #address-cells = <2>;
465 #size-cells = <2>;
472 clock-names = "cfg_noc",
478 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
480 assigned-clock-rates = <19200000>, <150000000>;
486 interrupt-names = "hs_phy_irq", "ss_phy_irq",
489 power-domains = <&gcc USB30_PRIM_GDSC>;
493 usb@a600000 {
501 phy-names = "usb2-phy", "usb3-phy";