Lines Matching +full:hs +full:- +full:usb +full:- +full:if
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/socionext,uniphier-usb3hs-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier USB3 High-Speed (HS) PHY
12 Although the controller includes High-Speed PHY and Super-Speed PHY,
13 this describes about High-Speed PHY.
16 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
21 - socionext,uniphier-pro5-usb3-hsphy
22 - socionext,uniphier-pxs2-usb3-hsphy
23 - socionext,uniphier-ld20-usb3-hsphy
24 - socionext,uniphier-pxs3-usb3-hsphy
25 - socionext,uniphier-nx1-usb3-hsphy
30 "#phy-cells":
37 clock-names: true
42 reset-names: true
44 vbus-supply:
45 description: A phandle to the regulator for USB VBUS
47 nvmem-cells:
51 Available only for HS-PHY implemented on LD20 and PXs3, and
52 if unspecified, default value is used.
54 nvmem-cell-names:
56 - const: rterm
57 - const: sel_t
58 - const: hs_i
60 Should be the following names, which correspond to each nvmem-cells.
62 required for each port, if any one is omitted, the trimming data
66 - if:
70 const: socionext,uniphier-pro5-usb3-hsphy
76 clock-names:
78 - const: gio
79 - const: link
83 reset-names:
85 - const: gio
86 - const: link
87 - if:
92 - socionext,uniphier-pxs2-usb3-hsphy
93 - socionext,uniphier-ld20-usb3-hsphy
99 clock-names:
101 - const: link
102 - const: phy
106 reset-names:
108 - const: link
109 - const: phy
110 - if:
115 - socionext,uniphier-pxs3-usb3-hsphy
116 - socionext,uniphier-nx1-usb3-hsphy
122 clock-names:
125 - const: link
126 - const: phy
127 - const: phy-ext
131 reset-names:
133 - const: link
134 - const: phy
137 - compatible
138 - reg
139 - "#phy-cells"
140 - clocks
141 - clock-names
142 - resets
143 - reset-names
148 - |
149 usb-glue@65b00000 {
150 compatible = "socionext,uniphier-ld20-dwc3-glue", "simple-mfd";
151 #address-cells = <1>;
152 #size-cells = <1>;
155 usb_hsphy0: hs-phy@200 {
156 compatible = "socionext,uniphier-ld20-usb3-hsphy";
158 #phy-cells = <0>;
159 clock-names = "link", "phy";
161 reset-names = "link", "phy";
163 vbus-supply = <&usb_vbus0>;
164 nvmem-cell-names = "rterm", "sel_t", "hs_i";
165 nvmem-cells = <&usb_rterm0>, <&usb_sel_t0>, <&usb_hs_i0>;