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/Linux-v6.1/drivers/gpu/drm/amd/amdgpu/
Damdgpu_rlc.c39 if (adev->gfx.rlc.in_safe_mode) in amdgpu_gfx_rlc_enter_safe_mode()
43 if (!adev->gfx.rlc.funcs->is_rlc_enabled(adev)) in amdgpu_gfx_rlc_enter_safe_mode()
49 adev->gfx.rlc.funcs->set_safe_mode(adev); in amdgpu_gfx_rlc_enter_safe_mode()
50 adev->gfx.rlc.in_safe_mode = true; in amdgpu_gfx_rlc_enter_safe_mode()
63 if (!(adev->gfx.rlc.in_safe_mode)) in amdgpu_gfx_rlc_exit_safe_mode()
67 if (!adev->gfx.rlc.funcs->is_rlc_enabled(adev)) in amdgpu_gfx_rlc_exit_safe_mode()
73 adev->gfx.rlc.funcs->unset_safe_mode(adev); in amdgpu_gfx_rlc_exit_safe_mode()
74 adev->gfx.rlc.in_safe_mode = false; in amdgpu_gfx_rlc_exit_safe_mode()
97 &adev->gfx.rlc.save_restore_obj, in amdgpu_gfx_rlc_init_sr()
98 &adev->gfx.rlc.save_restore_gpu_addr, in amdgpu_gfx_rlc_init_sr()
[all …]
Damdgpu_gfx.c32 /* delay 0.1 second to enable gfx off feature */
38 * GPU GFX IP block helpers function.
46 bit += mec * adev->gfx.mec.num_pipe_per_mec in amdgpu_gfx_mec_queue_to_bit()
47 * adev->gfx.mec.num_queue_per_pipe; in amdgpu_gfx_mec_queue_to_bit()
48 bit += pipe * adev->gfx.mec.num_queue_per_pipe; in amdgpu_gfx_mec_queue_to_bit()
57 *queue = bit % adev->gfx.mec.num_queue_per_pipe; in amdgpu_queue_mask_bit_to_mec_queue()
58 *pipe = (bit / adev->gfx.mec.num_queue_per_pipe) in amdgpu_queue_mask_bit_to_mec_queue()
59 % adev->gfx.mec.num_pipe_per_mec; in amdgpu_queue_mask_bit_to_mec_queue()
60 *mec = (bit / adev->gfx.mec.num_queue_per_pipe) in amdgpu_queue_mask_bit_to_mec_queue()
61 / adev->gfx.mec.num_pipe_per_mec; in amdgpu_queue_mask_bit_to_mec_queue()
[all …]
Dgfx_v6_0.c341 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); in gfx_v6_0_init_microcode()
344 err = amdgpu_ucode_validate(adev->gfx.pfp_fw); in gfx_v6_0_init_microcode()
347 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; in gfx_v6_0_init_microcode()
348 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); in gfx_v6_0_init_microcode()
349 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); in gfx_v6_0_init_microcode()
352 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); in gfx_v6_0_init_microcode()
355 err = amdgpu_ucode_validate(adev->gfx.me_fw); in gfx_v6_0_init_microcode()
358 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; in gfx_v6_0_init_microcode()
359 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); in gfx_v6_0_init_microcode()
360 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); in gfx_v6_0_init_microcode()
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Dgfx_v11_0.c42 #include "ivsrcid/gfx/irqsrcs_gfx_11_0_0.h"
190 if (adev->enable_mes && !adev->gfx.kiq.ring.sched.ready) { in gfx11_kiq_unmap_queues()
258 adev->gfx.kiq.pmf = &gfx_v11_0_kiq_pm4_funcs; in gfx_v11_0_set_kiq_pm4_funcs()
429 release_firmware(adev->gfx.pfp_fw); in gfx_v11_0_free_microcode()
430 adev->gfx.pfp_fw = NULL; in gfx_v11_0_free_microcode()
431 release_firmware(adev->gfx.me_fw); in gfx_v11_0_free_microcode()
432 adev->gfx.me_fw = NULL; in gfx_v11_0_free_microcode()
433 release_firmware(adev->gfx.rlc_fw); in gfx_v11_0_free_microcode()
434 adev->gfx.rlc_fw = NULL; in gfx_v11_0_free_microcode()
435 release_firmware(adev->gfx.mec_fw); in gfx_v11_0_free_microcode()
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Dgfx_v7_0.c930 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); in gfx_v7_0_init_microcode()
933 err = amdgpu_ucode_validate(adev->gfx.pfp_fw); in gfx_v7_0_init_microcode()
938 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); in gfx_v7_0_init_microcode()
941 err = amdgpu_ucode_validate(adev->gfx.me_fw); in gfx_v7_0_init_microcode()
946 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); in gfx_v7_0_init_microcode()
949 err = amdgpu_ucode_validate(adev->gfx.ce_fw); in gfx_v7_0_init_microcode()
954 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); in gfx_v7_0_init_microcode()
957 err = amdgpu_ucode_validate(adev->gfx.mec_fw); in gfx_v7_0_init_microcode()
963 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); in gfx_v7_0_init_microcode()
966 err = amdgpu_ucode_validate(adev->gfx.mec2_fw); in gfx_v7_0_init_microcode()
[all …]
Dgfx_v8_0.c927 release_firmware(adev->gfx.pfp_fw); in gfx_v8_0_free_microcode()
928 adev->gfx.pfp_fw = NULL; in gfx_v8_0_free_microcode()
929 release_firmware(adev->gfx.me_fw); in gfx_v8_0_free_microcode()
930 adev->gfx.me_fw = NULL; in gfx_v8_0_free_microcode()
931 release_firmware(adev->gfx.ce_fw); in gfx_v8_0_free_microcode()
932 adev->gfx.ce_fw = NULL; in gfx_v8_0_free_microcode()
933 release_firmware(adev->gfx.rlc_fw); in gfx_v8_0_free_microcode()
934 adev->gfx.rlc_fw = NULL; in gfx_v8_0_free_microcode()
935 release_firmware(adev->gfx.mec_fw); in gfx_v8_0_free_microcode()
936 adev->gfx.mec_fw = NULL; in gfx_v8_0_free_microcode()
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Dgfx_v9_0.c46 #include "ivsrcid/gfx/irqsrcs_gfx_9_0.h"
888 adev->gfx.kiq.pmf = &gfx_v9_0_kiq_pm4_funcs; in gfx_v9_0_set_kiq_pm4_funcs()
1078 release_firmware(adev->gfx.pfp_fw); in gfx_v9_0_free_microcode()
1079 adev->gfx.pfp_fw = NULL; in gfx_v9_0_free_microcode()
1080 release_firmware(adev->gfx.me_fw); in gfx_v9_0_free_microcode()
1081 adev->gfx.me_fw = NULL; in gfx_v9_0_free_microcode()
1082 release_firmware(adev->gfx.ce_fw); in gfx_v9_0_free_microcode()
1083 adev->gfx.ce_fw = NULL; in gfx_v9_0_free_microcode()
1084 release_firmware(adev->gfx.rlc_fw); in gfx_v9_0_free_microcode()
1085 adev->gfx.rlc_fw = NULL; in gfx_v9_0_free_microcode()
[all …]
Damdgpu_atomfirmware.c693 adev->gfx.config.max_shader_engines = gfx_info->v24.max_shader_engines; in amdgpu_atomfirmware_get_gfx_info()
694 adev->gfx.config.max_cu_per_sh = gfx_info->v24.max_cu_per_sh; in amdgpu_atomfirmware_get_gfx_info()
695 adev->gfx.config.max_sh_per_se = gfx_info->v24.max_sh_per_se; in amdgpu_atomfirmware_get_gfx_info()
696 adev->gfx.config.max_backends_per_se = gfx_info->v24.max_backends_per_se; in amdgpu_atomfirmware_get_gfx_info()
697 adev->gfx.config.max_texture_channel_caches = gfx_info->v24.max_texture_channel_caches; in amdgpu_atomfirmware_get_gfx_info()
698 adev->gfx.config.max_gprs = le16_to_cpu(gfx_info->v24.gc_num_gprs); in amdgpu_atomfirmware_get_gfx_info()
699 adev->gfx.config.max_gs_threads = gfx_info->v24.gc_num_max_gs_thds; in amdgpu_atomfirmware_get_gfx_info()
700 adev->gfx.config.gs_vgt_table_depth = gfx_info->v24.gc_gs_table_depth; in amdgpu_atomfirmware_get_gfx_info()
701 adev->gfx.config.gs_prim_buffer_depth = in amdgpu_atomfirmware_get_gfx_info()
703 adev->gfx.config.double_offchip_lds_buf = in amdgpu_atomfirmware_get_gfx_info()
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Dgfx_v10_0.c40 #include "ivsrcid/gfx/irqsrcs_gfx_10_1.h"
3571 if (adev->enable_mes && !adev->gfx.kiq.ring.sched.ready) { in gfx10_kiq_unmap_queues()
3639 adev->gfx.kiq.pmf = &gfx_v10_0_kiq_pm4_funcs; in gfx_v10_0_set_kiq_pm4_funcs()
3894 release_firmware(adev->gfx.pfp_fw); in gfx_v10_0_free_microcode()
3895 adev->gfx.pfp_fw = NULL; in gfx_v10_0_free_microcode()
3896 release_firmware(adev->gfx.me_fw); in gfx_v10_0_free_microcode()
3897 adev->gfx.me_fw = NULL; in gfx_v10_0_free_microcode()
3898 release_firmware(adev->gfx.ce_fw); in gfx_v10_0_free_microcode()
3899 adev->gfx.ce_fw = NULL; in gfx_v10_0_free_microcode()
3900 release_firmware(adev->gfx.rlc_fw); in gfx_v10_0_free_microcode()
[all …]
Damdgpu_kms.c223 fw_info->ver = adev->gfx.me_fw_version; in amdgpu_firmware_info()
224 fw_info->feature = adev->gfx.me_feature_version; in amdgpu_firmware_info()
227 fw_info->ver = adev->gfx.pfp_fw_version; in amdgpu_firmware_info()
228 fw_info->feature = adev->gfx.pfp_feature_version; in amdgpu_firmware_info()
231 fw_info->ver = adev->gfx.ce_fw_version; in amdgpu_firmware_info()
232 fw_info->feature = adev->gfx.ce_feature_version; in amdgpu_firmware_info()
235 fw_info->ver = adev->gfx.rlc_fw_version; in amdgpu_firmware_info()
236 fw_info->feature = adev->gfx.rlc_feature_version; in amdgpu_firmware_info()
239 fw_info->ver = adev->gfx.rlc_srlc_fw_version; in amdgpu_firmware_info()
240 fw_info->feature = adev->gfx.rlc_srlc_feature_version; in amdgpu_firmware_info()
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Damdgpu_ucode.c107 DRM_DEBUG("GFX\n"); in amdgpu_ucode_print_gfx_hdr()
125 DRM_ERROR("Unknown GFX ucode version: %u.%u\n", version_major, version_minor); in amdgpu_ucode_print_gfx_hdr()
138 DRM_ERROR("Unknown GFX ucode version: %u.%u\n", version_major, version_minor); in amdgpu_ucode_print_imu_hdr()
692 FW_VERSION_ATTR(me_fw_version, 0444, gfx.me_fw_version);
693 FW_VERSION_ATTR(pfp_fw_version, 0444, gfx.pfp_fw_version);
694 FW_VERSION_ATTR(ce_fw_version, 0444, gfx.ce_fw_version);
695 FW_VERSION_ATTR(rlc_fw_version, 0444, gfx.rlc_fw_version);
696 FW_VERSION_ATTR(rlc_srlc_fw_version, 0444, gfx.rlc_srlc_fw_version);
697 FW_VERSION_ATTR(rlc_srlg_fw_version, 0444, gfx.rlc_srlg_fw_version);
698 FW_VERSION_ATTR(rlc_srls_fw_version, 0444, gfx.rlc_srls_fw_version);
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Damdgpu_gfx.h28 * GFX stuff
37 /* GFX current status */
114 * GFX configurations
172 /* gfx configure feature */
327 /* gfx status */
338 /* gfx off */
341 … gfx_off_req_count; /* default 1, enable gfx off: dec 1, disable gfx off: ad…
342 struct delayed_work gfx_off_delay_work; /* async work to set gfx block off */
357 #define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev))
358 #define amdgpu_gfx_select_se_sh(adev, se, sh, instance) (adev)->gfx.funcs->select_se_sh((adev), (se…
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Damdgpu_amdkfd.c151 .num_pipe_per_mec = adev->gfx.mec.num_pipe_per_mec, in amdgpu_amdkfd_device_init()
152 .num_queue_per_pipe = adev->gfx.mec.num_queue_per_pipe, in amdgpu_amdkfd_device_init()
165 adev->gfx.mec.queue_bitmap, in amdgpu_amdkfd_device_init()
172 * adev->gfx.mec.num_pipe_per_mec in amdgpu_amdkfd_device_init()
173 * adev->gfx.mec.num_queue_per_pipe; in amdgpu_amdkfd_device_init()
399 return adev->gfx.pfp_fw_version; in amdgpu_amdkfd_get_fw_version()
402 return adev->gfx.me_fw_version; in amdgpu_amdkfd_get_fw_version()
405 return adev->gfx.ce_fw_version; in amdgpu_amdkfd_get_fw_version()
408 return adev->gfx.mec_fw_version; in amdgpu_amdkfd_get_fw_version()
411 return adev->gfx.mec2_fw_version; in amdgpu_amdkfd_get_fw_version()
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Dimu_v11_0.c52 err = request_firmware(&adev->gfx.imu_fw, fw_name, adev->dev); in imu_v11_0_init_microcode()
55 err = amdgpu_ucode_validate(adev->gfx.imu_fw); in imu_v11_0_init_microcode()
58 imu_hdr = (const struct imu_firmware_header_v1_0 *)adev->gfx.imu_fw->data; in imu_v11_0_init_microcode()
59 adev->gfx.imu_fw_version = le32_to_cpu(imu_hdr->header.ucode_version); in imu_v11_0_init_microcode()
60 //adev->gfx.imu_feature_version = le32_to_cpu(imu_hdr->ucode_feature_version); in imu_v11_0_init_microcode()
65 info->fw = adev->gfx.imu_fw; in imu_v11_0_init_microcode()
70 info->fw = adev->gfx.imu_fw; in imu_v11_0_init_microcode()
80 release_firmware(adev->gfx.imu_fw); in imu_v11_0_init_microcode()
92 if (!adev->gfx.imu_fw) in imu_v11_0_load_microcode()
95 hdr = (const struct imu_firmware_header_v1_0 *)adev->gfx.imu_fw->data; in imu_v11_0_load_microcode()
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Damdgpu_amdkfd_gfx_v9.c65 uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in acquire_queue()
66 uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); in acquire_queue()
74 unsigned int bit = pipe_id * adev->gfx.mec.num_queue_per_pipe + in get_queue_mask()
114 * need to do this twice, once for gfx and once for mmhub in kgd_gfx_v9_set_pasid_vmid_mapping()
164 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in kgd_gfx_v9_init_interrupts()
165 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); in kgd_gfx_v9_init_interrupts()
303 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; in kgd_gfx_v9_hiq_mqd_load()
312 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in kgd_gfx_v9_hiq_mqd_load()
313 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); in kgd_gfx_v9_hiq_mqd_load()
318 spin_lock(&adev->gfx.kiq.ring_lock); in kgd_gfx_v9_hiq_mqd_load()
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Damdgpu_debugfs.c130 if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) || in amdgpu_debugfs_process_reg_op()
131 (se_bank != 0xFFFFFFFF && se_bank >= adev->gfx.config.max_shader_engines)) { in amdgpu_debugfs_process_reg_op()
255 if ((rd->id.grbm.sh != 0xFFFFFFFF && rd->id.grbm.sh >= adev->gfx.config.max_sh_per_se) || in amdgpu_debugfs_regs2_op()
256 (rd->id.grbm.se != 0xFFFFFFFF && rd->id.grbm.se >= adev->gfx.config.max_shader_engines)) { in amdgpu_debugfs_regs2_op()
687 * amdgpu_debugfs_gca_config_read - Read from gfx config data
717 config[no_regs++] = adev->gfx.config.max_shader_engines; in amdgpu_debugfs_gca_config_read()
718 config[no_regs++] = adev->gfx.config.max_tile_pipes; in amdgpu_debugfs_gca_config_read()
719 config[no_regs++] = adev->gfx.config.max_cu_per_sh; in amdgpu_debugfs_gca_config_read()
720 config[no_regs++] = adev->gfx.config.max_sh_per_se; in amdgpu_debugfs_gca_config_read()
721 config[no_regs++] = adev->gfx.config.max_backends_per_se; in amdgpu_debugfs_gca_config_read()
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Damdgpu_amdkfd_gfx_v11.c57 uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in acquire_queue()
58 uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); in acquire_queue()
66 unsigned int bit = pipe_id * adev->gfx.mec.num_queue_per_pipe + in get_queue_mask()
97 pr_debug("mapping vmid %d -> pasid %d in IH block for GFX client\n", in set_pasid_vmid_mapping_v11()
109 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in init_interrupts_v11()
110 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); in init_interrupts_v11()
180 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in hqd_load_v11()
181 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); in hqd_load_v11()
263 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; in hiq_mqd_load_v11()
272 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in hiq_mqd_load_v11()
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Damdgpu_discovery.c1309 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v1.gc_num_se); in amdgpu_discovery_get_gfx_info()
1310 adev->gfx.config.max_cu_per_sh = 2 * (le32_to_cpu(gc_info->v1.gc_num_wgp0_per_sa) + in amdgpu_discovery_get_gfx_info()
1312 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v1.gc_num_sa_per_se); in amdgpu_discovery_get_gfx_info()
1313 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v1.gc_num_rb_per_se); in amdgpu_discovery_get_gfx_info()
1314 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v1.gc_num_gl2c); in amdgpu_discovery_get_gfx_info()
1315 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v1.gc_num_gprs); in amdgpu_discovery_get_gfx_info()
1316 adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v1.gc_num_max_gs_thds); in amdgpu_discovery_get_gfx_info()
1317 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v1.gc_gs_table_depth); in amdgpu_discovery_get_gfx_info()
1318 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v1.gc_gsprim_buff_depth); in amdgpu_discovery_get_gfx_info()
1319 adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v1.gc_double_offchip_lds_buffer); in amdgpu_discovery_get_gfx_info()
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/gpu/
Daspeed-gfx.txt1 Device tree configuration for the GFX display device on the ASPEED SoCs
6 + aspeed,ast2500-gfx
7 + aspeed,ast2400-gfx
11 - reg: Physical base address and length of the GFX registers
13 - interrupts: interrupt number for the GFX device
17 - resets: reset line that must be released to use the GFX device
26 gfx: display@1e6e6000 {
27 compatible = "aspeed,ast2500-gfx", "syscon";
/Linux-v6.1/Documentation/devicetree/bindings/mfd/
Daspeed-gfx.txt1 * Device tree bindings for Aspeed SoC Display Controller (GFX)
8 - compatible: "aspeed,ast2500-gfx", "syscon"
9 - reg: contains offset/length value of the GFX memory
14 gfx: display@1e6e6000 {
15 compatible = "aspeed,ast2500-gfx", "syscon";
/Linux-v6.1/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/
Dsmu_v13_0_1_ppsmc.h55 #define PPSMC_MSG_ForcePowerDownGfx 0x0B ///< Force power down GFX, i.e. enter GFXOFF
56 #define PPSMC_MSG_PrepareMp1ForUnload 0x0C ///< Prepare PMFW for GFX driver unload
61 #define PPSMC_MSG_GfxDeviceDriverReset 0x11 ///< Request GFX mode 2 reset
67 #define PPSMC_MSG_GetGfxclkFrequency 0x17 ///< Get GFX clock frequency
71 #define PPSMC_MSG_SetSoftMaxGfxClk 0x1B ///< Set soft max for GFX CLK
72 #define PPSMC_MSG_SetHardMinGfxClk 0x1C ///< Set hard min for GFX CLK
83 #define PPSMC_MSG_RequestActiveWgp 0x27 ///< Request GFX active WGP number
Dsmu_v13_0_4_ppsmc.h65 #define PPSMC_MSG_PrepareMp1ForUnload 0x0C ///< Prepare PMFW for GFX driver unload
70 #define PPSMC_MSG_GfxDeviceDriverReset 0x11 ///< Request GFX mode 2 reset
76 #define PPSMC_MSG_EnableGfxImu 0x16 ///< Enable GFX IMU
78 #define PPSMC_MSG_GetGfxclkFrequency 0x17 ///< Get GFX clock frequency
82 #define PPSMC_MSG_SetSoftMaxGfxClk 0x1B ///< Set soft max for GFX CLK
83 #define PPSMC_MSG_SetHardMinGfxClk 0x1C ///< Set hard min for GFX CLK
/Linux-v6.1/Documentation/gpu/amdgpu/
Ddriver-core.rst84 GFX/Compute pipeline. Consists mainly of a bunch of microcontrollers
86 provides the driver interface to interact with the GFX/Compute engine.
90 GFX/compute engine.
96 This is another microcontroller in the GFX/Compute engine. It handles
97 power management related functionality within the GFX/Compute engine.
111 This is a control queue used by the kernel driver to manage other gfx
112 and compute queues on the GFX/compute engine. You can use it to
/Linux-v6.1/drivers/soc/qcom/
Drpmhpd.c105 static struct rpmhpd gfx = { variable
106 .pd = { .name = "gfx", },
107 .res_name = "gfx.lvl",
198 [SC8280XP_GFX] = &gfx,
218 [SDM845_GFX] = &gfx,
261 [SM6350_GFX] = &gfx,
278 [SM8150_GFX] = &gfx,
298 [SM8250_GFX] = &gfx,
317 [SM8350_GFX] = &gfx,
339 [SM8450_GFX] = &gfx,
[all …]
/Linux-v6.1/drivers/gpu/drm/aspeed/
Daspeed_gfx_drv.c31 * DOC: ASPEED GFX Driver
33 * This driver is for the ASPEED BMC SoC's 'GFX' display hardware, also called
94 { .compatible = "aspeed,ast2400-gfx", .data = &ast2400_config },
95 { .compatible = "aspeed,ast2500-gfx", .data = &ast2500_config },
96 { .compatible = "aspeed,ast2600-gfx", .data = &ast2600_config },
232 aspeed_gfx_irq_handler, 0, "aspeed gfx", drm); in aspeed_gfx_load()
254 .name = "aspeed-gfx-drm",
255 .desc = "ASPEED GFX DRM",

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