Lines Matching full:gfx
927 release_firmware(adev->gfx.pfp_fw); in gfx_v8_0_free_microcode()
928 adev->gfx.pfp_fw = NULL; in gfx_v8_0_free_microcode()
929 release_firmware(adev->gfx.me_fw); in gfx_v8_0_free_microcode()
930 adev->gfx.me_fw = NULL; in gfx_v8_0_free_microcode()
931 release_firmware(adev->gfx.ce_fw); in gfx_v8_0_free_microcode()
932 adev->gfx.ce_fw = NULL; in gfx_v8_0_free_microcode()
933 release_firmware(adev->gfx.rlc_fw); in gfx_v8_0_free_microcode()
934 adev->gfx.rlc_fw = NULL; in gfx_v8_0_free_microcode()
935 release_firmware(adev->gfx.mec_fw); in gfx_v8_0_free_microcode()
936 adev->gfx.mec_fw = NULL; in gfx_v8_0_free_microcode()
939 release_firmware(adev->gfx.mec2_fw); in gfx_v8_0_free_microcode()
940 adev->gfx.mec2_fw = NULL; in gfx_v8_0_free_microcode()
942 kfree(adev->gfx.rlc.register_list_format); in gfx_v8_0_free_microcode()
992 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); in gfx_v8_0_init_microcode()
995 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); in gfx_v8_0_init_microcode()
999 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); in gfx_v8_0_init_microcode()
1003 err = amdgpu_ucode_validate(adev->gfx.pfp_fw); in gfx_v8_0_init_microcode()
1006 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; in gfx_v8_0_init_microcode()
1007 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); in gfx_v8_0_init_microcode()
1008 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); in gfx_v8_0_init_microcode()
1012 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); in gfx_v8_0_init_microcode()
1015 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); in gfx_v8_0_init_microcode()
1019 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); in gfx_v8_0_init_microcode()
1023 err = amdgpu_ucode_validate(adev->gfx.me_fw); in gfx_v8_0_init_microcode()
1026 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; in gfx_v8_0_init_microcode()
1027 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); in gfx_v8_0_init_microcode()
1029 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); in gfx_v8_0_init_microcode()
1033 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); in gfx_v8_0_init_microcode()
1036 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); in gfx_v8_0_init_microcode()
1040 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); in gfx_v8_0_init_microcode()
1044 err = amdgpu_ucode_validate(adev->gfx.ce_fw); in gfx_v8_0_init_microcode()
1047 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; in gfx_v8_0_init_microcode()
1048 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); in gfx_v8_0_init_microcode()
1049 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); in gfx_v8_0_init_microcode()
1055 if (adev->gfx.ce_feature_version >= 46 && in gfx_v8_0_init_microcode()
1056 adev->gfx.pfp_feature_version >= 46) { in gfx_v8_0_init_microcode()
1063 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); in gfx_v8_0_init_microcode()
1066 err = amdgpu_ucode_validate(adev->gfx.rlc_fw); in gfx_v8_0_init_microcode()
1067 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; in gfx_v8_0_init_microcode()
1068 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version); in gfx_v8_0_init_microcode()
1069 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version); in gfx_v8_0_init_microcode()
1071 adev->gfx.rlc.save_and_restore_offset = in gfx_v8_0_init_microcode()
1073 adev->gfx.rlc.clear_state_descriptor_offset = in gfx_v8_0_init_microcode()
1075 adev->gfx.rlc.avail_scratch_ram_locations = in gfx_v8_0_init_microcode()
1077 adev->gfx.rlc.reg_restore_list_size = in gfx_v8_0_init_microcode()
1079 adev->gfx.rlc.reg_list_format_start = in gfx_v8_0_init_microcode()
1081 adev->gfx.rlc.reg_list_format_separate_start = in gfx_v8_0_init_microcode()
1083 adev->gfx.rlc.starting_offsets_start = in gfx_v8_0_init_microcode()
1085 adev->gfx.rlc.reg_list_format_size_bytes = in gfx_v8_0_init_microcode()
1087 adev->gfx.rlc.reg_list_size_bytes = in gfx_v8_0_init_microcode()
1090 adev->gfx.rlc.register_list_format = in gfx_v8_0_init_microcode()
1091 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes + in gfx_v8_0_init_microcode()
1092 adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL); in gfx_v8_0_init_microcode()
1094 if (!adev->gfx.rlc.register_list_format) { in gfx_v8_0_init_microcode()
1101 for (i = 0 ; i < (adev->gfx.rlc.reg_list_format_size_bytes >> 2); i++) in gfx_v8_0_init_microcode()
1102 adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]); in gfx_v8_0_init_microcode()
1104 adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i; in gfx_v8_0_init_microcode()
1108 for (i = 0 ; i < (adev->gfx.rlc.reg_list_size_bytes >> 2); i++) in gfx_v8_0_init_microcode()
1109 adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]); in gfx_v8_0_init_microcode()
1113 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); in gfx_v8_0_init_microcode()
1116 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); in gfx_v8_0_init_microcode()
1120 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); in gfx_v8_0_init_microcode()
1124 err = amdgpu_ucode_validate(adev->gfx.mec_fw); in gfx_v8_0_init_microcode()
1127 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; in gfx_v8_0_init_microcode()
1128 adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); in gfx_v8_0_init_microcode()
1129 adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); in gfx_v8_0_init_microcode()
1135 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); in gfx_v8_0_init_microcode()
1138 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); in gfx_v8_0_init_microcode()
1142 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); in gfx_v8_0_init_microcode()
1145 err = amdgpu_ucode_validate(adev->gfx.mec2_fw); in gfx_v8_0_init_microcode()
1149 adev->gfx.mec2_fw->data; in gfx_v8_0_init_microcode()
1150 adev->gfx.mec2_fw_version = in gfx_v8_0_init_microcode()
1152 adev->gfx.mec2_feature_version = in gfx_v8_0_init_microcode()
1156 adev->gfx.mec2_fw = NULL; in gfx_v8_0_init_microcode()
1162 info->fw = adev->gfx.pfp_fw; in gfx_v8_0_init_microcode()
1169 info->fw = adev->gfx.me_fw; in gfx_v8_0_init_microcode()
1176 info->fw = adev->gfx.ce_fw; in gfx_v8_0_init_microcode()
1183 info->fw = adev->gfx.rlc_fw; in gfx_v8_0_init_microcode()
1190 info->fw = adev->gfx.mec_fw; in gfx_v8_0_init_microcode()
1196 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; in gfx_v8_0_init_microcode()
1203 info->fw = adev->gfx.mec_fw; in gfx_v8_0_init_microcode()
1208 if (adev->gfx.mec2_fw) { in gfx_v8_0_init_microcode()
1211 info->fw = adev->gfx.mec2_fw; in gfx_v8_0_init_microcode()
1222 release_firmware(adev->gfx.pfp_fw); in gfx_v8_0_init_microcode()
1223 adev->gfx.pfp_fw = NULL; in gfx_v8_0_init_microcode()
1224 release_firmware(adev->gfx.me_fw); in gfx_v8_0_init_microcode()
1225 adev->gfx.me_fw = NULL; in gfx_v8_0_init_microcode()
1226 release_firmware(adev->gfx.ce_fw); in gfx_v8_0_init_microcode()
1227 adev->gfx.ce_fw = NULL; in gfx_v8_0_init_microcode()
1228 release_firmware(adev->gfx.rlc_fw); in gfx_v8_0_init_microcode()
1229 adev->gfx.rlc_fw = NULL; in gfx_v8_0_init_microcode()
1230 release_firmware(adev->gfx.mec_fw); in gfx_v8_0_init_microcode()
1231 adev->gfx.mec_fw = NULL; in gfx_v8_0_init_microcode()
1232 release_firmware(adev->gfx.mec2_fw); in gfx_v8_0_init_microcode()
1233 adev->gfx.mec2_fw = NULL; in gfx_v8_0_init_microcode()
1245 if (adev->gfx.rlc.cs_data == NULL) in gfx_v8_0_get_csb_buffer()
1257 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { in gfx_v8_0_get_csb_buffer()
1275 buffer[count++] = cpu_to_le32(adev->gfx.config.rb_config[0][0].raster_config); in gfx_v8_0_get_csb_buffer()
1276 buffer[count++] = cpu_to_le32(adev->gfx.config.rb_config[0][0].raster_config_1); in gfx_v8_0_get_csb_buffer()
1298 adev->gfx.rlc.cs_data = vi_cs_data; in gfx_v8_0_rlc_init()
1300 cs_data = adev->gfx.rlc.cs_data; in gfx_v8_0_rlc_init()
1311 adev->gfx.rlc.cp_table_size = ALIGN(96 * 5 * 4, 2048) + (64 * 1024); /* JT + GDS */ in gfx_v8_0_rlc_init()
1318 if (adev->gfx.rlc.funcs->update_spm_vmid) in gfx_v8_0_rlc_init()
1319 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf); in gfx_v8_0_rlc_init()
1326 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); in gfx_v8_0_mec_fini()
1335 bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); in gfx_v8_0_mec_init()
1340 mec_hpd_size = adev->gfx.num_compute_rings * GFX8_MEC_HPD_SIZE; in gfx_v8_0_mec_init()
1344 &adev->gfx.mec.hpd_eop_obj, in gfx_v8_0_mec_init()
1345 &adev->gfx.mec.hpd_eop_gpu_addr, in gfx_v8_0_mec_init()
1354 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); in gfx_v8_0_mec_init()
1355 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); in gfx_v8_0_mec_init()
1517 struct amdgpu_ring *ring = &adev->gfx.compute_ring[0]; in gfx_v8_0_do_edc_gpr_workarounds()
1689 adev->gfx.config.max_shader_engines = 1; in gfx_v8_0_gpu_early_init()
1690 adev->gfx.config.max_tile_pipes = 2; in gfx_v8_0_gpu_early_init()
1691 adev->gfx.config.max_cu_per_sh = 6; in gfx_v8_0_gpu_early_init()
1692 adev->gfx.config.max_sh_per_se = 1; in gfx_v8_0_gpu_early_init()
1693 adev->gfx.config.max_backends_per_se = 2; in gfx_v8_0_gpu_early_init()
1694 adev->gfx.config.max_texture_channel_caches = 2; in gfx_v8_0_gpu_early_init()
1695 adev->gfx.config.max_gprs = 256; in gfx_v8_0_gpu_early_init()
1696 adev->gfx.config.max_gs_threads = 32; in gfx_v8_0_gpu_early_init()
1697 adev->gfx.config.max_hw_contexts = 8; in gfx_v8_0_gpu_early_init()
1699 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v8_0_gpu_early_init()
1700 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v8_0_gpu_early_init()
1701 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v8_0_gpu_early_init()
1702 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v8_0_gpu_early_init()
1706 adev->gfx.config.max_shader_engines = 4; in gfx_v8_0_gpu_early_init()
1707 adev->gfx.config.max_tile_pipes = 16; in gfx_v8_0_gpu_early_init()
1708 adev->gfx.config.max_cu_per_sh = 16; in gfx_v8_0_gpu_early_init()
1709 adev->gfx.config.max_sh_per_se = 1; in gfx_v8_0_gpu_early_init()
1710 adev->gfx.config.max_backends_per_se = 4; in gfx_v8_0_gpu_early_init()
1711 adev->gfx.config.max_texture_channel_caches = 16; in gfx_v8_0_gpu_early_init()
1712 adev->gfx.config.max_gprs = 256; in gfx_v8_0_gpu_early_init()
1713 adev->gfx.config.max_gs_threads = 32; in gfx_v8_0_gpu_early_init()
1714 adev->gfx.config.max_hw_contexts = 8; in gfx_v8_0_gpu_early_init()
1716 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v8_0_gpu_early_init()
1717 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v8_0_gpu_early_init()
1718 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v8_0_gpu_early_init()
1719 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v8_0_gpu_early_init()
1727 adev->gfx.config.max_gprs = 256; in gfx_v8_0_gpu_early_init()
1728 adev->gfx.config.max_gs_threads = 32; in gfx_v8_0_gpu_early_init()
1729 adev->gfx.config.max_hw_contexts = 8; in gfx_v8_0_gpu_early_init()
1731 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v8_0_gpu_early_init()
1732 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v8_0_gpu_early_init()
1733 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v8_0_gpu_early_init()
1734 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v8_0_gpu_early_init()
1742 adev->gfx.config.max_gprs = 256; in gfx_v8_0_gpu_early_init()
1743 adev->gfx.config.max_gs_threads = 32; in gfx_v8_0_gpu_early_init()
1744 adev->gfx.config.max_hw_contexts = 8; in gfx_v8_0_gpu_early_init()
1746 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v8_0_gpu_early_init()
1747 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v8_0_gpu_early_init()
1748 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v8_0_gpu_early_init()
1749 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v8_0_gpu_early_init()
1753 adev->gfx.config.max_shader_engines = 4; in gfx_v8_0_gpu_early_init()
1754 adev->gfx.config.max_tile_pipes = 8; in gfx_v8_0_gpu_early_init()
1755 adev->gfx.config.max_cu_per_sh = 8; in gfx_v8_0_gpu_early_init()
1756 adev->gfx.config.max_sh_per_se = 1; in gfx_v8_0_gpu_early_init()
1757 adev->gfx.config.max_backends_per_se = 2; in gfx_v8_0_gpu_early_init()
1758 adev->gfx.config.max_texture_channel_caches = 8; in gfx_v8_0_gpu_early_init()
1759 adev->gfx.config.max_gprs = 256; in gfx_v8_0_gpu_early_init()
1760 adev->gfx.config.max_gs_threads = 32; in gfx_v8_0_gpu_early_init()
1761 adev->gfx.config.max_hw_contexts = 8; in gfx_v8_0_gpu_early_init()
1763 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v8_0_gpu_early_init()
1764 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v8_0_gpu_early_init()
1765 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v8_0_gpu_early_init()
1766 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v8_0_gpu_early_init()
1770 adev->gfx.config.max_shader_engines = 1; in gfx_v8_0_gpu_early_init()
1771 adev->gfx.config.max_tile_pipes = 2; in gfx_v8_0_gpu_early_init()
1772 adev->gfx.config.max_sh_per_se = 1; in gfx_v8_0_gpu_early_init()
1773 adev->gfx.config.max_backends_per_se = 2; in gfx_v8_0_gpu_early_init()
1774 adev->gfx.config.max_cu_per_sh = 8; in gfx_v8_0_gpu_early_init()
1775 adev->gfx.config.max_texture_channel_caches = 2; in gfx_v8_0_gpu_early_init()
1776 adev->gfx.config.max_gprs = 256; in gfx_v8_0_gpu_early_init()
1777 adev->gfx.config.max_gs_threads = 32; in gfx_v8_0_gpu_early_init()
1778 adev->gfx.config.max_hw_contexts = 8; in gfx_v8_0_gpu_early_init()
1780 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v8_0_gpu_early_init()
1781 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v8_0_gpu_early_init()
1782 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v8_0_gpu_early_init()
1783 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v8_0_gpu_early_init()
1787 adev->gfx.config.max_shader_engines = 1; in gfx_v8_0_gpu_early_init()
1788 adev->gfx.config.max_tile_pipes = 2; in gfx_v8_0_gpu_early_init()
1789 adev->gfx.config.max_sh_per_se = 1; in gfx_v8_0_gpu_early_init()
1790 adev->gfx.config.max_backends_per_se = 1; in gfx_v8_0_gpu_early_init()
1791 adev->gfx.config.max_cu_per_sh = 3; in gfx_v8_0_gpu_early_init()
1792 adev->gfx.config.max_texture_channel_caches = 2; in gfx_v8_0_gpu_early_init()
1793 adev->gfx.config.max_gprs = 256; in gfx_v8_0_gpu_early_init()
1794 adev->gfx.config.max_gs_threads = 16; in gfx_v8_0_gpu_early_init()
1795 adev->gfx.config.max_hw_contexts = 8; in gfx_v8_0_gpu_early_init()
1797 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v8_0_gpu_early_init()
1798 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v8_0_gpu_early_init()
1799 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v8_0_gpu_early_init()
1800 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v8_0_gpu_early_init()
1804 adev->gfx.config.max_shader_engines = 2; in gfx_v8_0_gpu_early_init()
1805 adev->gfx.config.max_tile_pipes = 4; in gfx_v8_0_gpu_early_init()
1806 adev->gfx.config.max_cu_per_sh = 2; in gfx_v8_0_gpu_early_init()
1807 adev->gfx.config.max_sh_per_se = 1; in gfx_v8_0_gpu_early_init()
1808 adev->gfx.config.max_backends_per_se = 2; in gfx_v8_0_gpu_early_init()
1809 adev->gfx.config.max_texture_channel_caches = 4; in gfx_v8_0_gpu_early_init()
1810 adev->gfx.config.max_gprs = 256; in gfx_v8_0_gpu_early_init()
1811 adev->gfx.config.max_gs_threads = 32; in gfx_v8_0_gpu_early_init()
1812 adev->gfx.config.max_hw_contexts = 8; in gfx_v8_0_gpu_early_init()
1814 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v8_0_gpu_early_init()
1815 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v8_0_gpu_early_init()
1816 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v8_0_gpu_early_init()
1817 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v8_0_gpu_early_init()
1822 adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG); in gfx_v8_0_gpu_early_init()
1823 mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg; in gfx_v8_0_gpu_early_init()
1825 adev->gfx.config.num_banks = REG_GET_FIELD(mc_arb_ramcfg, in gfx_v8_0_gpu_early_init()
1827 adev->gfx.config.num_ranks = REG_GET_FIELD(mc_arb_ramcfg, in gfx_v8_0_gpu_early_init()
1830 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes; in gfx_v8_0_gpu_early_init()
1831 adev->gfx.config.mem_max_burst_length_bytes = 256; in gfx_v8_0_gpu_early_init()
1855 adev->gfx.config.mem_row_size_in_kb = 2; in gfx_v8_0_gpu_early_init()
1857 adev->gfx.config.mem_row_size_in_kb = 1; in gfx_v8_0_gpu_early_init()
1860 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024; in gfx_v8_0_gpu_early_init()
1861 if (adev->gfx.config.mem_row_size_in_kb > 4) in gfx_v8_0_gpu_early_init()
1862 adev->gfx.config.mem_row_size_in_kb = 4; in gfx_v8_0_gpu_early_init()
1865 adev->gfx.config.shader_engine_tile_size = 32; in gfx_v8_0_gpu_early_init()
1866 adev->gfx.config.num_gpus = 1; in gfx_v8_0_gpu_early_init()
1867 adev->gfx.config.multi_gpu_tile_size = 64; in gfx_v8_0_gpu_early_init()
1870 switch (adev->gfx.config.mem_row_size_in_kb) { in gfx_v8_0_gpu_early_init()
1882 adev->gfx.config.gb_addr_config = gb_addr_config; in gfx_v8_0_gpu_early_init()
1892 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id]; in gfx_v8_0_compute_ring_init()
1895 ring = &adev->gfx.compute_ring[ring_id]; in gfx_v8_0_compute_ring_init()
1905 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr in gfx_v8_0_compute_ring_init()
1910 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) in gfx_v8_0_compute_ring_init()
1916 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, in gfx_v8_0_compute_ring_init()
1942 adev->gfx.mec.num_mec = 2; in gfx_v8_0_sw_init()
1947 adev->gfx.mec.num_mec = 1; in gfx_v8_0_sw_init()
1951 adev->gfx.mec.num_pipe_per_mec = 4; in gfx_v8_0_sw_init()
1952 adev->gfx.mec.num_queue_per_pipe = 8; in gfx_v8_0_sw_init()
1955 …q_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_CP_END_OF_PIPE, &adev->gfx.eop_irq); in gfx_v8_0_sw_init()
1961 &adev->gfx.priv_reg_irq); in gfx_v8_0_sw_init()
1967 &adev->gfx.priv_inst_irq); in gfx_v8_0_sw_init()
1973 &adev->gfx.cp_ecc_error_irq); in gfx_v8_0_sw_init()
1979 &adev->gfx.sq_irq); in gfx_v8_0_sw_init()
1985 INIT_WORK(&adev->gfx.sq_work.work, gfx_v8_0_sq_irq_work_func); in gfx_v8_0_sw_init()
1987 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; in gfx_v8_0_sw_init()
1991 DRM_ERROR("Failed to load gfx firmware!\n"); in gfx_v8_0_sw_init()
1995 r = adev->gfx.rlc.funcs->init(adev); in gfx_v8_0_sw_init()
2007 /* set up the gfx ring */ in gfx_v8_0_sw_init()
2008 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { in gfx_v8_0_sw_init()
2009 ring = &adev->gfx.gfx_ring[i]; in gfx_v8_0_sw_init()
2011 sprintf(ring->name, "gfx"); in gfx_v8_0_sw_init()
2012 /* no gfx doorbells on iceland */ in gfx_v8_0_sw_init()
2018 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, in gfx_v8_0_sw_init()
2028 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { in gfx_v8_0_sw_init()
2029 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { in gfx_v8_0_sw_init()
2030 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { in gfx_v8_0_sw_init()
2051 kiq = &adev->gfx.kiq; in gfx_v8_0_sw_init()
2061 adev->gfx.ce_ram_size = 0x8000; in gfx_v8_0_sw_init()
2075 for (i = 0; i < adev->gfx.num_gfx_rings; i++) in gfx_v8_0_sw_fini()
2076 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); in gfx_v8_0_sw_fini()
2077 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v8_0_sw_fini()
2078 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); in gfx_v8_0_sw_fini()
2081 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring); in gfx_v8_0_sw_fini()
2086 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, in gfx_v8_0_sw_fini()
2087 &adev->gfx.rlc.clear_state_gpu_addr, in gfx_v8_0_sw_fini()
2088 (void **)&adev->gfx.rlc.cs_ptr); in gfx_v8_0_sw_fini()
2091 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, in gfx_v8_0_sw_fini()
2092 &adev->gfx.rlc.cp_table_gpu_addr, in gfx_v8_0_sw_fini()
2093 (void **)&adev->gfx.rlc.cp_table_ptr); in gfx_v8_0_sw_fini()
2103 const u32 num_tile_mode_states = ARRAY_SIZE(adev->gfx.config.tile_mode_array); in gfx_v8_0_tiling_mode_table_init()
2104 const u32 num_secondary_tile_mode_states = ARRAY_SIZE(adev->gfx.config.macrotile_mode_array); in gfx_v8_0_tiling_mode_table_init()
2107 modearray = adev->gfx.config.tile_mode_array; in gfx_v8_0_tiling_mode_table_init()
2108 mod2array = adev->gfx.config.macrotile_mode_array; in gfx_v8_0_tiling_mode_table_init()
3461 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / in gfx_v8_0_get_rb_active_bitmap()
3462 adev->gfx.config.max_sh_per_se); in gfx_v8_0_get_rb_active_bitmap()
3513 unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1); in gfx_v8_0_write_harvested_raster_configs()
3514 unsigned num_se = max_t(unsigned, adev->gfx.config.max_shader_engines, 1); in gfx_v8_0_write_harvested_raster_configs()
3623 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / in gfx_v8_0_setup_rb()
3624 adev->gfx.config.max_sh_per_se; in gfx_v8_0_setup_rb()
3628 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v8_0_setup_rb()
3629 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v8_0_setup_rb()
3632 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * in gfx_v8_0_setup_rb()
3638 adev->gfx.config.backend_enable_mask = active_rbs; in gfx_v8_0_setup_rb()
3639 adev->gfx.config.num_rbs = hweight32(active_rbs); in gfx_v8_0_setup_rb()
3641 num_rb_pipes = min_t(unsigned, adev->gfx.config.max_backends_per_se * in gfx_v8_0_setup_rb()
3642 adev->gfx.config.max_shader_engines, 16); in gfx_v8_0_setup_rb()
3646 if (!adev->gfx.config.backend_enable_mask || in gfx_v8_0_setup_rb()
3647 adev->gfx.config.num_rbs >= num_rb_pipes) { in gfx_v8_0_setup_rb()
3652 adev->gfx.config.backend_enable_mask, in gfx_v8_0_setup_rb()
3657 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v8_0_setup_rb()
3658 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v8_0_setup_rb()
3660 adev->gfx.config.rb_config[i][j].rb_backend_disable = in gfx_v8_0_setup_rb()
3662 adev->gfx.config.rb_config[i][j].user_rb_backend_disable = in gfx_v8_0_setup_rb()
3664 adev->gfx.config.rb_config[i][j].raster_config = in gfx_v8_0_setup_rb()
3666 adev->gfx.config.rb_config[i][j].raster_config_1 = in gfx_v8_0_setup_rb()
3731 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA in gfx_v8_0_init_gds_vmid()
3748 adev->gfx.config.double_offchip_lds_buf = 1; in gfx_v8_0_config_init()
3752 adev->gfx.config.double_offchip_lds_buf = 0; in gfx_v8_0_config_init()
3763 WREG32(mmGB_ADDR_CONFIG, adev->gfx.config.gb_addr_config); in gfx_v8_0_constants_init()
3764 WREG32(mmHDP_ADDR_CONFIG, adev->gfx.config.gb_addr_config); in gfx_v8_0_constants_init()
3765 WREG32(mmDMIF_ADDR_CALC, adev->gfx.config.gb_addr_config); in gfx_v8_0_constants_init()
3820 (adev->gfx.config.sc_prim_fifo_size_frontend << in gfx_v8_0_constants_init()
3822 (adev->gfx.config.sc_prim_fifo_size_backend << in gfx_v8_0_constants_init()
3824 (adev->gfx.config.sc_hiz_tile_fifo_size << in gfx_v8_0_constants_init()
3826 (adev->gfx.config.sc_earlyz_tile_fifo_size << in gfx_v8_0_constants_init()
3846 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v8_0_wait_for_rlc_serdes()
3847 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v8_0_wait_for_rlc_serdes()
3893 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); in gfx_v8_0_init_csb()
3896 adev->gfx.rlc.clear_state_gpu_addr >> 32); in gfx_v8_0_init_csb()
3898 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); in gfx_v8_0_init_csb()
3900 adev->gfx.rlc.clear_state_size); in gfx_v8_0_init_csb()
3963 kmemdup(adev->gfx.rlc.register_list_format, in gfx_v8_0_init_save_restore_list()
3964 adev->gfx.rlc.reg_list_format_size_bytes, GFP_KERNEL); in gfx_v8_0_init_save_restore_list()
3970 adev->gfx.rlc.reg_list_format_size_bytes >> 2, in gfx_v8_0_init_save_restore_list()
3982 for (i = 0; i < adev->gfx.rlc.reg_list_size_bytes >> 2; i++) in gfx_v8_0_init_save_restore_list()
3983 WREG32(mmRLC_SRM_ARAM_DATA, adev->gfx.rlc.register_restore[i]); in gfx_v8_0_init_save_restore_list()
3986 WREG32(mmRLC_GPM_SCRATCH_ADDR, adev->gfx.rlc.reg_list_format_start); in gfx_v8_0_init_save_restore_list()
3987 for (i = 0; i < adev->gfx.rlc.reg_list_format_size_bytes >> 2; i++) in gfx_v8_0_init_save_restore_list()
3990 list_size = adev->gfx.rlc.reg_list_size_bytes >> 2; in gfx_v8_0_init_save_restore_list()
3992 WREG32(mmRLC_GPM_SCRATCH_ADDR, adev->gfx.rlc.reg_restore_list_size); in gfx_v8_0_init_save_restore_list()
3997 adev->gfx.rlc.starting_offsets_start); in gfx_v8_0_init_save_restore_list()
4062 WREG32(mmRLC_JUMP_TABLE_RESTORE, adev->gfx.rlc.cp_table_gpu_addr >> 8); in gfx_v8_0_init_pg()
4064 WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask); in gfx_v8_0_init_pg()
4111 adev->gfx.rlc.funcs->stop(adev); in gfx_v8_0_rlc_resume()
4112 adev->gfx.rlc.funcs->reset(adev); in gfx_v8_0_rlc_resume()
4114 adev->gfx.rlc.funcs->start(adev); in gfx_v8_0_rlc_resume()
4167 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0]; in gfx_v8_0_cp_gfx_start()
4173 WREG32(mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1); in gfx_v8_0_cp_gfx_start()
4209 amdgpu_ring_write(ring, adev->gfx.config.rb_config[0][0].raster_config); in gfx_v8_0_cp_gfx_start()
4210 amdgpu_ring_write(ring, adev->gfx.config.rb_config[0][0].raster_config_1); in gfx_v8_0_cp_gfx_start()
4231 /* no gfx doorbells on iceland */ in gfx_v8_0_set_cpg_door_bell()
4276 ring = &adev->gfx.gfx_ring[0]; in gfx_v8_0_cp_gfx_resume()
4322 adev->gfx.kiq.ring.sched.ready = false; in gfx_v8_0_cp_compute_enable()
4344 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; in gfx_v8_0_kiq_kcq_enable()
4349 if (!test_bit(i, adev->gfx.mec.queue_bitmap)) in gfx_v8_0_kiq_kcq_enable()
4363 r = amdgpu_ring_alloc(kiq_ring, (8 * adev->gfx.num_compute_rings) + 8); in gfx_v8_0_kiq_kcq_enable()
4377 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v8_0_kiq_kcq_enable()
4378 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i]; in gfx_v8_0_kiq_kcq_enable()
4631 if (adev->gfx.mec.mqd_backup[mqd_idx]) in gfx_v8_0_kiq_init_queue()
4632 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct vi_mqd_allocation)); in gfx_v8_0_kiq_init_queue()
4653 if (adev->gfx.mec.mqd_backup[mqd_idx]) in gfx_v8_0_kiq_init_queue()
4654 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct vi_mqd_allocation)); in gfx_v8_0_kiq_init_queue()
4664 int mqd_idx = ring - &adev->gfx.compute_ring[0]; in gfx_v8_0_kcq_init_queue()
4676 if (adev->gfx.mec.mqd_backup[mqd_idx]) in gfx_v8_0_kcq_init_queue()
4677 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct vi_mqd_allocation)); in gfx_v8_0_kcq_init_queue()
4680 if (adev->gfx.mec.mqd_backup[mqd_idx]) in gfx_v8_0_kcq_init_queue()
4681 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct vi_mqd_allocation)); in gfx_v8_0_kcq_init_queue()
4706 ring = &adev->gfx.kiq.ring; in gfx_v8_0_kiq_resume()
4731 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v8_0_kcq_resume()
4732 ring = &adev->gfx.compute_ring[i]; in gfx_v8_0_kcq_resume()
4763 /* collect all the ring_tests here, gfx, kiq, compute */ in gfx_v8_0_cp_test_all_rings()
4764 ring = &adev->gfx.gfx_ring[0]; in gfx_v8_0_cp_test_all_rings()
4769 ring = &adev->gfx.kiq.ring; in gfx_v8_0_cp_test_all_rings()
4774 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v8_0_cp_test_all_rings()
4775 ring = &adev->gfx.compute_ring[i]; in gfx_v8_0_cp_test_all_rings()
4824 r = adev->gfx.rlc.funcs->resume(adev); in gfx_v8_0_hw_init()
4836 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; in gfx_v8_0_kcq_disable()
4838 r = amdgpu_ring_alloc(kiq_ring, 6 * adev->gfx.num_compute_rings); in gfx_v8_0_kcq_disable()
4842 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v8_0_kcq_disable()
4843 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i]; in gfx_v8_0_kcq_disable()
4916 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); in gfx_v8_0_hw_fini()
4917 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); in gfx_v8_0_hw_fini()
4919 amdgpu_irq_put(adev, &adev->gfx.cp_ecc_error_irq, 0); in gfx_v8_0_hw_fini()
4921 amdgpu_irq_put(adev, &adev->gfx.sq_irq, 0); in gfx_v8_0_hw_fini()
4936 adev->gfx.rlc.funcs->stop(adev); in gfx_v8_0_hw_fini()
5006 adev->gfx.grbm_soft_reset = grbm_soft_reset; in gfx_v8_0_check_soft_reset()
5007 adev->gfx.srbm_soft_reset = srbm_soft_reset; in gfx_v8_0_check_soft_reset()
5010 adev->gfx.grbm_soft_reset = 0; in gfx_v8_0_check_soft_reset()
5011 adev->gfx.srbm_soft_reset = 0; in gfx_v8_0_check_soft_reset()
5021 if ((!adev->gfx.grbm_soft_reset) && in gfx_v8_0_pre_soft_reset()
5022 (!adev->gfx.srbm_soft_reset)) in gfx_v8_0_pre_soft_reset()
5025 grbm_soft_reset = adev->gfx.grbm_soft_reset; in gfx_v8_0_pre_soft_reset()
5028 adev->gfx.rlc.funcs->stop(adev); in gfx_v8_0_pre_soft_reset()
5032 /* Disable GFX parsing/prefetching */ in gfx_v8_0_pre_soft_reset()
5041 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v8_0_pre_soft_reset()
5042 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i]; in gfx_v8_0_pre_soft_reset()
5063 if ((!adev->gfx.grbm_soft_reset) && in gfx_v8_0_soft_reset()
5064 (!adev->gfx.srbm_soft_reset)) in gfx_v8_0_soft_reset()
5067 grbm_soft_reset = adev->gfx.grbm_soft_reset; in gfx_v8_0_soft_reset()
5068 srbm_soft_reset = adev->gfx.srbm_soft_reset; in gfx_v8_0_soft_reset()
5124 if ((!adev->gfx.grbm_soft_reset) && in gfx_v8_0_post_soft_reset()
5125 (!adev->gfx.srbm_soft_reset)) in gfx_v8_0_post_soft_reset()
5128 grbm_soft_reset = adev->gfx.grbm_soft_reset; in gfx_v8_0_post_soft_reset()
5136 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v8_0_post_soft_reset()
5137 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i]; in gfx_v8_0_post_soft_reset()
5155 adev->gfx.rlc.funcs->start(adev); in gfx_v8_0_post_soft_reset()
5172 mutex_lock(&adev->gfx.gpu_clock_mutex); in gfx_v8_0_get_gpu_clock_counter()
5176 mutex_unlock(&adev->gfx.gpu_clock_mutex); in gfx_v8_0_get_gpu_clock_counter()
5291 adev->gfx.num_gfx_rings = GFX8_NUM_GFX_RINGS; in gfx_v8_0_early_init()
5292 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), in gfx_v8_0_early_init()
5294 adev->gfx.funcs = &gfx_v8_0_gfx_funcs; in gfx_v8_0_early_init()
5308 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); in gfx_v8_0_late_init()
5312 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); in gfx_v8_0_late_init()
5321 r = amdgpu_irq_get(adev, &adev->gfx.cp_ecc_error_irq, 0); in gfx_v8_0_late_init()
5327 r = amdgpu_irq_get(adev, &adev->gfx.sq_irq, 0); in gfx_v8_0_late_init()
5373 /* Read any GFX register to wake up GFX. */ in cz_enable_gfx_pipeline_power_gating()
5799 /* disable cntx_empty_int_enable & GFX Idle interrupt */ in gfx_v8_0_update_coarse_grain_clock_gating()
5809 /* read gfx register to wake up cgcg */ in gfx_v8_0_update_coarse_grain_clock_gating()
6336 /* set load_per_context_state & load_gfx_sh_regs for GFX */ in gfx_v8_ring_emit_cntxcntl()
6640 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); in gfx_v8_0_eop_irq()
6644 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v8_0_eop_irq()
6645 ring = &adev->gfx.compute_ring[i]; in gfx_v8_0_eop_irq()
6670 drm_sched_fault(&adev->gfx.gfx_ring[0].sched); in gfx_v8_0_fault()
6674 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v8_0_fault()
6675 ring = &adev->gfx.compute_ring[i]; in gfx_v8_0_fault()
6784 struct amdgpu_device *adev = container_of(work, struct amdgpu_device, gfx.sq_work.work); in gfx_v8_0_sq_irq_work_func()
6801 if (work_pending(&adev->gfx.sq_work.work)) { in gfx_v8_0_sq_irq()
6804 adev->gfx.sq_work.ih_data = ih_data; in gfx_v8_0_sq_irq()
6805 schedule_work(&adev->gfx.sq_work.work); in gfx_v8_0_sq_irq()
6880 * number of gfx waves. Setting 5 bit will make sure gfx only gets in gfx_v8_0_emit_wave_limit()
6891 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { in gfx_v8_0_emit_wave_limit()
7029 adev->gfx.kiq.ring.funcs = &gfx_v8_0_ring_funcs_kiq; in gfx_v8_0_set_ring_funcs()
7031 for (i = 0; i < adev->gfx.num_gfx_rings; i++) in gfx_v8_0_set_ring_funcs()
7032 adev->gfx.gfx_ring[i].funcs = &gfx_v8_0_ring_funcs_gfx; in gfx_v8_0_set_ring_funcs()
7034 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v8_0_set_ring_funcs()
7035 adev->gfx.compute_ring[i].funcs = &gfx_v8_0_ring_funcs_compute; in gfx_v8_0_set_ring_funcs()
7065 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; in gfx_v8_0_set_irq_funcs()
7066 adev->gfx.eop_irq.funcs = &gfx_v8_0_eop_irq_funcs; in gfx_v8_0_set_irq_funcs()
7068 adev->gfx.priv_reg_irq.num_types = 1; in gfx_v8_0_set_irq_funcs()
7069 adev->gfx.priv_reg_irq.funcs = &gfx_v8_0_priv_reg_irq_funcs; in gfx_v8_0_set_irq_funcs()
7071 adev->gfx.priv_inst_irq.num_types = 1; in gfx_v8_0_set_irq_funcs()
7072 adev->gfx.priv_inst_irq.funcs = &gfx_v8_0_priv_inst_irq_funcs; in gfx_v8_0_set_irq_funcs()
7074 adev->gfx.cp_ecc_error_irq.num_types = 1; in gfx_v8_0_set_irq_funcs()
7075 adev->gfx.cp_ecc_error_irq.funcs = &gfx_v8_0_cp_ecc_error_irq_funcs; in gfx_v8_0_set_irq_funcs()
7077 adev->gfx.sq_irq.num_types = 1; in gfx_v8_0_set_irq_funcs()
7078 adev->gfx.sq_irq.funcs = &gfx_v8_0_sq_irq_funcs; in gfx_v8_0_set_irq_funcs()
7083 adev->gfx.rlc.funcs = &iceland_rlc_funcs; in gfx_v8_0_set_rlc_funcs()
7116 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh); in gfx_v8_0_get_cu_active_bitmap()
7125 struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info; in gfx_v8_0_get_cu_info()
7134 ao_cu_num = adev->gfx.config.max_cu_per_sh; in gfx_v8_0_get_cu_info()
7139 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v8_0_get_cu_info()
7140 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v8_0_get_cu_info()
7151 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) { in gfx_v8_0_get_cu_info()