Lines Matching full:gfx
42 #include "ivsrcid/gfx/irqsrcs_gfx_11_0_0.h"
190 if (adev->enable_mes && !adev->gfx.kiq.ring.sched.ready) { in gfx11_kiq_unmap_queues()
258 adev->gfx.kiq.pmf = &gfx_v11_0_kiq_pm4_funcs; in gfx_v11_0_set_kiq_pm4_funcs()
429 release_firmware(adev->gfx.pfp_fw); in gfx_v11_0_free_microcode()
430 adev->gfx.pfp_fw = NULL; in gfx_v11_0_free_microcode()
431 release_firmware(adev->gfx.me_fw); in gfx_v11_0_free_microcode()
432 adev->gfx.me_fw = NULL; in gfx_v11_0_free_microcode()
433 release_firmware(adev->gfx.rlc_fw); in gfx_v11_0_free_microcode()
434 adev->gfx.rlc_fw = NULL; in gfx_v11_0_free_microcode()
435 release_firmware(adev->gfx.mec_fw); in gfx_v11_0_free_microcode()
436 adev->gfx.mec_fw = NULL; in gfx_v11_0_free_microcode()
438 kfree(adev->gfx.rlc.register_list_format); in gfx_v11_0_free_microcode()
455 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); in gfx_v11_0_init_microcode()
458 err = amdgpu_ucode_validate(adev->gfx.pfp_fw); in gfx_v11_0_init_microcode()
462 adev->gfx.rs64_enable = amdgpu_ucode_hdr_version( in gfx_v11_0_init_microcode()
464 adev->gfx.pfp_fw->data, 2, 0); in gfx_v11_0_init_microcode()
465 if (adev->gfx.rs64_enable) { in gfx_v11_0_init_microcode()
475 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); in gfx_v11_0_init_microcode()
478 err = amdgpu_ucode_validate(adev->gfx.me_fw); in gfx_v11_0_init_microcode()
481 if (adev->gfx.rs64_enable) { in gfx_v11_0_init_microcode()
491 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); in gfx_v11_0_init_microcode()
494 err = amdgpu_ucode_validate(adev->gfx.rlc_fw); in gfx_v11_0_init_microcode()
497 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; in gfx_v11_0_init_microcode()
506 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); in gfx_v11_0_init_microcode()
509 err = amdgpu_ucode_validate(adev->gfx.mec_fw); in gfx_v11_0_init_microcode()
512 if (adev->gfx.rs64_enable) { in gfx_v11_0_init_microcode()
523 /* only one MEC for gfx 11.0.0. */ in gfx_v11_0_init_microcode()
524 adev->gfx.mec2_fw = NULL; in gfx_v11_0_init_microcode()
531 release_firmware(adev->gfx.pfp_fw); in gfx_v11_0_init_microcode()
532 adev->gfx.pfp_fw = NULL; in gfx_v11_0_init_microcode()
533 release_firmware(adev->gfx.me_fw); in gfx_v11_0_init_microcode()
534 adev->gfx.me_fw = NULL; in gfx_v11_0_init_microcode()
535 release_firmware(adev->gfx.rlc_fw); in gfx_v11_0_init_microcode()
536 adev->gfx.rlc_fw = NULL; in gfx_v11_0_init_microcode()
537 release_firmware(adev->gfx.mec_fw); in gfx_v11_0_init_microcode()
538 adev->gfx.mec_fw = NULL; in gfx_v11_0_init_microcode()
614 if (adev->gfx.rlc.cs_data == NULL) in gfx_v11_0_get_csb_buffer()
626 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { in gfx_v11_0_get_csb_buffer()
645 buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override); in gfx_v11_0_get_csb_buffer()
657 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, in gfx_v11_0_rlc_fini()
658 &adev->gfx.rlc.clear_state_gpu_addr, in gfx_v11_0_rlc_fini()
659 (void **)&adev->gfx.rlc.cs_ptr); in gfx_v11_0_rlc_fini()
662 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, in gfx_v11_0_rlc_fini()
663 &adev->gfx.rlc.cp_table_gpu_addr, in gfx_v11_0_rlc_fini()
664 (void **)&adev->gfx.rlc.cp_table_ptr); in gfx_v11_0_rlc_fini()
671 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl; in gfx_v11_0_init_rlcg_reg_access_ctrl()
679 adev->gfx.rlc.rlcg_reg_access_supported = true; in gfx_v11_0_init_rlcg_reg_access_ctrl()
687 adev->gfx.rlc.cs_data = gfx11_cs_data; in gfx_v11_0_rlc_init()
689 cs_data = adev->gfx.rlc.cs_data; in gfx_v11_0_rlc_init()
699 if (adev->gfx.rlc.funcs->update_spm_vmid) in gfx_v11_0_rlc_init()
700 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf); in gfx_v11_0_rlc_init()
707 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); in gfx_v11_0_mec_fini()
708 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); in gfx_v11_0_mec_fini()
709 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_data_obj, NULL, NULL); in gfx_v11_0_mec_fini()
716 bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES); in gfx_v11_0_me_init()
722 DRM_ERROR("Failed to load gfx firmware!\n"); in gfx_v11_0_me_init()
733 bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); in gfx_v11_0_mec_init()
737 mec_hpd_size = adev->gfx.num_compute_rings * GFX11_MEC_HPD_SIZE; in gfx_v11_0_mec_init()
742 &adev->gfx.mec.hpd_eop_obj, in gfx_v11_0_mec_init()
743 &adev->gfx.mec.hpd_eop_gpu_addr, in gfx_v11_0_mec_init()
753 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); in gfx_v11_0_mec_init()
754 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); in gfx_v11_0_mec_init()
846 adev->gfx.funcs = &gfx_v11_0_gfx_funcs; in gfx_v11_0_gpu_early_init()
852 adev->gfx.config.max_hw_contexts = 8; in gfx_v11_0_gpu_early_init()
853 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v11_0_gpu_early_init()
854 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v11_0_gpu_early_init()
855 adev->gfx.config.sc_hiz_tile_fifo_size = 0; in gfx_v11_0_gpu_early_init()
856 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; in gfx_v11_0_gpu_early_init()
859 adev->gfx.config.max_hw_contexts = 8; in gfx_v11_0_gpu_early_init()
860 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v11_0_gpu_early_init()
861 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v11_0_gpu_early_init()
862 adev->gfx.config.sc_hiz_tile_fifo_size = 0x80; in gfx_v11_0_gpu_early_init()
863 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x300; in gfx_v11_0_gpu_early_init()
880 ring = &adev->gfx.gfx_ring[ring_id]; in gfx_v11_0_gfx_ring_init()
896 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, in gfx_v11_0_gfx_ring_init()
911 ring = &adev->gfx.compute_ring[ring_id]; in gfx_v11_0_compute_ring_init()
921 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr in gfx_v11_0_compute_ring_init()
926 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) in gfx_v11_0_compute_ring_init()
931 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, in gfx_v11_0_compute_ring_init()
986 &adev->gfx.rlc.rlc_autoload_bo, in gfx_v11_0_rlc_autoload_buffer_init()
987 &adev->gfx.rlc.rlc_autoload_gpu_addr, in gfx_v11_0_rlc_autoload_buffer_init()
988 (void **)&adev->gfx.rlc.rlc_autoload_ptr); in gfx_v11_0_rlc_autoload_buffer_init()
1006 char *ptr = adev->gfx.rlc.rlc_autoload_ptr; in gfx_v11_0_rlc_backdoor_autoload_copy_ucode()
1061 if (adev->gfx.rs64_enable) { in gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode()
1064 adev->gfx.pfp_fw->data; in gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode()
1066 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + in gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode()
1072 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + in gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode()
1081 adev->gfx.me_fw->data; in gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode()
1083 fw_data = (const __le32 *)(adev->gfx.me_fw->data + in gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode()
1089 fw_data = (const __le32 *)(adev->gfx.me_fw->data + in gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode()
1098 adev->gfx.mec_fw->data; in gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode()
1100 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + in gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode()
1106 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + in gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode()
1120 adev->gfx.pfp_fw->data; in gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode()
1121 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + in gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode()
1129 adev->gfx.me_fw->data; in gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode()
1130 fw_data = (const __le32 *)(adev->gfx.me_fw->data + in gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode()
1138 adev->gfx.mec_fw->data; in gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode()
1139 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + in gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode()
1149 adev->gfx.rlc_fw->data; in gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode()
1150 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + in gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode()
1160 rlcv22_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; in gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode()
1162 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + in gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode()
1168 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + in gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode()
1253 gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset; in gfx_v11_0_rlc_backdoor_autoload_enable()
1261 if (adev->gfx.imu.funcs->load_microcode) in gfx_v11_0_rlc_backdoor_autoload_enable()
1262 adev->gfx.imu.funcs->load_microcode(adev); in gfx_v11_0_rlc_backdoor_autoload_enable()
1264 if (adev->gfx.imu.funcs->setup_imu) in gfx_v11_0_rlc_backdoor_autoload_enable()
1265 adev->gfx.imu.funcs->setup_imu(adev); in gfx_v11_0_rlc_backdoor_autoload_enable()
1266 if (adev->gfx.imu.funcs->start_imu) in gfx_v11_0_rlc_backdoor_autoload_enable()
1267 adev->gfx.imu.funcs->start_imu(adev); in gfx_v11_0_rlc_backdoor_autoload_enable()
1288 adev->gfx.me.num_me = 1; in gfx_v11_0_sw_init()
1289 adev->gfx.me.num_pipe_per_me = 1; in gfx_v11_0_sw_init()
1290 adev->gfx.me.num_queue_per_pipe = 1; in gfx_v11_0_sw_init()
1291 adev->gfx.mec.num_mec = 2; in gfx_v11_0_sw_init()
1292 adev->gfx.mec.num_pipe_per_mec = 4; in gfx_v11_0_sw_init()
1293 adev->gfx.mec.num_queue_per_pipe = 4; in gfx_v11_0_sw_init()
1296 adev->gfx.me.num_me = 1; in gfx_v11_0_sw_init()
1297 adev->gfx.me.num_pipe_per_me = 1; in gfx_v11_0_sw_init()
1298 adev->gfx.me.num_queue_per_pipe = 1; in gfx_v11_0_sw_init()
1299 adev->gfx.mec.num_mec = 1; in gfx_v11_0_sw_init()
1300 adev->gfx.mec.num_pipe_per_mec = 4; in gfx_v11_0_sw_init()
1301 adev->gfx.mec.num_queue_per_pipe = 8; in gfx_v11_0_sw_init()
1308 &adev->gfx.eop_irq); in gfx_v11_0_sw_init()
1315 &adev->gfx.priv_reg_irq); in gfx_v11_0_sw_init()
1322 &adev->gfx.priv_inst_irq); in gfx_v11_0_sw_init()
1326 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; in gfx_v11_0_sw_init()
1328 if (adev->gfx.imu.funcs) { in gfx_v11_0_sw_init()
1329 if (adev->gfx.imu.funcs->init_microcode) { in gfx_v11_0_sw_init()
1330 r = adev->gfx.imu.funcs->init_microcode(adev); in gfx_v11_0_sw_init()
1352 /* set up the gfx ring */ in gfx_v11_0_sw_init()
1353 for (i = 0; i < adev->gfx.me.num_me; i++) { in gfx_v11_0_sw_init()
1354 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) { in gfx_v11_0_sw_init()
1355 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { in gfx_v11_0_sw_init()
1370 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { in gfx_v11_0_sw_init()
1371 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { in gfx_v11_0_sw_init()
1372 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { in gfx_v11_0_sw_init()
1394 kiq = &adev->gfx.kiq; in gfx_v11_0_sw_init()
1423 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj, in gfx_v11_0_pfp_fini()
1424 &adev->gfx.pfp.pfp_fw_gpu_addr, in gfx_v11_0_pfp_fini()
1425 (void **)&adev->gfx.pfp.pfp_fw_ptr); in gfx_v11_0_pfp_fini()
1427 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_data_obj, in gfx_v11_0_pfp_fini()
1428 &adev->gfx.pfp.pfp_fw_data_gpu_addr, in gfx_v11_0_pfp_fini()
1429 (void **)&adev->gfx.pfp.pfp_fw_data_ptr); in gfx_v11_0_pfp_fini()
1434 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj, in gfx_v11_0_me_fini()
1435 &adev->gfx.me.me_fw_gpu_addr, in gfx_v11_0_me_fini()
1436 (void **)&adev->gfx.me.me_fw_ptr); in gfx_v11_0_me_fini()
1438 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_data_obj, in gfx_v11_0_me_fini()
1439 &adev->gfx.me.me_fw_data_gpu_addr, in gfx_v11_0_me_fini()
1440 (void **)&adev->gfx.me.me_fw_data_ptr); in gfx_v11_0_me_fini()
1445 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo, in gfx_v11_0_rlc_autoload_buffer_fini()
1446 &adev->gfx.rlc.rlc_autoload_gpu_addr, in gfx_v11_0_rlc_autoload_buffer_fini()
1447 (void **)&adev->gfx.rlc.rlc_autoload_ptr); in gfx_v11_0_rlc_autoload_buffer_fini()
1455 for (i = 0; i < adev->gfx.num_gfx_rings; i++) in gfx_v11_0_sw_fini()
1456 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); in gfx_v11_0_sw_fini()
1457 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v11_0_sw_fini()
1458 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); in gfx_v11_0_sw_fini()
1463 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring); in gfx_v11_0_sw_fini()
1517 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / in gfx_v11_0_get_rb_active_bitmap()
1518 adev->gfx.config.max_sh_per_se); in gfx_v11_0_get_rb_active_bitmap()
1528 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / in gfx_v11_0_setup_rb()
1529 adev->gfx.config.max_sh_per_se; in gfx_v11_0_setup_rb()
1532 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v11_0_setup_rb()
1533 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v11_0_setup_rb()
1536 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * in gfx_v11_0_setup_rb()
1543 adev->gfx.config.backend_enable_mask = active_rbs; in gfx_v11_0_setup_rb()
1544 adev->gfx.config.num_rbs = hweight32(active_rbs); in gfx_v11_0_setup_rb()
1595 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA in gfx_v11_0_init_gds_vmid()
1619 adev->gfx.config.tcc_disabled_mask = in gfx_v11_0_get_tcc_info()
1632 gfx_v11_0_get_cu_info(adev, &adev->gfx.cu_info); in gfx_v11_0_constants_init()
1634 adev->gfx.config.pa_sc_tile_steering_override = 0; in gfx_v11_0_constants_init()
1683 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); in gfx_v11_0_init_csb()
1686 adev->gfx.rlc.clear_state_gpu_addr >> 32); in gfx_v11_0_init_csb()
1688 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); in gfx_v11_0_init_csb()
1689 WREG32_SOC15(GC, 0, regRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); in gfx_v11_0_init_csb()
1760 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; in gfx_v11_0_load_rlcg_microcode()
1761 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + in gfx_v11_0_load_rlcg_microcode()
1772 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); in gfx_v11_0_load_rlcg_microcode()
1782 hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; in gfx_v11_0_load_rlc_iram_dram_microcode()
1784 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + in gfx_v11_0_load_rlc_iram_dram_microcode()
1797 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version); in gfx_v11_0_load_rlc_iram_dram_microcode()
1799 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + in gfx_v11_0_load_rlc_iram_dram_microcode()
1811 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version); in gfx_v11_0_load_rlc_iram_dram_microcode()
1826 hdr = (const struct rlc_firmware_header_v2_3 *)adev->gfx.rlc_fw->data; in gfx_v11_0_load_rlcp_rlcv_microcode()
1828 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + in gfx_v11_0_load_rlcp_rlcv_microcode()
1841 WREG32_SOC15(GC, 0, regRLC_PACE_UCODE_ADDR, adev->gfx.rlc_fw_version); in gfx_v11_0_load_rlcp_rlcv_microcode()
1847 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + in gfx_v11_0_load_rlcp_rlcv_microcode()
1860 WREG32_SOC15(GC, 0, regRLC_GPU_IOV_UCODE_ADDR, adev->gfx.rlc_fw_version); in gfx_v11_0_load_rlcp_rlcv_microcode()
1873 if (!adev->gfx.rlc_fw) in gfx_v11_0_rlc_load_microcode()
1876 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; in gfx_v11_0_rlc_load_microcode()
1912 adev->gfx.rlc.funcs->stop(adev); in gfx_v11_0_rlc_resume()
1929 adev->gfx.rlc.funcs->start(adev); in gfx_v11_0_rlc_resume()
2074 adev->gfx.pfp_fw->data; in gfx_v11_0_config_pfp_cache_rs64()
2124 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { in gfx_v11_0_config_pfp_cache_rs64()
2196 adev->gfx.me_fw->data; in gfx_v11_0_config_me_cache_rs64()
2247 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { in gfx_v11_0_config_me_cache_rs64()
2319 adev->gfx.mec_fw->data; in gfx_v11_0_config_mec_cache_rs64()
2333 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { in gfx_v11_0_config_mec_cache_rs64()
2402 adev->gfx.mec_fw->data; in gfx_v11_0_config_gfx_rs64()
2404 adev->gfx.me_fw->data; in gfx_v11_0_config_gfx_rs64()
2406 adev->gfx.pfp_fw->data; in gfx_v11_0_config_gfx_rs64()
2509 if (adev->gfx.rs64_enable) { in gfx_v11_0_wait_for_rlc_autoload_complete()
2510 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + in gfx_v11_0_wait_for_rlc_autoload_complete()
2512 addr2 = adev->gfx.rlc.rlc_autoload_gpu_addr + in gfx_v11_0_wait_for_rlc_autoload_complete()
2517 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + in gfx_v11_0_wait_for_rlc_autoload_complete()
2519 addr2 = adev->gfx.rlc.rlc_autoload_gpu_addr + in gfx_v11_0_wait_for_rlc_autoload_complete()
2524 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + in gfx_v11_0_wait_for_rlc_autoload_complete()
2526 addr2 = adev->gfx.rlc.rlc_autoload_gpu_addr + in gfx_v11_0_wait_for_rlc_autoload_complete()
2532 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + in gfx_v11_0_wait_for_rlc_autoload_complete()
2537 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + in gfx_v11_0_wait_for_rlc_autoload_complete()
2542 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + in gfx_v11_0_wait_for_rlc_autoload_complete()
2569 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt"); in gfx_v11_0_cp_gfx_enable()
2582 adev->gfx.pfp_fw->data; in gfx_v11_0_cp_gfx_load_pfp_microcode()
2586 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + in gfx_v11_0_cp_gfx_load_pfp_microcode()
2592 &adev->gfx.pfp.pfp_fw_obj, in gfx_v11_0_cp_gfx_load_pfp_microcode()
2593 &adev->gfx.pfp.pfp_fw_gpu_addr, in gfx_v11_0_cp_gfx_load_pfp_microcode()
2594 (void **)&adev->gfx.pfp.pfp_fw_ptr); in gfx_v11_0_cp_gfx_load_pfp_microcode()
2601 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size); in gfx_v11_0_cp_gfx_load_pfp_microcode()
2603 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj); in gfx_v11_0_cp_gfx_load_pfp_microcode()
2604 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj); in gfx_v11_0_cp_gfx_load_pfp_microcode()
2606 gfx_v11_0_config_pfp_cache(adev, adev->gfx.pfp.pfp_fw_gpu_addr); in gfx_v11_0_cp_gfx_load_pfp_microcode()
2614 WREG32_SOC15(GC, 0, regCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version); in gfx_v11_0_cp_gfx_load_pfp_microcode()
2629 adev->gfx.pfp_fw->data; in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
2634 fw_ucode = (const __le32 *)(adev->gfx.pfp_fw->data + in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
2638 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
2645 &adev->gfx.pfp.pfp_fw_obj, in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
2646 &adev->gfx.pfp.pfp_fw_gpu_addr, in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
2647 (void **)&adev->gfx.pfp.pfp_fw_ptr); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
2656 &adev->gfx.pfp.pfp_fw_data_obj, in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
2657 &adev->gfx.pfp.pfp_fw_data_gpu_addr, in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
2658 (void **)&adev->gfx.pfp.pfp_fw_data_ptr); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
2665 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_ucode, fw_ucode_size); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
2666 memcpy(adev->gfx.pfp.pfp_fw_data_ptr, fw_data, fw_data_size); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
2668 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
2669 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_data_obj); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
2670 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
2671 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_data_obj); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
2677 lower_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
2679 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
2724 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
2755 lower_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr)); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
2757 upper_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr)); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
2796 adev->gfx.me_fw->data; in gfx_v11_0_cp_gfx_load_me_microcode()
2800 fw_data = (const __le32 *)(adev->gfx.me_fw->data + in gfx_v11_0_cp_gfx_load_me_microcode()
2806 &adev->gfx.me.me_fw_obj, in gfx_v11_0_cp_gfx_load_me_microcode()
2807 &adev->gfx.me.me_fw_gpu_addr, in gfx_v11_0_cp_gfx_load_me_microcode()
2808 (void **)&adev->gfx.me.me_fw_ptr); in gfx_v11_0_cp_gfx_load_me_microcode()
2815 memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size); in gfx_v11_0_cp_gfx_load_me_microcode()
2817 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj); in gfx_v11_0_cp_gfx_load_me_microcode()
2818 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj); in gfx_v11_0_cp_gfx_load_me_microcode()
2820 gfx_v11_0_config_me_cache(adev, adev->gfx.me.me_fw_gpu_addr); in gfx_v11_0_cp_gfx_load_me_microcode()
2828 WREG32_SOC15(GC, 0, regCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version); in gfx_v11_0_cp_gfx_load_me_microcode()
2843 adev->gfx.me_fw->data; in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
2848 fw_ucode = (const __le32 *)(adev->gfx.me_fw->data + in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
2852 fw_data = (const __le32 *)(adev->gfx.me_fw->data + in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
2859 &adev->gfx.me.me_fw_obj, in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
2860 &adev->gfx.me.me_fw_gpu_addr, in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
2861 (void **)&adev->gfx.me.me_fw_ptr); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
2870 &adev->gfx.me.me_fw_data_obj, in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
2871 &adev->gfx.me.me_fw_data_gpu_addr, in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
2872 (void **)&adev->gfx.me.me_fw_data_ptr); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
2879 memcpy(adev->gfx.me.me_fw_ptr, fw_ucode, fw_ucode_size); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
2880 memcpy(adev->gfx.me.me_fw_data_ptr, fw_data, fw_data_size); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
2882 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
2883 amdgpu_bo_kunmap(adev->gfx.me.me_fw_data_obj); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
2884 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
2885 amdgpu_bo_unreserve(adev->gfx.me.me_fw_data_obj); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
2891 lower_32_bits(adev->gfx.me.me_fw_gpu_addr)); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
2893 upper_32_bits(adev->gfx.me.me_fw_gpu_addr)); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
2939 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
2970 lower_32_bits(adev->gfx.me.me_fw_data_gpu_addr)); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
2972 upper_32_bits(adev->gfx.me.me_fw_data_gpu_addr)); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3007 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw) in gfx_v11_0_cp_gfx_load_microcode()
3012 if (adev->gfx.rs64_enable) in gfx_v11_0_cp_gfx_load_microcode()
3021 if (adev->gfx.rs64_enable) in gfx_v11_0_cp_gfx_load_microcode()
3043 adev->gfx.config.max_hw_contexts - 1); in gfx_v11_0_cp_gfx_start()
3049 ring = &adev->gfx.gfx_ring[0]; in gfx_v11_0_cp_gfx_start()
3081 amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override); in gfx_v11_0_cp_gfx_start()
3092 if (adev->gfx.num_gfx_rings > 1) { in gfx_v11_0_cp_gfx_start()
3093 /* maximum supported gfx ring is 2 */ in gfx_v11_0_cp_gfx_start()
3094 ring = &adev->gfx.gfx_ring[1]; in gfx_v11_0_cp_gfx_start()
3159 /* Init gfx ring 0 for pipe 0 */ in gfx_v11_0_cp_gfx_resume()
3164 ring = &adev->gfx.gfx_ring[0]; in gfx_v11_0_cp_gfx_resume()
3199 /* Init gfx ring 1 for pipe 1 */ in gfx_v11_0_cp_gfx_resume()
3200 if (adev->gfx.num_gfx_rings > 1) { in gfx_v11_0_cp_gfx_resume()
3203 /* maximum supported gfx ring is 2 */ in gfx_v11_0_cp_gfx_resume()
3204 ring = &adev->gfx.gfx_ring[1]; in gfx_v11_0_cp_gfx_resume()
3243 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { in gfx_v11_0_cp_gfx_resume()
3244 ring = &adev->gfx.gfx_ring[i]; in gfx_v11_0_cp_gfx_resume()
3255 if (adev->gfx.rs64_enable) { in gfx_v11_0_cp_compute_enable()
3293 adev->gfx.kiq.ring.sched.ready = enable; in gfx_v11_0_cp_compute_enable()
3306 if (!adev->gfx.mec_fw) in gfx_v11_0_cp_compute_load_microcode()
3311 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; in gfx_v11_0_cp_compute_load_microcode()
3315 (adev->gfx.mec_fw->data + in gfx_v11_0_cp_compute_load_microcode()
3321 &adev->gfx.mec.mec_fw_obj, in gfx_v11_0_cp_compute_load_microcode()
3322 &adev->gfx.mec.mec_fw_gpu_addr, in gfx_v11_0_cp_compute_load_microcode()
3332 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); in gfx_v11_0_cp_compute_load_microcode()
3333 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); in gfx_v11_0_cp_compute_load_microcode()
3335 gfx_v11_0_config_mec_cache(adev, adev->gfx.mec.mec_fw_gpu_addr); in gfx_v11_0_cp_compute_load_microcode()
3344 WREG32_SOC15(GC, 0, regCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version); in gfx_v11_0_cp_compute_load_microcode()
3358 if (!adev->gfx.mec_fw) in gfx_v11_0_cp_compute_load_microcode_rs64()
3363 mec_hdr = (const struct gfx_firmware_header_v2_0 *)adev->gfx.mec_fw->data; in gfx_v11_0_cp_compute_load_microcode_rs64()
3366 fw_ucode = (const __le32 *) (adev->gfx.mec_fw->data + in gfx_v11_0_cp_compute_load_microcode_rs64()
3370 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + in gfx_v11_0_cp_compute_load_microcode_rs64()
3376 &adev->gfx.mec.mec_fw_obj, in gfx_v11_0_cp_compute_load_microcode_rs64()
3377 &adev->gfx.mec.mec_fw_gpu_addr, in gfx_v11_0_cp_compute_load_microcode_rs64()
3387 &adev->gfx.mec.mec_fw_data_obj, in gfx_v11_0_cp_compute_load_microcode_rs64()
3388 &adev->gfx.mec.mec_fw_data_gpu_addr, in gfx_v11_0_cp_compute_load_microcode_rs64()
3399 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); in gfx_v11_0_cp_compute_load_microcode_rs64()
3400 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_data_obj); in gfx_v11_0_cp_compute_load_microcode_rs64()
3401 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); in gfx_v11_0_cp_compute_load_microcode_rs64()
3402 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_data_obj); in gfx_v11_0_cp_compute_load_microcode_rs64()
3416 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { in gfx_v11_0_cp_compute_load_microcode_rs64()
3419 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_LO, adev->gfx.mec.mec_fw_data_gpu_addr); in gfx_v11_0_cp_compute_load_microcode_rs64()
3421 upper_32_bits(adev->gfx.mec.mec_fw_data_gpu_addr)); in gfx_v11_0_cp_compute_load_microcode_rs64()
3429 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr); in gfx_v11_0_cp_compute_load_microcode_rs64()
3431 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); in gfx_v11_0_cp_compute_load_microcode_rs64()
3514 /* set up gfx hqd wptr */ in gfx_v11_0_gfx_mqd_init()
3545 /* set up gfx hqd base. this is similar as CP_RB_BASE */ in gfx_v11_0_gfx_mqd_init()
3645 int mqd_idx = ring - &adev->gfx.gfx_ring[0]; in gfx_v11_0_gfx_init_queue()
3657 if (adev->gfx.me.mqd_backup[mqd_idx]) in gfx_v11_0_gfx_init_queue()
3658 memcpy(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); in gfx_v11_0_gfx_init_queue()
3661 if (adev->gfx.me.mqd_backup[mqd_idx]) in gfx_v11_0_gfx_init_queue()
3662 memcpy(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd)); in gfx_v11_0_gfx_init_queue()
3684 struct amdgpu_kiq *kiq = &adev->gfx.kiq; in gfx_v11_0_kiq_enable_kgq()
3685 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; in gfx_v11_0_kiq_enable_kgq()
3692 adev->gfx.num_gfx_rings); in gfx_v11_0_kiq_enable_kgq()
3698 for (i = 0; i < adev->gfx.num_gfx_rings; i++) in gfx_v11_0_kiq_enable_kgq()
3699 kiq->pmf->kiq_map_queues(kiq_ring, &adev->gfx.gfx_ring[i]); in gfx_v11_0_kiq_enable_kgq()
3710 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { in gfx_v11_0_cp_async_gfx_ring_resume()
3711 ring = &adev->gfx.gfx_ring[i]; in gfx_v11_0_cp_async_gfx_ring_resume()
3736 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { in gfx_v11_0_cp_async_gfx_ring_resume()
3737 ring = &adev->gfx.gfx_ring[i]; in gfx_v11_0_cp_async_gfx_ring_resume()
3993 if (adev->gfx.mec.mqd_backup[mqd_idx]) in gfx_v11_0_kiq_init_queue()
3994 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); in gfx_v11_0_kiq_init_queue()
4014 if (adev->gfx.mec.mqd_backup[mqd_idx]) in gfx_v11_0_kiq_init_queue()
4015 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); in gfx_v11_0_kiq_init_queue()
4025 int mqd_idx = ring - &adev->gfx.compute_ring[0]; in gfx_v11_0_kcq_init_queue()
4035 if (adev->gfx.mec.mqd_backup[mqd_idx]) in gfx_v11_0_kcq_init_queue()
4036 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); in gfx_v11_0_kcq_init_queue()
4039 if (adev->gfx.mec.mqd_backup[mqd_idx]) in gfx_v11_0_kcq_init_queue()
4040 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); in gfx_v11_0_kcq_init_queue()
4058 ring = &adev->gfx.kiq.ring; in gfx_v11_0_kiq_resume()
4086 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v11_0_kcq_resume()
4087 ring = &adev->gfx.compute_ring[i]; in gfx_v11_0_kcq_resume()
4122 if (adev->gfx.rs64_enable) in gfx_v11_0_cp_resume()
4158 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { in gfx_v11_0_cp_resume()
4159 ring = &adev->gfx.gfx_ring[i]; in gfx_v11_0_cp_resume()
4165 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v11_0_cp_resume()
4166 ring = &adev->gfx.compute_ring[i]; in gfx_v11_0_cp_resume()
4206 if (adev->gfx.rs64_enable) { in gfx_v11_0_select_cp_fw_arch()
4228 adev->gfx.config.gb_addr_config_fields.num_pkrs = in get_gb_addr_config()
4231 adev->gfx.config.gb_addr_config = gb_addr_config; in get_gb_addr_config()
4233 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << in get_gb_addr_config()
4234 REG_GET_FIELD(adev->gfx.config.gb_addr_config, in get_gb_addr_config()
4237 adev->gfx.config.max_tile_pipes = in get_gb_addr_config()
4238 adev->gfx.config.gb_addr_config_fields.num_pipes; in get_gb_addr_config()
4240 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << in get_gb_addr_config()
4241 REG_GET_FIELD(adev->gfx.config.gb_addr_config, in get_gb_addr_config()
4243 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << in get_gb_addr_config()
4244 REG_GET_FIELD(adev->gfx.config.gb_addr_config, in get_gb_addr_config()
4246 adev->gfx.config.gb_addr_config_fields.num_se = 1 << in get_gb_addr_config()
4247 REG_GET_FIELD(adev->gfx.config.gb_addr_config, in get_gb_addr_config()
4249 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + in get_gb_addr_config()
4250 REG_GET_FIELD(adev->gfx.config.gb_addr_config, in get_gb_addr_config()
4275 if (adev->gfx.imu.funcs) { in gfx_v11_0_hw_init()
4277 if (adev->gfx.imu.funcs->program_rlc_ram) in gfx_v11_0_hw_init()
4278 adev->gfx.imu.funcs->program_rlc_ram(adev); in gfx_v11_0_hw_init()
4286 if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) { in gfx_v11_0_hw_init()
4287 if (adev->gfx.imu.funcs->load_microcode) in gfx_v11_0_hw_init()
4288 adev->gfx.imu.funcs->load_microcode(adev); in gfx_v11_0_hw_init()
4289 if (adev->gfx.imu.funcs->setup_imu) in gfx_v11_0_hw_init()
4290 adev->gfx.imu.funcs->setup_imu(adev); in gfx_v11_0_hw_init()
4291 if (adev->gfx.imu.funcs->start_imu) in gfx_v11_0_hw_init()
4292 adev->gfx.imu.funcs->start_imu(adev); in gfx_v11_0_hw_init()
4309 adev->gfx.is_poweron = true; in gfx_v11_0_hw_init()
4315 adev->gfx.rs64_enable) in gfx_v11_0_hw_init()
4328 * For gfx 11, rlc firmware loading relies on smu firmware is in gfx_v11_0_hw_init()
4367 struct amdgpu_kiq *kiq = &adev->gfx.kiq; in gfx_v11_0_kiq_disable_kgq()
4375 adev->gfx.num_gfx_rings)) in gfx_v11_0_kiq_disable_kgq()
4378 for (i = 0; i < adev->gfx.num_gfx_rings; i++) in gfx_v11_0_kiq_disable_kgq()
4379 kiq->pmf->kiq_unmap_queues(kiq_ring, &adev->gfx.gfx_ring[i], in gfx_v11_0_kiq_disable_kgq()
4382 if (adev->gfx.kiq.ring.sched.ready) in gfx_v11_0_kiq_disable_kgq()
4395 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); in gfx_v11_0_hw_fini()
4396 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); in gfx_v11_0_hw_fini()
4426 adev->gfx.is_poweron = false; in gfx_v11_0_hw_fini()
4486 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { in gfx_v11_0_soft_reset()
4487 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { in gfx_v11_0_soft_reset()
4488 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { in gfx_v11_0_soft_reset()
4500 for (i = 0; i < adev->gfx.me.num_me; ++i) { in gfx_v11_0_soft_reset()
4501 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) { in gfx_v11_0_soft_reset()
4502 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { in gfx_v11_0_soft_reset()
4596 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { in gfx_v11_0_check_soft_reset()
4597 ring = &adev->gfx.gfx_ring[i]; in gfx_v11_0_check_soft_reset()
4603 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v11_0_check_soft_reset()
4604 ring = &adev->gfx.compute_ring[i]; in gfx_v11_0_check_soft_reset()
4618 mutex_lock(&adev->gfx.gpu_clock_mutex); in gfx_v11_0_get_gpu_clock_counter()
4621 mutex_unlock(&adev->gfx.gpu_clock_mutex); in gfx_v11_0_get_gpu_clock_counter()
4659 adev->gfx.num_gfx_rings = GFX11_NUM_GFX_RINGS; in gfx_v11_0_early_init()
4660 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), in gfx_v11_0_early_init()
4681 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); in gfx_v11_0_late_init()
4685 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); in gfx_v11_0_late_init()
5481 /* set load_per_context_state & load_gfx_sh_regs for GFX */ in gfx_v11_0_ring_emit_cntxcntl()
5521 struct amdgpu_kiq *kiq = &adev->gfx.kiq; in gfx_v11_0_ring_preempt_ib()
5574 gfx[0].gfx_meta_data) + in gfx_v11_0_ring_emit_de_meta()
5582 gfx[0].gds_backup) + in gfx_v11_0_ring_emit_de_meta()
5857 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); in gfx_v11_0_eop_irq()
5859 amdgpu_fence_process(&adev->gfx.gfx_ring[1]); in gfx_v11_0_eop_irq()
5863 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v11_0_eop_irq()
5864 ring = &adev->gfx.compute_ring[i]; in gfx_v11_0_eop_irq()
5932 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { in gfx_v11_0_handle_priv_fault()
5933 ring = &adev->gfx.gfx_ring[i]; in gfx_v11_0_handle_priv_fault()
5934 /* we only enabled 1 gfx queue per pipe for now */ in gfx_v11_0_handle_priv_fault()
5941 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v11_0_handle_priv_fault()
5942 ring = &adev->gfx.compute_ring[i]; in gfx_v11_0_handle_priv_fault()
5979 struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
6177 adev->gfx.kiq.ring.funcs = &gfx_v11_0_ring_funcs_kiq; in gfx_v11_0_set_ring_funcs()
6179 for (i = 0; i < adev->gfx.num_gfx_rings; i++) in gfx_v11_0_set_ring_funcs()
6180 adev->gfx.gfx_ring[i].funcs = &gfx_v11_0_ring_funcs_gfx; in gfx_v11_0_set_ring_funcs()
6182 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v11_0_set_ring_funcs()
6183 adev->gfx.compute_ring[i].funcs = &gfx_v11_0_ring_funcs_compute; in gfx_v11_0_set_ring_funcs()
6203 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; in gfx_v11_0_set_irq_funcs()
6204 adev->gfx.eop_irq.funcs = &gfx_v11_0_eop_irq_funcs; in gfx_v11_0_set_irq_funcs()
6206 adev->gfx.priv_reg_irq.num_types = 1; in gfx_v11_0_set_irq_funcs()
6207 adev->gfx.priv_reg_irq.funcs = &gfx_v11_0_priv_reg_irq_funcs; in gfx_v11_0_set_irq_funcs()
6209 adev->gfx.priv_inst_irq.num_types = 1; in gfx_v11_0_set_irq_funcs()
6210 adev->gfx.priv_inst_irq.funcs = &gfx_v11_0_priv_inst_irq_funcs; in gfx_v11_0_set_irq_funcs()
6216 adev->gfx.imu.mode = MISSION_MODE; in gfx_v11_0_set_imu_funcs()
6218 adev->gfx.imu.mode = DEBUG_MODE; in gfx_v11_0_set_imu_funcs()
6220 adev->gfx.imu.funcs = &gfx_v11_0_imu_funcs; in gfx_v11_0_set_imu_funcs()
6225 adev->gfx.rlc.funcs = &gfx_v11_0_rlc_funcs; in gfx_v11_0_set_rlc_funcs()
6230 unsigned total_cu = adev->gfx.config.max_cu_per_sh * in gfx_v11_0_set_gds_init()
6231 adev->gfx.config.max_sh_per_se * in gfx_v11_0_set_gds_init()
6232 adev->gfx.config.max_shader_engines; in gfx_v11_0_set_gds_init()
6242 /* set gfx eng mqd */ in gfx_v11_0_set_mqd_funcs()
6278 amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1); in gfx_v11_0_get_wgp_active_bitmap_per_sh()
6314 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v11_0_get_cu_info()
6315 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v11_0_get_cu_info()
6341 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { in gfx_v11_0_get_cu_info()