Lines Matching full:gfx
930 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); in gfx_v7_0_init_microcode()
933 err = amdgpu_ucode_validate(adev->gfx.pfp_fw); in gfx_v7_0_init_microcode()
938 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); in gfx_v7_0_init_microcode()
941 err = amdgpu_ucode_validate(adev->gfx.me_fw); in gfx_v7_0_init_microcode()
946 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); in gfx_v7_0_init_microcode()
949 err = amdgpu_ucode_validate(adev->gfx.ce_fw); in gfx_v7_0_init_microcode()
954 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); in gfx_v7_0_init_microcode()
957 err = amdgpu_ucode_validate(adev->gfx.mec_fw); in gfx_v7_0_init_microcode()
963 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); in gfx_v7_0_init_microcode()
966 err = amdgpu_ucode_validate(adev->gfx.mec2_fw); in gfx_v7_0_init_microcode()
972 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); in gfx_v7_0_init_microcode()
975 err = amdgpu_ucode_validate(adev->gfx.rlc_fw); in gfx_v7_0_init_microcode()
980 release_firmware(adev->gfx.pfp_fw); in gfx_v7_0_init_microcode()
981 adev->gfx.pfp_fw = NULL; in gfx_v7_0_init_microcode()
982 release_firmware(adev->gfx.me_fw); in gfx_v7_0_init_microcode()
983 adev->gfx.me_fw = NULL; in gfx_v7_0_init_microcode()
984 release_firmware(adev->gfx.ce_fw); in gfx_v7_0_init_microcode()
985 adev->gfx.ce_fw = NULL; in gfx_v7_0_init_microcode()
986 release_firmware(adev->gfx.mec_fw); in gfx_v7_0_init_microcode()
987 adev->gfx.mec_fw = NULL; in gfx_v7_0_init_microcode()
988 release_firmware(adev->gfx.mec2_fw); in gfx_v7_0_init_microcode()
989 adev->gfx.mec2_fw = NULL; in gfx_v7_0_init_microcode()
990 release_firmware(adev->gfx.rlc_fw); in gfx_v7_0_init_microcode()
991 adev->gfx.rlc_fw = NULL; in gfx_v7_0_init_microcode()
998 release_firmware(adev->gfx.pfp_fw); in gfx_v7_0_free_microcode()
999 adev->gfx.pfp_fw = NULL; in gfx_v7_0_free_microcode()
1000 release_firmware(adev->gfx.me_fw); in gfx_v7_0_free_microcode()
1001 adev->gfx.me_fw = NULL; in gfx_v7_0_free_microcode()
1002 release_firmware(adev->gfx.ce_fw); in gfx_v7_0_free_microcode()
1003 adev->gfx.ce_fw = NULL; in gfx_v7_0_free_microcode()
1004 release_firmware(adev->gfx.mec_fw); in gfx_v7_0_free_microcode()
1005 adev->gfx.mec_fw = NULL; in gfx_v7_0_free_microcode()
1006 release_firmware(adev->gfx.mec2_fw); in gfx_v7_0_free_microcode()
1007 adev->gfx.mec2_fw = NULL; in gfx_v7_0_free_microcode()
1008 release_firmware(adev->gfx.rlc_fw); in gfx_v7_0_free_microcode()
1009 adev->gfx.rlc_fw = NULL; in gfx_v7_0_free_microcode()
1026 ARRAY_SIZE(adev->gfx.config.tile_mode_array); in gfx_v7_0_tiling_mode_table_init()
1028 ARRAY_SIZE(adev->gfx.config.macrotile_mode_array); in gfx_v7_0_tiling_mode_table_init()
1032 tile = adev->gfx.config.tile_mode_array; in gfx_v7_0_tiling_mode_table_init()
1033 macrotile = adev->gfx.config.macrotile_mode_array; in gfx_v7_0_tiling_mode_table_init()
1035 switch (adev->gfx.config.mem_row_size_in_kb) { in gfx_v7_0_tiling_mode_table_init()
1631 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / in gfx_v7_0_get_rb_active_bitmap()
1632 adev->gfx.config.max_sh_per_se); in gfx_v7_0_get_rb_active_bitmap()
1674 unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1); in gfx_v7_0_write_harvested_raster_configs()
1675 unsigned num_se = max_t(unsigned, adev->gfx.config.max_shader_engines, 1); in gfx_v7_0_write_harvested_raster_configs()
1791 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / in gfx_v7_0_setup_rb()
1792 adev->gfx.config.max_sh_per_se; in gfx_v7_0_setup_rb()
1796 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v7_0_setup_rb()
1797 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v7_0_setup_rb()
1800 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * in gfx_v7_0_setup_rb()
1806 adev->gfx.config.backend_enable_mask = active_rbs; in gfx_v7_0_setup_rb()
1807 adev->gfx.config.num_rbs = hweight32(active_rbs); in gfx_v7_0_setup_rb()
1809 num_rb_pipes = min_t(unsigned, adev->gfx.config.max_backends_per_se * in gfx_v7_0_setup_rb()
1810 adev->gfx.config.max_shader_engines, 16); in gfx_v7_0_setup_rb()
1814 if (!adev->gfx.config.backend_enable_mask || in gfx_v7_0_setup_rb()
1815 adev->gfx.config.num_rbs >= num_rb_pipes) { in gfx_v7_0_setup_rb()
1820 adev->gfx.config.backend_enable_mask, in gfx_v7_0_setup_rb()
1825 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v7_0_setup_rb()
1826 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v7_0_setup_rb()
1828 adev->gfx.config.rb_config[i][j].rb_backend_disable = in gfx_v7_0_setup_rb()
1830 adev->gfx.config.rb_config[i][j].user_rb_backend_disable = in gfx_v7_0_setup_rb()
1832 adev->gfx.config.rb_config[i][j].raster_config = in gfx_v7_0_setup_rb()
1834 adev->gfx.config.rb_config[i][j].raster_config_1 = in gfx_v7_0_setup_rb()
1894 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA in gfx_v7_0_init_gds_vmid()
1909 adev->gfx.config.double_offchip_lds_buf = 1; in gfx_v7_0_config_init()
1917 * init the gfx constants such as the 3D engine, tiling configuration
1928 WREG32(mmGB_ADDR_CONFIG, adev->gfx.config.gb_addr_config); in gfx_v7_0_constants_init()
1929 WREG32(mmHDP_ADDR_CONFIG, adev->gfx.config.gb_addr_config); in gfx_v7_0_constants_init()
1930 WREG32(mmDMIF_ADDR_CALC, adev->gfx.config.gb_addr_config); in gfx_v7_0_constants_init()
2014 …((adev->gfx.config.sc_prim_fifo_size_frontend << PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIF… in gfx_v7_0_constants_init()
2015 …(adev->gfx.config.sc_prim_fifo_size_backend << PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) | in gfx_v7_0_constants_init()
2016 (adev->gfx.config.sc_hiz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) | in gfx_v7_0_constants_init()
2017 (adev->gfx.config.sc_earlyz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT))); in gfx_v7_0_constants_init()
2053 * gfx_v7_0_ring_test_ring - basic gfx ring test
2057 * Allocate a scratch register and write to it using the gfx ring (CIK).
2058 * Provides a basic gfx ring test to verify that the ring is working.
2140 * gfx_v7_0_ring_emit_fence_gfx - emit a fence on the gfx ring
2147 * Emits a fence sequence number on the gfx ring and flushes
2225 * on the gfx ring. IBs are usually generated by userspace
2228 * on the gfx ring for execution by the GPU.
2321 * Allocate an IB and execute it on the gfx ring (CIK).
2322 * Provides a basic gfx ring test to verify that IBs are working.
2369 * On CIK, gfx and compute now have independent command processors.
2371 * GFX
2372 * Gfx consists of a single ring and can process both gfx jobs and
2373 * compute jobs. The gfx CP consists of three microengines (ME):
2391 * gfx_v7_0_cp_gfx_enable - enable/disable the gfx CP MEs
2396 * Halts or unhalts the gfx MEs.
2410 * gfx_v7_0_cp_gfx_load_microcode - load the gfx CP ME ucode
2414 * Loads the gfx PFP, ME, and CE ucode.
2425 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) in gfx_v7_0_cp_gfx_load_microcode()
2428 pfp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; in gfx_v7_0_cp_gfx_load_microcode()
2429 ce_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; in gfx_v7_0_cp_gfx_load_microcode()
2430 me_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; in gfx_v7_0_cp_gfx_load_microcode()
2435 adev->gfx.pfp_fw_version = le32_to_cpu(pfp_hdr->header.ucode_version); in gfx_v7_0_cp_gfx_load_microcode()
2436 adev->gfx.ce_fw_version = le32_to_cpu(ce_hdr->header.ucode_version); in gfx_v7_0_cp_gfx_load_microcode()
2437 adev->gfx.me_fw_version = le32_to_cpu(me_hdr->header.ucode_version); in gfx_v7_0_cp_gfx_load_microcode()
2438 adev->gfx.me_feature_version = le32_to_cpu(me_hdr->ucode_feature_version); in gfx_v7_0_cp_gfx_load_microcode()
2439 adev->gfx.ce_feature_version = le32_to_cpu(ce_hdr->ucode_feature_version); in gfx_v7_0_cp_gfx_load_microcode()
2440 adev->gfx.pfp_feature_version = le32_to_cpu(pfp_hdr->ucode_feature_version); in gfx_v7_0_cp_gfx_load_microcode()
2446 (adev->gfx.pfp_fw->data + in gfx_v7_0_cp_gfx_load_microcode()
2452 WREG32(mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version); in gfx_v7_0_cp_gfx_load_microcode()
2456 (adev->gfx.ce_fw->data + in gfx_v7_0_cp_gfx_load_microcode()
2462 WREG32(mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version); in gfx_v7_0_cp_gfx_load_microcode()
2466 (adev->gfx.me_fw->data + in gfx_v7_0_cp_gfx_load_microcode()
2472 WREG32(mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version); in gfx_v7_0_cp_gfx_load_microcode()
2478 * gfx_v7_0_cp_gfx_start - start the gfx ring
2488 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0]; in gfx_v7_0_cp_gfx_start()
2494 WREG32(mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1); in gfx_v7_0_cp_gfx_start()
2506 /* init the CE partitions. CE only used for gfx on CIK */ in gfx_v7_0_cp_gfx_start()
2520 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { in gfx_v7_0_cp_gfx_start()
2534 amdgpu_ring_write(ring, adev->gfx.config.rb_config[0][0].raster_config); in gfx_v7_0_cp_gfx_start()
2535 amdgpu_ring_write(ring, adev->gfx.config.rb_config[0][0].raster_config_1); in gfx_v7_0_cp_gfx_start()
2554 * gfx_v7_0_cp_gfx_resume - setup the gfx ring buffer registers
2558 * Program the location and size of the gfx ring buffer
2582 /* ring 0 - compute and gfx */ in gfx_v7_0_cp_gfx_resume()
2584 ring = &adev->gfx.gfx_ring[0]; in gfx_v7_0_cp_gfx_resume()
2688 if (!adev->gfx.mec_fw) in gfx_v7_0_cp_compute_load_microcode()
2691 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; in gfx_v7_0_cp_compute_load_microcode()
2693 adev->gfx.mec_fw_version = le32_to_cpu(mec_hdr->header.ucode_version); in gfx_v7_0_cp_compute_load_microcode()
2694 adev->gfx.mec_feature_version = le32_to_cpu( in gfx_v7_0_cp_compute_load_microcode()
2701 (adev->gfx.mec_fw->data + in gfx_v7_0_cp_compute_load_microcode()
2712 if (!adev->gfx.mec2_fw) in gfx_v7_0_cp_compute_load_microcode()
2715 mec2_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data; in gfx_v7_0_cp_compute_load_microcode()
2717 adev->gfx.mec2_fw_version = le32_to_cpu(mec2_hdr->header.ucode_version); in gfx_v7_0_cp_compute_load_microcode()
2718 adev->gfx.mec2_feature_version = le32_to_cpu( in gfx_v7_0_cp_compute_load_microcode()
2723 (adev->gfx.mec2_fw->data + in gfx_v7_0_cp_compute_load_microcode()
2747 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v7_0_cp_compute_fini()
2748 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i]; in gfx_v7_0_cp_compute_fini()
2756 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); in gfx_v7_0_mec_fini()
2765 bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); in gfx_v7_0_mec_init()
2771 mec_hpd_size = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec in gfx_v7_0_mec_init()
2776 &adev->gfx.mec.hpd_eop_obj, in gfx_v7_0_mec_init()
2777 &adev->gfx.mec.hpd_eop_gpu_addr, in gfx_v7_0_mec_init()
2788 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); in gfx_v7_0_mec_init()
2789 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); in gfx_v7_0_mec_init()
2838 size_t eop_offset = (mec * adev->gfx.mec.num_pipe_per_mec + pipe) in gfx_v7_0_compute_pipe_init()
2842 eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + eop_offset; in gfx_v7_0_compute_pipe_init()
3037 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id]; in gfx_v7_0_compute_queue_init()
3083 for (i = 0; i < adev->gfx.mec.num_mec; i++) in gfx_v7_0_cp_compute_resume()
3084 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) in gfx_v7_0_cp_compute_resume()
3088 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v7_0_cp_compute_resume()
3098 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v7_0_cp_compute_resume()
3099 ring = &adev->gfx.compute_ring[i]; in gfx_v7_0_cp_compute_resume()
3271 adev->gfx.rlc.reg_list = spectre_rlc_save_restore_register_list; in gfx_v7_0_rlc_init()
3272 adev->gfx.rlc.reg_list_size = in gfx_v7_0_rlc_init()
3275 adev->gfx.rlc.reg_list = kalindi_rlc_save_restore_register_list; in gfx_v7_0_rlc_init()
3276 adev->gfx.rlc.reg_list_size = in gfx_v7_0_rlc_init()
3280 adev->gfx.rlc.cs_data = ci_cs_data; in gfx_v7_0_rlc_init()
3281 adev->gfx.rlc.cp_table_size = ALIGN(CP_ME_TABLE_SIZE * 5 * 4, 2048); /* CP JT */ in gfx_v7_0_rlc_init()
3282 adev->gfx.rlc.cp_table_size += 64 * 1024; /* GDS */ in gfx_v7_0_rlc_init()
3284 src_ptr = adev->gfx.rlc.reg_list; in gfx_v7_0_rlc_init()
3285 dws = adev->gfx.rlc.reg_list_size; in gfx_v7_0_rlc_init()
3288 cs_data = adev->gfx.rlc.cs_data; in gfx_v7_0_rlc_init()
3304 if (adev->gfx.rlc.cp_table_size) { in gfx_v7_0_rlc_init()
3311 if (adev->gfx.rlc.funcs->update_spm_vmid) in gfx_v7_0_rlc_init()
3312 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf); in gfx_v7_0_rlc_init()
3335 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v7_0_wait_for_rlc_serdes()
3336 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v7_0_wait_for_rlc_serdes()
3487 if (!adev->gfx.rlc_fw) in gfx_v7_0_rlc_resume()
3490 hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data; in gfx_v7_0_rlc_resume()
3492 adev->gfx.rlc_fw_version = le32_to_cpu(hdr->header.ucode_version); in gfx_v7_0_rlc_resume()
3493 adev->gfx.rlc_feature_version = le32_to_cpu( in gfx_v7_0_rlc_resume()
3496 adev->gfx.rlc.funcs->stop(adev); in gfx_v7_0_rlc_resume()
3502 adev->gfx.rlc.funcs->reset(adev); in gfx_v7_0_rlc_resume()
3520 (adev->gfx.rlc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); in gfx_v7_0_rlc_resume()
3525 WREG32(mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); in gfx_v7_0_rlc_resume()
3533 adev->gfx.rlc.funcs->start(adev); in gfx_v7_0_rlc_resume()
3813 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh); in gfx_v7_0_get_cu_active_bitmap()
3822 WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask); in gfx_v7_0_init_ao_cu_mask()
3826 tmp |= (adev->gfx.cu_info.number << RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT); in gfx_v7_0_init_ao_cu_mask()
3866 if (adev->gfx.rlc.cs_data) { in gfx_v7_0_init_gfx_cgpg()
3868 WREG32(mmRLC_GPM_SCRATCH_DATA, upper_32_bits(adev->gfx.rlc.clear_state_gpu_addr)); in gfx_v7_0_init_gfx_cgpg()
3869 WREG32(mmRLC_GPM_SCRATCH_DATA, lower_32_bits(adev->gfx.rlc.clear_state_gpu_addr)); in gfx_v7_0_init_gfx_cgpg()
3870 WREG32(mmRLC_GPM_SCRATCH_DATA, adev->gfx.rlc.clear_state_size); in gfx_v7_0_init_gfx_cgpg()
3876 if (adev->gfx.rlc.reg_list) { in gfx_v7_0_init_gfx_cgpg()
3878 for (i = 0; i < adev->gfx.rlc.reg_list_size; i++) in gfx_v7_0_init_gfx_cgpg()
3879 WREG32(mmRLC_GPM_SCRATCH_DATA, adev->gfx.rlc.reg_list[i]); in gfx_v7_0_init_gfx_cgpg()
3887 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8); in gfx_v7_0_init_gfx_cgpg()
3888 WREG32(mmRLC_JUMP_TABLE_RESTORE, adev->gfx.rlc.cp_table_gpu_addr >> 8); in gfx_v7_0_init_gfx_cgpg()
3923 if (adev->gfx.rlc.cs_data == NULL) in gfx_v7_0_get_csb_size()
3931 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { in gfx_v7_0_get_csb_size()
3956 if (adev->gfx.rlc.cs_data == NULL) in gfx_v7_0_get_csb_buffer()
3968 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { in gfx_v7_0_get_csb_buffer()
4063 mutex_lock(&adev->gfx.gpu_clock_mutex); in gfx_v7_0_get_gpu_clock_counter()
4067 mutex_unlock(&adev->gfx.gpu_clock_mutex); in gfx_v7_0_get_gpu_clock_counter()
4214 adev->gfx.num_gfx_rings = GFX7_NUM_GFX_RINGS; in gfx_v7_0_early_init()
4215 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), in gfx_v7_0_early_init()
4217 adev->gfx.funcs = &gfx_v7_0_gfx_funcs; in gfx_v7_0_early_init()
4218 adev->gfx.rlc.funcs = &gfx_v7_0_rlc_funcs; in gfx_v7_0_early_init()
4231 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); in gfx_v7_0_late_init()
4235 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); in gfx_v7_0_late_init()
4251 adev->gfx.config.max_shader_engines = 2; in gfx_v7_0_gpu_early_init()
4252 adev->gfx.config.max_tile_pipes = 4; in gfx_v7_0_gpu_early_init()
4253 adev->gfx.config.max_cu_per_sh = 7; in gfx_v7_0_gpu_early_init()
4254 adev->gfx.config.max_sh_per_se = 1; in gfx_v7_0_gpu_early_init()
4255 adev->gfx.config.max_backends_per_se = 2; in gfx_v7_0_gpu_early_init()
4256 adev->gfx.config.max_texture_channel_caches = 4; in gfx_v7_0_gpu_early_init()
4257 adev->gfx.config.max_gprs = 256; in gfx_v7_0_gpu_early_init()
4258 adev->gfx.config.max_gs_threads = 32; in gfx_v7_0_gpu_early_init()
4259 adev->gfx.config.max_hw_contexts = 8; in gfx_v7_0_gpu_early_init()
4261 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v7_0_gpu_early_init()
4262 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v7_0_gpu_early_init()
4263 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v7_0_gpu_early_init()
4264 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v7_0_gpu_early_init()
4268 adev->gfx.config.max_shader_engines = 4; in gfx_v7_0_gpu_early_init()
4269 adev->gfx.config.max_tile_pipes = 16; in gfx_v7_0_gpu_early_init()
4270 adev->gfx.config.max_cu_per_sh = 11; in gfx_v7_0_gpu_early_init()
4271 adev->gfx.config.max_sh_per_se = 1; in gfx_v7_0_gpu_early_init()
4272 adev->gfx.config.max_backends_per_se = 4; in gfx_v7_0_gpu_early_init()
4273 adev->gfx.config.max_texture_channel_caches = 16; in gfx_v7_0_gpu_early_init()
4274 adev->gfx.config.max_gprs = 256; in gfx_v7_0_gpu_early_init()
4275 adev->gfx.config.max_gs_threads = 32; in gfx_v7_0_gpu_early_init()
4276 adev->gfx.config.max_hw_contexts = 8; in gfx_v7_0_gpu_early_init()
4278 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v7_0_gpu_early_init()
4279 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v7_0_gpu_early_init()
4280 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v7_0_gpu_early_init()
4281 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v7_0_gpu_early_init()
4285 adev->gfx.config.max_shader_engines = 1; in gfx_v7_0_gpu_early_init()
4286 adev->gfx.config.max_tile_pipes = 4; in gfx_v7_0_gpu_early_init()
4287 adev->gfx.config.max_cu_per_sh = 8; in gfx_v7_0_gpu_early_init()
4288 adev->gfx.config.max_backends_per_se = 2; in gfx_v7_0_gpu_early_init()
4289 adev->gfx.config.max_sh_per_se = 1; in gfx_v7_0_gpu_early_init()
4290 adev->gfx.config.max_texture_channel_caches = 4; in gfx_v7_0_gpu_early_init()
4291 adev->gfx.config.max_gprs = 256; in gfx_v7_0_gpu_early_init()
4292 adev->gfx.config.max_gs_threads = 16; in gfx_v7_0_gpu_early_init()
4293 adev->gfx.config.max_hw_contexts = 8; in gfx_v7_0_gpu_early_init()
4295 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v7_0_gpu_early_init()
4296 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v7_0_gpu_early_init()
4297 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v7_0_gpu_early_init()
4298 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v7_0_gpu_early_init()
4304 adev->gfx.config.max_shader_engines = 1; in gfx_v7_0_gpu_early_init()
4305 adev->gfx.config.max_tile_pipes = 2; in gfx_v7_0_gpu_early_init()
4306 adev->gfx.config.max_cu_per_sh = 2; in gfx_v7_0_gpu_early_init()
4307 adev->gfx.config.max_sh_per_se = 1; in gfx_v7_0_gpu_early_init()
4308 adev->gfx.config.max_backends_per_se = 1; in gfx_v7_0_gpu_early_init()
4309 adev->gfx.config.max_texture_channel_caches = 2; in gfx_v7_0_gpu_early_init()
4310 adev->gfx.config.max_gprs = 256; in gfx_v7_0_gpu_early_init()
4311 adev->gfx.config.max_gs_threads = 16; in gfx_v7_0_gpu_early_init()
4312 adev->gfx.config.max_hw_contexts = 8; in gfx_v7_0_gpu_early_init()
4314 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v7_0_gpu_early_init()
4315 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v7_0_gpu_early_init()
4316 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v7_0_gpu_early_init()
4317 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v7_0_gpu_early_init()
4322 adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG); in gfx_v7_0_gpu_early_init()
4323 mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg; in gfx_v7_0_gpu_early_init()
4325 adev->gfx.config.num_banks = REG_GET_FIELD(mc_arb_ramcfg, in gfx_v7_0_gpu_early_init()
4327 adev->gfx.config.num_ranks = REG_GET_FIELD(mc_arb_ramcfg, in gfx_v7_0_gpu_early_init()
4330 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes; in gfx_v7_0_gpu_early_init()
4331 adev->gfx.config.mem_max_burst_length_bytes = 256; in gfx_v7_0_gpu_early_init()
4355 adev->gfx.config.mem_row_size_in_kb = 2; in gfx_v7_0_gpu_early_init()
4357 adev->gfx.config.mem_row_size_in_kb = 1; in gfx_v7_0_gpu_early_init()
4360 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024; in gfx_v7_0_gpu_early_init()
4361 if (adev->gfx.config.mem_row_size_in_kb > 4) in gfx_v7_0_gpu_early_init()
4362 adev->gfx.config.mem_row_size_in_kb = 4; in gfx_v7_0_gpu_early_init()
4365 adev->gfx.config.shader_engine_tile_size = 32; in gfx_v7_0_gpu_early_init()
4366 adev->gfx.config.num_gpus = 1; in gfx_v7_0_gpu_early_init()
4367 adev->gfx.config.multi_gpu_tile_size = 64; in gfx_v7_0_gpu_early_init()
4371 switch (adev->gfx.config.mem_row_size_in_kb) { in gfx_v7_0_gpu_early_init()
4383 adev->gfx.config.gb_addr_config = gb_addr_config; in gfx_v7_0_gpu_early_init()
4391 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id]; in gfx_v7_0_compute_ring_init()
4404 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) in gfx_v7_0_compute_ring_init()
4409 &adev->gfx.eop_irq, irq_type, in gfx_v7_0_compute_ring_init()
4426 adev->gfx.mec.num_mec = 2; in gfx_v7_0_sw_init()
4433 adev->gfx.mec.num_mec = 1; in gfx_v7_0_sw_init()
4436 adev->gfx.mec.num_pipe_per_mec = 4; in gfx_v7_0_sw_init()
4437 adev->gfx.mec.num_queue_per_pipe = 8; in gfx_v7_0_sw_init()
4440 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 181, &adev->gfx.eop_irq); in gfx_v7_0_sw_init()
4446 &adev->gfx.priv_reg_irq); in gfx_v7_0_sw_init()
4452 &adev->gfx.priv_inst_irq); in gfx_v7_0_sw_init()
4458 DRM_ERROR("Failed to load gfx firmware!\n"); in gfx_v7_0_sw_init()
4462 r = adev->gfx.rlc.funcs->init(adev); in gfx_v7_0_sw_init()
4475 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { in gfx_v7_0_sw_init()
4476 ring = &adev->gfx.gfx_ring[i]; in gfx_v7_0_sw_init()
4478 sprintf(ring->name, "gfx"); in gfx_v7_0_sw_init()
4480 &adev->gfx.eop_irq, in gfx_v7_0_sw_init()
4489 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { in gfx_v7_0_sw_init()
4490 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { in gfx_v7_0_sw_init()
4491 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { in gfx_v7_0_sw_init()
4506 adev->gfx.ce_ram_size = 0x8000; in gfx_v7_0_sw_init()
4518 for (i = 0; i < adev->gfx.num_gfx_rings; i++) in gfx_v7_0_sw_fini()
4519 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); in gfx_v7_0_sw_fini()
4520 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v7_0_sw_fini()
4521 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); in gfx_v7_0_sw_fini()
4526 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, in gfx_v7_0_sw_fini()
4527 &adev->gfx.rlc.clear_state_gpu_addr, in gfx_v7_0_sw_fini()
4528 (void **)&adev->gfx.rlc.cs_ptr); in gfx_v7_0_sw_fini()
4529 if (adev->gfx.rlc.cp_table_size) { in gfx_v7_0_sw_fini()
4530 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, in gfx_v7_0_sw_fini()
4531 &adev->gfx.rlc.cp_table_gpu_addr, in gfx_v7_0_sw_fini()
4532 (void **)&adev->gfx.rlc.cp_table_ptr); in gfx_v7_0_sw_fini()
4547 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); in gfx_v7_0_hw_init()
4549 r = adev->gfx.rlc.funcs->resume(adev); in gfx_v7_0_hw_init()
4564 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); in gfx_v7_0_hw_fini()
4565 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); in gfx_v7_0_hw_fini()
4567 adev->gfx.rlc.funcs->stop(adev); in gfx_v7_0_hw_fini()
4652 adev->gfx.rlc.funcs->stop(adev); in gfx_v7_0_soft_reset()
4654 /* Disable GFX parsing/prefetching */ in gfx_v7_0_soft_reset()
4867 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); in gfx_v7_0_eop_irq()
4871 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v7_0_eop_irq()
4872 ring = &adev->gfx.compute_ring[i]; in gfx_v7_0_eop_irq()
4892 drm_sched_fault(&adev->gfx.gfx_ring[0].sched); in gfx_v7_0_fault()
4896 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v7_0_fault()
4897 ring = &adev->gfx.compute_ring[i]; in gfx_v7_0_fault()
4919 // XXX soft reset the gfx block only in gfx_v7_0_priv_inst_irq()
5084 for (i = 0; i < adev->gfx.num_gfx_rings; i++) in gfx_v7_0_set_ring_funcs()
5085 adev->gfx.gfx_ring[i].funcs = &gfx_v7_0_ring_funcs_gfx; in gfx_v7_0_set_ring_funcs()
5086 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v7_0_set_ring_funcs()
5087 adev->gfx.compute_ring[i].funcs = &gfx_v7_0_ring_funcs_compute; in gfx_v7_0_set_ring_funcs()
5107 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; in gfx_v7_0_set_irq_funcs()
5108 adev->gfx.eop_irq.funcs = &gfx_v7_0_eop_irq_funcs; in gfx_v7_0_set_irq_funcs()
5110 adev->gfx.priv_reg_irq.num_types = 1; in gfx_v7_0_set_irq_funcs()
5111 adev->gfx.priv_reg_irq.funcs = &gfx_v7_0_priv_reg_irq_funcs; in gfx_v7_0_set_irq_funcs()
5113 adev->gfx.priv_inst_irq.num_types = 1; in gfx_v7_0_set_irq_funcs()
5114 adev->gfx.priv_inst_irq.funcs = &gfx_v7_0_priv_inst_irq_funcs; in gfx_v7_0_set_irq_funcs()
5131 struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info; in gfx_v7_0_get_cu_info()
5138 ao_cu_num = adev->gfx.config.max_cu_per_sh; in gfx_v7_0_get_cu_info()
5145 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v7_0_get_cu_info()
5146 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v7_0_get_cu_info()
5157 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) { in gfx_v7_0_get_cu_info()