| /Linux-v5.10/arch/arm64/boot/dts/cavium/ |
| D | thunder-88xx.dtsi | 2 * Cavium Thunder DTS file - Thunder SoC description
6 * This file is dual-licensed: you can use it either under the terms
24 * MA 02110-1301 USA
51 compatible = "cavium,thunder-88xx";
52 interrupt-parent = <&gic0>;
53 #address-cells = <2>;
54 #size-cells = <2>;
57 compatible = "arm,psci-0.2";
58 method = "smc";
62 #address-cells = <2>;
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| /Linux-v5.10/Documentation/firmware-guide/acpi/ |
| D | method-tracing.rst | 1 .. SPDX-License-Identifier: GPL-2.0
15 method tracing facility.
20 ACPICA provides method tracing capability. And two functions are
24 -----------
28 ACPI_DEBUG_PRINT() macro can be reduced at 2 levels - per-component
30 /sys/module/acpi/parameters/debug_layer) and per-type level (known as
33 But when the particular layer/level is applied to the control method
36 to only enable the particular debug layer/level (normally more detailed)
37 logs when the control method evaluation is started, and disable the
38 detailed logging when the control method evaluation is stopped.
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| /Linux-v5.10/Documentation/devicetree/bindings/arm/ |
| D | cpus.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
21 with updates for 32-bit and 64-bit ARM systems provided in this document.
30 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
59 On 32-bit ARM v7 or later systems this property is
68 On ARM v8 64-bit systems this property is required
71 * If cpus node's #address-cells property is set to 2
79 * If cpus node's #address-cells property is set to 1
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| D | idle-states.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/idle-states.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
14 1 - Introduction
18 where cores can be put in different low-power states (ranging from simple wfi
20 range of dynamic idle states that a processor can enter at run-time, can be
27 - Running
28 - Idle_standby
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| /Linux-v5.10/arch/arm64/boot/dts/marvell/ |
| D | armada-ap810-ap0-octa-core.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include "armada-ap810-ap0.dtsi"
12 #address-cells = <1>;
13 #size-cells = <0>;
14 compatible = "marvell,armada-ap810-octa";
18 compatible = "arm,cortex-a72";
20 enable-method = "psci";
24 compatible = "arm,cortex-a72";
26 enable-method = "psci";
30 compatible = "arm,cortex-a72";
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| /Linux-v5.10/arch/arm/kernel/ |
| D | cpuidle.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
19 * arm_cpuidle_simple_enter() - a wrapper to cpu_do_idle()
38 * arm_cpuidle_suspend() - function to enter low power idle states
54 * arm_cpuidle_get_ops() - find a registered cpuidle_ops by name
55 * @method: the method name
58 * method name.
62 static const struct cpuidle_ops *__init arm_cpuidle_get_ops(const char *method) in arm_cpuidle_get_ops() argument
66 for (; m->method; m++) in arm_cpuidle_get_ops()
67 if (!strcmp(m->method, method)) in arm_cpuidle_get_ops()
68 return m->ops; in arm_cpuidle_get_ops()
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| /Linux-v5.10/arch/arm64/boot/dts/hisilicon/ |
| D | hip05.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "hisilicon,hip05-d02";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
18 method = "smc";
22 #address-cells = <1>;
23 #size-cells = <0>;
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| D | hip07.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "hisilicon,hip07-d05";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
18 method = "smc";
22 #address-cells = <1>;
23 #size-cells = <0>;
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| /Linux-v5.10/arch/arm64/boot/dts/mediatek/ |
| D | mt6755.dtsi | 14 #include <dt-bindings/interrupt-controller/irq.h>
15 #include <dt-bindings/interrupt-controller/arm-gic.h>
19 interrupt-parent = <&sysirq>;
20 #address-cells = <2>;
21 #size-cells = <2>;
24 compatible = "arm,psci-0.2";
25 method = "smc";
29 #address-cells = <1>;
30 #size-cells = <0>;
34 compatible = "arm,cortex-a53";
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| D | mt6795.dtsi | 14 #include <dt-bindings/interrupt-controller/irq.h>
15 #include <dt-bindings/interrupt-controller/arm-gic.h>
19 interrupt-parent = <&sysirq>;
20 #address-cells = <2>;
21 #size-cells = <2>;
24 compatible = "arm,psci-0.2";
25 method = "smc";
29 #address-cells = <1>;
30 #size-cells = <0>;
34 compatible = "arm,cortex-a53";
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| /Linux-v5.10/Documentation/devicetree/bindings/ |
| D | numa.txt | 6 1 - Introduction
18 2 - numa-node-id
23 a node id is a 32-bit integer.
26 numa-node-id property which contains the node id of the device.
30 numa-node-id = <0>;
33 numa-node-id = <1>;
36 3 - distance-map
39 The optional device tree node distance-map describes the relative
42 - compatible : Should at least contain "numa-distance-map-v1".
44 - distance-matrix
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| /Linux-v5.10/arch/arm64/kernel/ |
| D | cpu_ops.c | 1 // SPDX-License-Identifier: GPL-2.0-only
46 if (!strcmp(name, (*ops)->name)) in cpu_get_ops()
68 enable_method = of_get_property(dn, "enable-method", NULL); in cpu_read_enable_method()
71 * The boot CPU may not have an enable method (e.g. in cpu_read_enable_method()
72 * when spin-table is used for secondaries). in cpu_read_enable_method()
76 pr_err("%pOF: missing enable-method property\n", in cpu_read_enable_method()
85 * checking the enable method since for some in cpu_read_enable_method()
90 pr_err("Unsupported ACPI enable-method\n"); in cpu_read_enable_method()
97 * Read a cpu's enable method and record it in cpu_ops.
104 return -ENODEV; in init_cpu_ops()
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| /Linux-v5.10/arch/arm64/boot/dts/arm/ |
| D | foundation-v8-psci.dtsi | 9 compatible = "arm,psci-1.0";
10 method = "smc";
15 enable-method = "psci";
19 enable-method = "psci";
23 enable-method = "psci";
27 enable-method = "psci";
|
| D | foundation-v8-spin-table.dtsi | 8 enable-method = "spin-table";
9 cpu-release-addr = <0x0 0x8000fff8>;
13 enable-method = "spin-table";
14 cpu-release-addr = <0x0 0x8000fff8>;
18 enable-method = "spin-table";
19 cpu-release-addr = <0x0 0x8000fff8>;
23 enable-method = "spin-table";
24 cpu-release-addr = <0x0 0x8000fff8>;
|
| /Linux-v5.10/Documentation/devicetree/bindings/arm/cpu-enable-method/ |
| D | marvell,berlin-smp | 2 Secondary CPU enable-method "marvell,berlin-smp" binding
5 This document describes the "marvell,berlin-smp" method for enabling secondary
6 CPUs. To apply to all CPUs, a single "marvell,berlin-smp" enable method should
9 Enable method name: "marvell,berlin-smp"
11 Compatible CPUs: "marvell,pj4b" and "arm,cortex-a9"
15 This enable method needs valid nodes compatible with "arm,cortex-a9-scu" and
16 "marvell,berlin-cpu-ctrl"[1].
21 #address-cells = <1>;
22 #size-cells = <0>;
23 enable-method = "marvell,berlin-smp";
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| D | nuvoton,npcm750-smp | 2 Secondary CPU enable-method "nuvoton,npcm750-smp" binding
5 To apply to all CPUs, a single "nuvoton,npcm750-smp" enable method should be
8 Enable method name: "nuvoton,npcm750-smp"
10 Compatible CPUs: "arm,cortex-a9"
14 This enable method needs valid nodes compatible with "arm,cortex-a9-scu" and
15 "nuvoton,npcm750-gcr".
20 #address-cells = <1>;
21 #size-cells = <0>;
22 enable-method = "nuvoton,npcm750-smp";
26 compatible = "arm,cortex-a9";
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| D | al,alpine-smp | 2 Secondary CPU enable-method "al,alpine-smp" binding
5 This document describes the "al,alpine-smp" method for
7 "al,alpine-smp" enable method should be defined in the
10 Enable method name: "al,alpine-smp"
12 Compatible CPUs: "arm,cortex-a15"
16 This enable method requires valid nodes compatible with
17 "al,alpine-cpu-resume" and "al,alpine-nb-service".
26 - compatible : Should contain "al,alpine-cpu-resume".
27 - reg : Offset and length of the register set for the device
30 * Alpine System-Fabric Service Registers
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|
| /Linux-v5.10/Documentation/PCI/ |
| D | pci-iov-howto.rst | 1 .. SPDX-License-Identifier: GPL-2.0
9 :Authors: - Yu Zhao <yu.zhao@intel.com>
10 - Donald Dutile <ddutile@redhat.com>
15 What is SR-IOV
16 --------------
18 Single Root I/O Virtualization (SR-IOV) is a PCI Express Extended
34 How can I enable SR-IOV capability
35 ----------------------------------
37 Multiple methods are available for SR-IOV enablement.
38 In the first method, the device driver (PF driver) will control the
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|
| /Linux-v5.10/arch/arm64/boot/dts/amazon/ |
| D | alpine-v3.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 compatible = "amazon,al-alpine-v3";
14 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
20 #address-cells = <1>;
21 #size-cells = <0>;
25 compatible = "arm,cortex-a72";
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|
| /Linux-v5.10/Documentation/devicetree/bindings/cpufreq/ |
| D | cpufreq-qcom-hw.txt | 8 - compatible
11 Definition: must be "qcom,cpufreq-hw" or "qcom,cpufreq-epss".
13 - clocks
18 - clock-names
23 - reg
25 Value type: <prop-encoded-array>
28 - reg-names
32 "freq-domain0", "freq-domain1".
34 - #freq-domain-cells:
38 * Property qcom,freq-domain
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|
| /Linux-v5.10/arch/sh/boards/ |
| D | of-generic.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2015-2016 Smart Energy Instruments, Inc.
12 #include <linux/clk-provider.h>
57 const char *method = NULL; in sh_of_smp_probe() local
66 u64 id = -1; in sh_of_smp_probe()
69 if (!method) in sh_of_smp_probe()
70 of_property_read_string(np, "enable-method", &method); in sh_of_smp_probe()
77 if (!method) { in sh_of_smp_probe()
79 of_property_read_string(np, "enable-method", &method); in sh_of_smp_probe()
83 pr_info("CPU enable method: %s\n", method); in sh_of_smp_probe()
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|
| /Linux-v5.10/arch/arm64/boot/dts/nvidia/ |
| D | tegra210-p2530.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
14 stdout-path = "serial0:115200n8";
29 clock-frequency = <400000>;
33 nvidia,invert-interrupt;
39 bus-width = <8>;
40 non-removable;
44 compatible = "fixed-clock";
45 clock-frequency = <32768>;
46 #clock-cells = <0>;
51 enable-method = "psci";
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| /Linux-v5.10/arch/arm64/boot/dts/amlogic/ |
| D | meson-g12b.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include "meson-g12.dtsi"
13 #address-cells = <0x2>;
14 #size-cells = <0x0>;
16 cpu-map {
48 compatible = "arm,cortex-a53";
50 enable-method = "psci";
51 capacity-dmips-mhz = <592>;
52 next-level-cache = <&l2>;
53 #cooling-cells = <2>;
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| /Linux-v5.10/Documentation/devicetree/bindings/cpu/ |
| D | cpu-topology.txt | 6 1 - Introduction
12 - socket
13 - cluster
14 - core
15 - thread
18 symmetric multi-threading (SMT) is supported or not.
29 Currently, only ARM/RISC-V intend to use this cpu topology binding but it may be
39 2 - cpu-map node
42 The ARM/RISC-V CPU topology is defined within the cpu-map node, which is a direct
46 - cpu-map node
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| /Linux-v5.10/arch/arm/boot/dts/ |
| D | bcm2837.dtsi | 2 #include "bcm2835-common.dtsi"
3 #include "bcm2835-rpi-common.dtsi"
11 dma-ranges = <0xc0000000 0x00000000 0x3f000000>;
14 compatible = "brcm,bcm2836-l1-intc";
16 interrupt-controller;
17 #interrupt-cells = <2>;
18 interrupt-parent = <&local_intc>;
22 arm-pmu {
23 compatible = "arm,cortex-a53-pmu";
24 interrupt-parent = <&local_intc>;
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