Lines Matching +full:enable +full:- +full:method
1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "hisilicon,hip05-d02";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
18 method = "smc";
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
86 compatible = "arm,cortex-a57";
88 enable-method = "psci";
89 next-level-cache = <&cluster0_l2>;
94 compatible = "arm,cortex-a57";
96 enable-method = "psci";
97 next-level-cache = <&cluster0_l2>;
102 compatible = "arm,cortex-a57";
104 enable-method = "psci";
105 next-level-cache = <&cluster0_l2>;
110 compatible = "arm,cortex-a57";
112 enable-method = "psci";
113 next-level-cache = <&cluster0_l2>;
118 compatible = "arm,cortex-a57";
120 enable-method = "psci";
121 next-level-cache = <&cluster1_l2>;
126 compatible = "arm,cortex-a57";
128 enable-method = "psci";
129 next-level-cache = <&cluster1_l2>;
134 compatible = "arm,cortex-a57";
136 enable-method = "psci";
137 next-level-cache = <&cluster1_l2>;
142 compatible = "arm,cortex-a57";
144 enable-method = "psci";
145 next-level-cache = <&cluster1_l2>;
150 compatible = "arm,cortex-a57";
152 enable-method = "psci";
153 next-level-cache = <&cluster2_l2>;
158 compatible = "arm,cortex-a57";
160 enable-method = "psci";
161 next-level-cache = <&cluster2_l2>;
166 compatible = "arm,cortex-a57";
168 enable-method = "psci";
169 next-level-cache = <&cluster2_l2>;
174 compatible = "arm,cortex-a57";
176 enable-method = "psci";
177 next-level-cache = <&cluster2_l2>;
182 compatible = "arm,cortex-a57";
184 enable-method = "psci";
185 next-level-cache = <&cluster3_l2>;
190 compatible = "arm,cortex-a57";
192 enable-method = "psci";
193 next-level-cache = <&cluster3_l2>;
198 compatible = "arm,cortex-a57";
200 enable-method = "psci";
201 next-level-cache = <&cluster3_l2>;
206 compatible = "arm,cortex-a57";
208 enable-method = "psci";
209 next-level-cache = <&cluster3_l2>;
212 cluster0_l2: l2-cache0 {
216 cluster1_l2: l2-cache1 {
220 cluster2_l2: l2-cache2 {
224 cluster3_l2: l2-cache3 {
229 gic: interrupt-controller@8d000000 {
230 compatible = "arm,gic-v3";
231 #interrupt-cells = <3>;
232 #address-cells = <2>;
233 #size-cells = <2>;
235 interrupt-controller;
236 #redistributor-regions = <1>;
237 redistributor-stride = <0x0 0x30000>;
245 its_peri: interrupt-controller@8c000000 {
246 compatible = "arm,gic-v3-its";
247 msi-controller;
248 #msi-cells = <1>;
252 its_m3: interrupt-controller@a3000000 {
253 compatible = "arm,gic-v3-its";
254 msi-controller;
255 #msi-cells = <1>;
259 its_pcie: interrupt-controller@b7000000 {
260 compatible = "arm,gic-v3-its";
261 msi-controller;
262 #msi-cells = <1>;
266 its_dsa: interrupt-controller@c6000000 {
267 compatible = "arm,gic-v3-its";
268 msi-controller;
269 #msi-cells = <1>;
275 compatible = "arm,armv8-timer";
283 compatible = "arm,cortex-a57-pmu";
288 compatible = "simple-bus";
289 #address-cells = <2>;
290 #size-cells = <2>;
294 compatible = "fixed-clock";
295 #clock-cells = <0>;
296 clock-frequency = <200000000>;
300 compatible = "snps,dw-apb-uart";
304 clock-names = "apb_pclk";
305 reg-shift = <2>;
306 reg-io-width = <4>;
311 compatible = "snps,dw-apb-uart";
315 clock-names = "apb_pclk";
316 reg-shift = <2>;
317 reg-io-width = <4>;
322 compatible = "hisilicon,hisi-localbus", "simple-bus";
328 #address-cells = <1>;
329 #size-cells = <0>;
330 compatible = "snps,dw-apb-gpio";
334 porta: gpio-controller@0 {
335 compatible = "snps,dw-apb-gpio-port";
336 gpio-controller;
337 #gpio-cells = <2>;
338 snps,nr-gpios = <32>;
340 interrupt-controller;
341 #interrupt-cells = <2>;
347 #address-cells = <1>;
348 #size-cells = <0>;
349 compatible = "snps,dw-apb-gpio";
353 portb: gpio-controller@0 {
354 compatible = "snps,dw-apb-gpio-port";
355 gpio-controller;
356 #gpio-cells = <2>;
357 snps,nr-gpios = <32>;
359 interrupt-controller;
360 #interrupt-cells = <2>;