Lines Matching +full:enable +full:- +full:method
1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "hisilicon,hip07-d05";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
18 method = "smc";
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
269 compatible = "arm,cortex-a72";
271 enable-method = "psci";
272 next-level-cache = <&cluster0_l2>;
273 numa-node-id = <0>;
278 compatible = "arm,cortex-a72";
280 enable-method = "psci";
281 next-level-cache = <&cluster0_l2>;
282 numa-node-id = <0>;
287 compatible = "arm,cortex-a72";
289 enable-method = "psci";
290 next-level-cache = <&cluster0_l2>;
291 numa-node-id = <0>;
296 compatible = "arm,cortex-a72";
298 enable-method = "psci";
299 next-level-cache = <&cluster0_l2>;
300 numa-node-id = <0>;
305 compatible = "arm,cortex-a72";
307 enable-method = "psci";
308 next-level-cache = <&cluster1_l2>;
309 numa-node-id = <0>;
314 compatible = "arm,cortex-a72";
316 enable-method = "psci";
317 next-level-cache = <&cluster1_l2>;
318 numa-node-id = <0>;
323 compatible = "arm,cortex-a72";
325 enable-method = "psci";
326 next-level-cache = <&cluster1_l2>;
327 numa-node-id = <0>;
332 compatible = "arm,cortex-a72";
334 enable-method = "psci";
335 next-level-cache = <&cluster1_l2>;
336 numa-node-id = <0>;
341 compatible = "arm,cortex-a72";
343 enable-method = "psci";
344 next-level-cache = <&cluster2_l2>;
345 numa-node-id = <0>;
350 compatible = "arm,cortex-a72";
352 enable-method = "psci";
353 next-level-cache = <&cluster2_l2>;
354 numa-node-id = <0>;
359 compatible = "arm,cortex-a72";
361 enable-method = "psci";
362 next-level-cache = <&cluster2_l2>;
363 numa-node-id = <0>;
368 compatible = "arm,cortex-a72";
370 enable-method = "psci";
371 next-level-cache = <&cluster2_l2>;
372 numa-node-id = <0>;
377 compatible = "arm,cortex-a72";
379 enable-method = "psci";
380 next-level-cache = <&cluster3_l2>;
381 numa-node-id = <0>;
386 compatible = "arm,cortex-a72";
388 enable-method = "psci";
389 next-level-cache = <&cluster3_l2>;
390 numa-node-id = <0>;
395 compatible = "arm,cortex-a72";
397 enable-method = "psci";
398 next-level-cache = <&cluster3_l2>;
399 numa-node-id = <0>;
404 compatible = "arm,cortex-a72";
406 enable-method = "psci";
407 next-level-cache = <&cluster3_l2>;
408 numa-node-id = <0>;
413 compatible = "arm,cortex-a72";
415 enable-method = "psci";
416 next-level-cache = <&cluster4_l2>;
417 numa-node-id = <1>;
422 compatible = "arm,cortex-a72";
424 enable-method = "psci";
425 next-level-cache = <&cluster4_l2>;
426 numa-node-id = <1>;
431 compatible = "arm,cortex-a72";
433 enable-method = "psci";
434 next-level-cache = <&cluster4_l2>;
435 numa-node-id = <1>;
440 compatible = "arm,cortex-a72";
442 enable-method = "psci";
443 next-level-cache = <&cluster4_l2>;
444 numa-node-id = <1>;
449 compatible = "arm,cortex-a72";
451 enable-method = "psci";
452 next-level-cache = <&cluster5_l2>;
453 numa-node-id = <1>;
458 compatible = "arm,cortex-a72";
460 enable-method = "psci";
461 next-level-cache = <&cluster5_l2>;
462 numa-node-id = <1>;
467 compatible = "arm,cortex-a72";
469 enable-method = "psci";
470 next-level-cache = <&cluster5_l2>;
471 numa-node-id = <1>;
476 compatible = "arm,cortex-a72";
478 enable-method = "psci";
479 next-level-cache = <&cluster5_l2>;
480 numa-node-id = <1>;
485 compatible = "arm,cortex-a72";
487 enable-method = "psci";
488 next-level-cache = <&cluster6_l2>;
489 numa-node-id = <1>;
494 compatible = "arm,cortex-a72";
496 enable-method = "psci";
497 next-level-cache = <&cluster6_l2>;
498 numa-node-id = <1>;
503 compatible = "arm,cortex-a72";
505 enable-method = "psci";
506 next-level-cache = <&cluster6_l2>;
507 numa-node-id = <1>;
512 compatible = "arm,cortex-a72";
514 enable-method = "psci";
515 next-level-cache = <&cluster6_l2>;
516 numa-node-id = <1>;
521 compatible = "arm,cortex-a72";
523 enable-method = "psci";
524 next-level-cache = <&cluster7_l2>;
525 numa-node-id = <1>;
530 compatible = "arm,cortex-a72";
532 enable-method = "psci";
533 next-level-cache = <&cluster7_l2>;
534 numa-node-id = <1>;
539 compatible = "arm,cortex-a72";
541 enable-method = "psci";
542 next-level-cache = <&cluster7_l2>;
543 numa-node-id = <1>;
548 compatible = "arm,cortex-a72";
550 enable-method = "psci";
551 next-level-cache = <&cluster7_l2>;
552 numa-node-id = <1>;
557 compatible = "arm,cortex-a72";
559 enable-method = "psci";
560 next-level-cache = <&cluster8_l2>;
561 numa-node-id = <2>;
566 compatible = "arm,cortex-a72";
568 enable-method = "psci";
569 next-level-cache = <&cluster8_l2>;
570 numa-node-id = <2>;
575 compatible = "arm,cortex-a72";
577 enable-method = "psci";
578 next-level-cache = <&cluster8_l2>;
579 numa-node-id = <2>;
584 compatible = "arm,cortex-a72";
586 enable-method = "psci";
587 next-level-cache = <&cluster8_l2>;
588 numa-node-id = <2>;
593 compatible = "arm,cortex-a72";
595 enable-method = "psci";
596 next-level-cache = <&cluster9_l2>;
597 numa-node-id = <2>;
602 compatible = "arm,cortex-a72";
604 enable-method = "psci";
605 next-level-cache = <&cluster9_l2>;
606 numa-node-id = <2>;
611 compatible = "arm,cortex-a72";
613 enable-method = "psci";
614 next-level-cache = <&cluster9_l2>;
615 numa-node-id = <2>;
620 compatible = "arm,cortex-a72";
622 enable-method = "psci";
623 next-level-cache = <&cluster9_l2>;
624 numa-node-id = <2>;
629 compatible = "arm,cortex-a72";
631 enable-method = "psci";
632 next-level-cache = <&cluster10_l2>;
633 numa-node-id = <2>;
638 compatible = "arm,cortex-a72";
640 enable-method = "psci";
641 next-level-cache = <&cluster10_l2>;
642 numa-node-id = <2>;
647 compatible = "arm,cortex-a72";
649 enable-method = "psci";
650 next-level-cache = <&cluster10_l2>;
651 numa-node-id = <2>;
656 compatible = "arm,cortex-a72";
658 enable-method = "psci";
659 next-level-cache = <&cluster10_l2>;
660 numa-node-id = <2>;
665 compatible = "arm,cortex-a72";
667 enable-method = "psci";
668 next-level-cache = <&cluster11_l2>;
669 numa-node-id = <2>;
674 compatible = "arm,cortex-a72";
676 enable-method = "psci";
677 next-level-cache = <&cluster11_l2>;
678 numa-node-id = <2>;
683 compatible = "arm,cortex-a72";
685 enable-method = "psci";
686 next-level-cache = <&cluster11_l2>;
687 numa-node-id = <2>;
692 compatible = "arm,cortex-a72";
694 enable-method = "psci";
695 next-level-cache = <&cluster11_l2>;
696 numa-node-id = <2>;
701 compatible = "arm,cortex-a72";
703 enable-method = "psci";
704 next-level-cache = <&cluster12_l2>;
705 numa-node-id = <3>;
710 compatible = "arm,cortex-a72";
712 enable-method = "psci";
713 next-level-cache = <&cluster12_l2>;
714 numa-node-id = <3>;
719 compatible = "arm,cortex-a72";
721 enable-method = "psci";
722 next-level-cache = <&cluster12_l2>;
723 numa-node-id = <3>;
728 compatible = "arm,cortex-a72";
730 enable-method = "psci";
731 next-level-cache = <&cluster12_l2>;
732 numa-node-id = <3>;
737 compatible = "arm,cortex-a72";
739 enable-method = "psci";
740 next-level-cache = <&cluster13_l2>;
741 numa-node-id = <3>;
746 compatible = "arm,cortex-a72";
748 enable-method = "psci";
749 next-level-cache = <&cluster13_l2>;
750 numa-node-id = <3>;
755 compatible = "arm,cortex-a72";
757 enable-method = "psci";
758 next-level-cache = <&cluster13_l2>;
759 numa-node-id = <3>;
764 compatible = "arm,cortex-a72";
766 enable-method = "psci";
767 next-level-cache = <&cluster13_l2>;
768 numa-node-id = <3>;
773 compatible = "arm,cortex-a72";
775 enable-method = "psci";
776 next-level-cache = <&cluster14_l2>;
777 numa-node-id = <3>;
782 compatible = "arm,cortex-a72";
784 enable-method = "psci";
785 next-level-cache = <&cluster14_l2>;
786 numa-node-id = <3>;
791 compatible = "arm,cortex-a72";
793 enable-method = "psci";
794 next-level-cache = <&cluster14_l2>;
795 numa-node-id = <3>;
800 compatible = "arm,cortex-a72";
802 enable-method = "psci";
803 next-level-cache = <&cluster14_l2>;
804 numa-node-id = <3>;
809 compatible = "arm,cortex-a72";
811 enable-method = "psci";
812 next-level-cache = <&cluster15_l2>;
813 numa-node-id = <3>;
818 compatible = "arm,cortex-a72";
820 enable-method = "psci";
821 next-level-cache = <&cluster15_l2>;
822 numa-node-id = <3>;
827 compatible = "arm,cortex-a72";
829 enable-method = "psci";
830 next-level-cache = <&cluster15_l2>;
831 numa-node-id = <3>;
836 compatible = "arm,cortex-a72";
838 enable-method = "psci";
839 next-level-cache = <&cluster15_l2>;
840 numa-node-id = <3>;
843 cluster0_l2: l2-cache0 {
847 cluster1_l2: l2-cache1 {
851 cluster2_l2: l2-cache2 {
855 cluster3_l2: l2-cache3 {
859 cluster4_l2: l2-cache4 {
863 cluster5_l2: l2-cache5 {
867 cluster6_l2: l2-cache6 {
871 cluster7_l2: l2-cache7 {
875 cluster8_l2: l2-cache8 {
879 cluster9_l2: l2-cache9 {
883 cluster10_l2: l2-cache10 {
887 cluster11_l2: l2-cache11 {
891 cluster12_l2: l2-cache12 {
895 cluster13_l2: l2-cache13 {
899 cluster14_l2: l2-cache14 {
903 cluster15_l2: l2-cache15 {
908 gic: interrupt-controller@4d000000 {
909 compatible = "arm,gic-v3";
910 #interrupt-cells = <3>;
911 #address-cells = <2>;
912 #size-cells = <2>;
914 interrupt-controller;
915 #redistributor-regions = <4>;
916 redistributor-stride = <0x0 0x40000>;
927 p0_its_peri_a: interrupt-controller@4c000000 {
928 compatible = "arm,gic-v3-its";
929 msi-controller;
930 #msi-cells = <1>;
934 p0_its_peri_b: interrupt-controller@6c000000 {
935 compatible = "arm,gic-v3-its";
936 msi-controller;
937 #msi-cells = <1>;
941 p0_its_dsa_a: interrupt-controller@c6000000 {
942 compatible = "arm,gic-v3-its";
943 msi-controller;
944 #msi-cells = <1>;
948 p0_its_dsa_b: interrupt-controller@8,c6000000 {
949 compatible = "arm,gic-v3-its";
950 msi-controller;
951 #msi-cells = <1>;
955 p1_its_peri_a: interrupt-controller@400,4c000000 {
956 compatible = "arm,gic-v3-its";
957 msi-controller;
958 #msi-cells = <1>;
962 p1_its_peri_b: interrupt-controller@400,6c000000 {
963 compatible = "arm,gic-v3-its";
964 msi-controller;
965 #msi-cells = <1>;
969 p1_its_dsa_a: interrupt-controller@400,c6000000 {
970 compatible = "arm,gic-v3-its";
971 msi-controller;
972 #msi-cells = <1>;
976 p1_its_dsa_b: interrupt-controller@408,c6000000 {
977 compatible = "arm,gic-v3-its";
978 msi-controller;
979 #msi-cells = <1>;
985 compatible = "arm,armv8-timer";
993 compatible = "arm,cortex-a72-pmu";
997 p0_mbigen_peri_b: interrupt-controller@60080000 {
998 compatible = "hisilicon,mbigen-v2";
1002 msi-parent = <&p0_its_peri_b 0x120c7>;
1003 interrupt-controller;
1004 #interrupt-cells = <2>;
1005 num-pins = <1>;
1009 p0_mbigen_pcie_a: interrupt-controller@a0080000 {
1010 compatible = "hisilicon,mbigen-v2";
1014 msi-parent = <&p0_its_dsa_a 0x40087>;
1015 interrupt-controller;
1016 #interrupt-cells = <2>;
1017 num-pins = <10>;
1021 msi-parent = <&p0_its_dsa_a 0x40000>;
1022 interrupt-controller;
1023 #interrupt-cells = <2>;
1024 num-pins = <128>;
1028 msi-parent = <&p0_its_dsa_a 0x40040>;
1029 interrupt-controller;
1030 #interrupt-cells = <2>;
1031 num-pins = <128>;
1035 msi-parent = <&p0_its_dsa_a 0x40b0c>;
1036 interrupt-controller;
1037 #interrupt-cells = <2>;
1038 num-pins = <3>;
1042 msi-parent = <&p0_its_dsa_a 0x40080>;
1043 interrupt-controller;
1044 #interrupt-cells = <2>;
1045 num-pins = <2>;
1048 p0_mbigen_alg_a:interrupt-controller@d0080000 {
1049 compatible = "hisilicon,mbigen-v2";
1053 msi-parent = <&p0_its_dsa_a 0x40400>;
1054 interrupt-controller;
1055 #interrupt-cells = <2>;
1056 num-pins = <33>;
1059 msi-parent = <&p0_its_dsa_a 0x40b1b>;
1060 interrupt-controller;
1061 #interrupt-cells = <2>;
1062 num-pins = <3>;
1065 p0_mbigen_alg_b:interrupt-controller@8,d0080000 {
1066 compatible = "hisilicon,mbigen-v2";
1070 msi-parent = <&p0_its_dsa_b 0x42400>;
1071 interrupt-controller;
1072 #interrupt-cells = <2>;
1073 num-pins = <33>;
1076 msi-parent = <&p0_its_dsa_b 0x42b1b>;
1077 interrupt-controller;
1078 #interrupt-cells = <2>;
1079 num-pins = <3>;
1082 p1_mbigen_alg_a:interrupt-controller@400,d0080000 {
1083 compatible = "hisilicon,mbigen-v2";
1087 msi-parent = <&p1_its_dsa_a 0x44400>;
1088 interrupt-controller;
1089 #interrupt-cells = <2>;
1090 num-pins = <33>;
1093 msi-parent = <&p1_its_dsa_a 0x44b1b>;
1094 interrupt-controller;
1095 #interrupt-cells = <2>;
1096 num-pins = <3>;
1099 p1_mbigen_alg_b:interrupt-controller@408,d0080000 {
1100 compatible = "hisilicon,mbigen-v2";
1104 msi-parent = <&p1_its_dsa_b 0x46400>;
1105 interrupt-controller;
1106 #interrupt-cells = <2>;
1107 num-pins = <33>;
1110 msi-parent = <&p1_its_dsa_b 0x46b1b>;
1111 interrupt-controller;
1112 #interrupt-cells = <2>;
1113 num-pins = <3>;
1116 p0_mbigen_dsa_a: interrupt-controller@c0080000 {
1117 compatible = "hisilicon,mbigen-v2";
1121 msi-parent = <&p0_its_dsa_a 0x40800>;
1122 interrupt-controller;
1123 #interrupt-cells = <2>;
1124 num-pins = <409>;
1127 mbigen_dsa_roce: intc-roce {
1128 msi-parent = <&p0_its_dsa_a 0x40B1E>;
1129 interrupt-controller;
1130 #interrupt-cells = <2>;
1131 num-pins = <34>;
1134 mbigen_sas0: intc-sas0 {
1135 msi-parent = <&p0_its_dsa_a 0x40900>;
1136 interrupt-controller;
1137 #interrupt-cells = <2>;
1138 num-pins = <128>;
1142 msi-parent = <&p0_its_dsa_a 0x40b20>;
1143 interrupt-controller;
1144 #interrupt-cells = <2>;
1145 num-pins = <3>;
1161 * when iommu-map entry is used along with the PCIe node.
1162 * Refer:https://www.spinics.net/lists/arm-kernel/msg602812.html
1165 compatible = "arm,smmu-v3";
1167 #iommu-cells = <1>;
1168 dma-coherent;
1169 smmu-cb-memtype = <0x0 0x1>;
1170 hisilicon,broken-prefetch-cmd;
1174 compatible = "arm,smmu-v3";
1176 interrupt-parent = <&p0_mbigen_smmu_alg_a>;
1180 interrupt-names = "eventq", "gerror", "priq";
1181 #iommu-cells = <1>;
1182 dma-coherent;
1183 hisilicon,broken-prefetch-cmd;
1184 /* smmu-cb-memtype = <0x0 0x1>;*/
1187 compatible = "arm,smmu-v3";
1189 interrupt-parent = <&p0_mbigen_smmu_alg_b>;
1193 interrupt-names = "eventq", "gerror", "priq";
1194 #iommu-cells = <1>;
1195 dma-coherent;
1196 hisilicon,broken-prefetch-cmd;
1197 /* smmu-cb-memtype = <0x0 0x1>;*/
1200 compatible = "arm,smmu-v3";
1202 interrupt-parent = <&p1_mbigen_smmu_alg_a>;
1206 interrupt-names = "eventq", "gerror", "priq";
1207 #iommu-cells = <1>;
1208 dma-coherent;
1209 hisilicon,broken-prefetch-cmd;
1210 /* smmu-cb-memtype = <0x0 0x1>;*/
1213 compatible = "arm,smmu-v3";
1215 interrupt-parent = <&p1_mbigen_smmu_alg_b>;
1219 interrupt-names = "eventq", "gerror", "priq";
1220 #iommu-cells = <1>;
1221 dma-coherent;
1222 hisilicon,broken-prefetch-cmd;
1223 /* smmu-cb-memtype = <0x0 0x1>;*/
1227 compatible = "simple-bus";
1228 #address-cells = <2>;
1229 #size-cells = <2>;
1233 compatible = "hisilicon,hip07-lpc";
1234 #size-cells = <1>;
1235 #address-cells = <2>;
1239 compatible = "ipmi-bt";
1247 compatible = "arm,sbsa-uart";
1249 interrupt-parent = <&mbigen_uart>;
1251 current-speed = <115200>;
1252 reg-io-width = <4>;
1257 compatible = "generic-ohci";
1259 interrupt-parent = <&mbigen_usb>;
1261 dma-coherent;
1266 compatible = "generic-ehci";
1268 interrupt-parent = <&mbigen_usb>;
1270 dma-coherent;
1275 compatible = "hisilicon,peri-subctrl","syscon";
1280 compatible = "hisilicon,dsa-subctrl", "syscon";
1287 reg-io-width = <2>;
1291 compatible = "hisilicon,pcie-sas-subctrl", "syscon";
1301 compatible = "hisilicon,hns-mdio";
1303 subctrl-vbase = <&peri_c_subctrl 0x338 0xa38
1305 #address-cells = <1>;
1306 #size-cells = <0>;
1308 phy0: ethernet-phy@0 {
1309 compatible = "ethernet-phy-ieee802.3-c22";
1313 phy1: ethernet-phy@1 {
1314 compatible = "ethernet-phy-ieee802.3-c22";
1320 #address-cells = <1>;
1321 #size-cells = <0>;
1322 compatible = "hisilicon,hns-dsaf-v2";
1323 mode = "6port-16rss";
1326 reg-names = "ppe-base", "dsaf-base";
1327 interrupt-parent = <&mbigen_dsaf0>;
1328 subctrl-syscon = <&dsa_subctrl>;
1329 reset-field-offset = <0>;
1414 desc-num = <0x400>;
1415 buf-size = <0x1000>;
1416 dma-coherent;
1420 serdes-syscon = <&serdes_ctrl>;
1421 cpld-syscon = <&dsa_cpld 0x0>;
1422 port-rst-offset = <0>;
1423 port-mode-offset = <0>;
1424 mc-mac-mask = [ff f0 00 00 00 00];
1425 media-type = "fiber";
1430 serdes-syscon= <&serdes_ctrl>;
1431 cpld-syscon = <&dsa_cpld 0x4>;
1432 port-rst-offset = <1>;
1433 port-mode-offset = <1>;
1434 mc-mac-mask = [ff f0 00 00 00 00];
1435 media-type = "fiber";
1440 phy-handle = <&phy0>;
1441 serdes-syscon= <&serdes_ctrl>;
1442 port-rst-offset = <4>;
1443 port-mode-offset = <2>;
1444 mc-mac-mask = [ff f0 00 00 00 00];
1445 media-type = "copper";
1450 phy-handle = <&phy1>;
1451 serdes-syscon= <&serdes_ctrl>;
1452 port-rst-offset = <5>;
1453 port-mode-offset = <3>;
1454 mc-mac-mask = [ff f0 00 00 00 00];
1455 media-type = "copper";
1460 compatible = "hisilicon,hns-nic-v2";
1461 ae-handle = <&dsaf0>;
1462 port-idx-in-ae = <4>;
1463 local-mac-address = [00 00 00 00 00 00];
1465 dma-coherent;
1469 compatible = "hisilicon,hns-nic-v2";
1470 ae-handle = <&dsaf0>;
1471 port-idx-in-ae = <5>;
1472 local-mac-address = [00 00 00 00 00 00];
1474 dma-coherent;
1478 compatible = "hisilicon,hns-nic-v2";
1479 ae-handle = <&dsaf0>;
1480 port-idx-in-ae = <0>;
1481 local-mac-address = [00 00 00 00 00 00];
1483 dma-coherent;
1487 compatible = "hisilicon,hns-nic-v2";
1488 ae-handle = <&dsaf0>;
1489 port-idx-in-ae = <1>;
1490 local-mac-address = [00 00 00 00 00 00];
1492 dma-coherent;
1496 compatible = "hisilicon,hns-roce-v1";
1498 dma-coherent;
1499 eth-handle = <ð2 ð3 0 0 ð0 ð1>;
1500 dsaf-handle = <&dsaf0>;
1501 node-guid = [00 9A CD 00 00 01 02 03];
1502 #address-cells = <2>;
1503 #size-cells = <2>;
1504 interrupt-parent = <&mbigen_dsa_roce>;
1540 interrupt-names = "hns-roce-comp-0",
1541 "hns-roce-comp-1",
1542 "hns-roce-comp-2",
1543 "hns-roce-comp-3",
1544 "hns-roce-comp-4",
1545 "hns-roce-comp-5",
1546 "hns-roce-comp-6",
1547 "hns-roce-comp-7",
1548 "hns-roce-comp-8",
1549 "hns-roce-comp-9",
1550 "hns-roce-comp-10",
1551 "hns-roce-comp-11",
1552 "hns-roce-comp-12",
1553 "hns-roce-comp-13",
1554 "hns-roce-comp-14",
1555 "hns-roce-comp-15",
1556 "hns-roce-comp-16",
1557 "hns-roce-comp-17",
1558 "hns-roce-comp-18",
1559 "hns-roce-comp-19",
1560 "hns-roce-comp-20",
1561 "hns-roce-comp-21",
1562 "hns-roce-comp-22",
1563 "hns-roce-comp-23",
1564 "hns-roce-comp-24",
1565 "hns-roce-comp-25",
1566 "hns-roce-comp-26",
1567 "hns-roce-comp-27",
1568 "hns-roce-comp-28",
1569 "hns-roce-comp-29",
1570 "hns-roce-comp-30",
1571 "hns-roce-comp-31",
1572 "hns-roce-async",
1573 "hns-roce-common";
1577 compatible = "hisilicon,hip07-sas-v2";
1579 sas-addr = [50 01 88 20 16 00 00 00];
1580 hisilicon,sas-syscon = <&dsa_subctrl>;
1581 ctrl-reset-reg = <0xa60>;
1582 ctrl-reset-sts-reg = <0x5a30>;
1583 ctrl-clock-ena-reg = <0x338>;
1584 queue-count = <16>;
1585 phy-count = <8>;
1586 dma-coherent;
1587 interrupt-parent = <&mbigen_sas0>;
1618 compatible = "hisilicon,hip07-sas-v2";
1620 sas-addr = [50 01 88 20 16 00 00 00];
1621 hisilicon,sas-syscon = <&pcie_subctl>;
1622 hip06-sas-v2-quirk-amt;
1623 ctrl-reset-reg = <0xa18>;
1624 ctrl-reset-sts-reg = <0x5a0c>;
1625 ctrl-clock-ena-reg = <0x318>;
1626 queue-count = <16>;
1627 phy-count = <8>;
1628 dma-coherent;
1629 interrupt-parent = <&mbigen_sas1>;
1660 compatible = "hisilicon,hip07-sas-v2";
1662 sas-addr = [50 01 88 20 16 00 00 00];
1663 hisilicon,sas-syscon = <&pcie_subctl>;
1664 ctrl-reset-reg = <0xae0>;
1665 ctrl-reset-sts-reg = <0x5a70>;
1666 ctrl-clock-ena-reg = <0x3a8>;
1667 queue-count = <16>;
1668 phy-count = <9>;
1669 dma-coherent;
1670 interrupt-parent = <&mbigen_sas2>;
1701 compatible = "hisilicon,hip07-pcie-ecam";
1704 bus-range = <0xf8 0xff>;
1705 msi-map = <0xf800 &p0_its_dsa_a 0xf800 0x800>;
1706 msi-map-mask = <0xffff>;
1707 #address-cells = <3>;
1708 #size-cells = <2>;
1710 dma-coherent;
1713 #interrupt-cells = <1>;
1714 interrupt-map-mask = <0xf800 0 0 7>;
1715 interrupt-map = <0x0 0 0 1 &mbigen_pcie2_a 671 4
1722 compatible = "hisilicon,hip07-sec";
1741 interrupt-parent = <&p0_mbigen_sec_a>;
1743 dma-coherent;
1763 compatible = "hisilicon,hip07-sec";
1782 interrupt-parent = <&p0_mbigen_sec_b>;
1784 dma-coherent;
1804 compatible = "hisilicon,hip07-sec";
1823 interrupt-parent = <&p1_mbigen_sec_a>;
1825 dma-coherent;
1845 compatible = "hisilicon,hip07-sec";
1864 interrupt-parent = <&p1_mbigen_sec_b>;
1866 dma-coherent;