Lines Matching +full:enable +full:- +full:method
1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 compatible = "amazon,al-alpine-v3";
14 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
20 #address-cells = <1>;
21 #size-cells = <0>;
25 compatible = "arm,cortex-a72";
27 enable-method = "psci";
28 d-cache-size = <0x8000>;
29 d-cache-line-size = <64>;
30 d-cache-sets = <256>;
31 i-cache-size = <0xc000>;
32 i-cache-line-size = <64>;
33 i-cache-sets = <256>;
34 next-level-cache = <&cluster0_l2>;
39 compatible = "arm,cortex-a72";
41 enable-method = "psci";
42 d-cache-size = <0x8000>;
43 d-cache-line-size = <64>;
44 d-cache-sets = <256>;
45 i-cache-size = <0xc000>;
46 i-cache-line-size = <64>;
47 i-cache-sets = <256>;
48 next-level-cache = <&cluster0_l2>;
53 compatible = "arm,cortex-a72";
55 enable-method = "psci";
56 d-cache-size = <0x8000>;
57 d-cache-line-size = <64>;
58 d-cache-sets = <256>;
59 i-cache-size = <0xc000>;
60 i-cache-line-size = <64>;
61 i-cache-sets = <256>;
62 next-level-cache = <&cluster0_l2>;
67 compatible = "arm,cortex-a72";
69 enable-method = "psci";
70 d-cache-size = <0x8000>;
71 d-cache-line-size = <64>;
72 d-cache-sets = <256>;
73 i-cache-size = <0xc000>;
74 i-cache-line-size = <64>;
75 i-cache-sets = <256>;
76 next-level-cache = <&cluster0_l2>;
81 compatible = "arm,cortex-a72";
83 enable-method = "psci";
84 d-cache-size = <0x8000>;
85 d-cache-line-size = <64>;
86 d-cache-sets = <256>;
87 i-cache-size = <0xc000>;
88 i-cache-line-size = <64>;
89 i-cache-sets = <256>;
90 next-level-cache = <&cluster1_l2>;
95 compatible = "arm,cortex-a72";
97 enable-method = "psci";
98 d-cache-size = <0x8000>;
99 d-cache-line-size = <64>;
100 d-cache-sets = <256>;
101 i-cache-size = <0xc000>;
102 i-cache-line-size = <64>;
103 i-cache-sets = <256>;
104 next-level-cache = <&cluster1_l2>;
109 compatible = "arm,cortex-a72";
111 enable-method = "psci";
112 d-cache-size = <0x8000>;
113 d-cache-line-size = <64>;
114 d-cache-sets = <256>;
115 i-cache-size = <0xc000>;
116 i-cache-line-size = <64>;
117 i-cache-sets = <256>;
118 next-level-cache = <&cluster1_l2>;
123 compatible = "arm,cortex-a72";
125 enable-method = "psci";
126 d-cache-size = <0x8000>;
127 d-cache-line-size = <64>;
128 d-cache-sets = <256>;
129 i-cache-size = <0xc000>;
130 i-cache-line-size = <64>;
131 i-cache-sets = <256>;
132 next-level-cache = <&cluster1_l2>;
137 compatible = "arm,cortex-a72";
139 enable-method = "psci";
140 d-cache-size = <0x8000>;
141 d-cache-line-size = <64>;
142 d-cache-sets = <256>;
143 i-cache-size = <0xc000>;
144 i-cache-line-size = <64>;
145 i-cache-sets = <256>;
146 next-level-cache = <&cluster2_l2>;
151 compatible = "arm,cortex-a72";
153 enable-method = "psci";
154 d-cache-size = <0x8000>;
155 d-cache-line-size = <64>;
156 d-cache-sets = <256>;
157 i-cache-size = <0xc000>;
158 i-cache-line-size = <64>;
159 i-cache-sets = <256>;
160 next-level-cache = <&cluster2_l2>;
165 compatible = "arm,cortex-a72";
167 enable-method = "psci";
168 d-cache-size = <0x8000>;
169 d-cache-line-size = <64>;
170 d-cache-sets = <256>;
171 i-cache-size = <0xc000>;
172 i-cache-line-size = <64>;
173 i-cache-sets = <256>;
174 next-level-cache = <&cluster2_l2>;
179 compatible = "arm,cortex-a72";
181 enable-method = "psci";
182 d-cache-size = <0x8000>;
183 d-cache-line-size = <64>;
184 d-cache-sets = <256>;
185 i-cache-size = <0xc000>;
186 i-cache-line-size = <64>;
187 i-cache-sets = <256>;
188 next-level-cache = <&cluster2_l2>;
193 compatible = "arm,cortex-a72";
195 enable-method = "psci";
196 d-cache-size = <0x8000>;
197 d-cache-line-size = <64>;
198 d-cache-sets = <256>;
199 i-cache-size = <0xc000>;
200 i-cache-line-size = <64>;
201 i-cache-sets = <256>;
202 next-level-cache = <&cluster3_l2>;
207 compatible = "arm,cortex-a72";
209 enable-method = "psci";
210 d-cache-size = <0x8000>;
211 d-cache-line-size = <64>;
212 d-cache-sets = <256>;
213 i-cache-size = <0xc000>;
214 i-cache-line-size = <64>;
215 i-cache-sets = <256>;
216 next-level-cache = <&cluster3_l2>;
221 compatible = "arm,cortex-a72";
223 enable-method = "psci";
224 d-cache-size = <0x8000>;
225 d-cache-line-size = <64>;
226 d-cache-sets = <256>;
227 i-cache-size = <0xc000>;
228 i-cache-line-size = <64>;
229 i-cache-sets = <256>;
230 next-level-cache = <&cluster3_l2>;
235 compatible = "arm,cortex-a72";
237 enable-method = "psci";
238 d-cache-size = <0x8000>;
239 d-cache-line-size = <64>;
240 d-cache-sets = <256>;
241 i-cache-size = <0xc000>;
242 i-cache-line-size = <64>;
243 i-cache-sets = <256>;
244 next-level-cache = <&cluster3_l2>;
249 cache-size = <0x200000>;
250 cache-line-size = <64>;
251 cache-sets = <2048>;
252 cache-level = <2>;
257 cache-size = <0x200000>;
258 cache-line-size = <64>;
259 cache-sets = <2048>;
260 cache-level = <2>;
265 cache-size = <0x200000>;
266 cache-line-size = <64>;
267 cache-sets = <2048>;
268 cache-level = <2>;
273 cache-size = <0x200000>;
274 cache-line-size = <64>;
275 cache-sets = <2048>;
276 cache-level = <2>;
281 reserved-memory {
282 #address-cells = <2>;
283 #size-cells = <2>;
288 no-map;
293 compatible = "arm,psci-0.2";
294 method = "smc";
298 compatible = "arm,armv8-timer";
306 compatible = "arm,cortex-a72-pmu";
312 compatible = "simple-bus";
313 #address-cells = <2>;
314 #size-cells = <2>;
317 gic: interrupt-controller@f0000000 {
318 compatible = "arm,gic-v3";
319 #interrupt-cells = <3>;
320 interrupt-controller;
330 compatible = "pci-host-ecam-generic";
332 #size-cells = <2>;
333 #address-cells = <3>;
334 #interrupt-cells = <1>;
336 interrupt-map-mask = <0xf800 0 0 7>;
338 interrupt-map = <0x4000 0 0 1 &gic 0 57 IRQ_TYPE_LEVEL_HIGH>,
347 bus-range = <0x00 0x00>;
348 msi-parent = <&msix>;
352 compatible = "al,alpine-msix";
354 interrupt-controller;
355 msi-controller;
356 al,msi-base-spi = <336>;
357 al,msi-num-spis = <959>;
358 interrupt-parent = <&gic>;
361 io-fabric {
362 compatible = "simple-bus";
363 #address-cells = <1>;
364 #size-cells = <1>;
371 clock-frequency = <0>; /* Filled by firmware */
372 reg-shift = <2>;
373 reg-io-width = <4>;
381 clock-frequency = <0>; /* Filled by firmware */
382 reg-shift = <2>;
383 reg-io-width = <4>;
391 clock-frequency = <0>; /* Filled by firmware */
392 reg-shift = <2>;
393 reg-io-width = <4>;
401 clock-frequency = <0>; /* Filled by firmware */
402 reg-shift = <2>;
403 reg-io-width = <4>;