cycles (full) in projects: Linux-v6.1 - OpenGrok search results

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Searched full:cycles (Results 1 – 25 of 1347) sorted by relevance

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/Linux-v6.1/tools/perf/tests/shell/
D	stat.sh	`33 if ! perf stat -e '{cycles,cycles,cycles,cycles,cycles,cycles,cycles,cycles,cycles,cycles}' \ 39 …if ! perf stat -r2 -e '{cycles,cycles,cycles,cycles,cycles,cycles,cycles,cycles,cycles,cycles}:W' \ 78 …nstructions,branch-misses,bus-cycles,cache-misses,cache-references,cpu-cycles,instructions,mem-loa… 84 …nstructions,branch-misses,bus-cycles,cache-misses,cache-references,cpu-cycles,instructions,mem-loa…`
/Linux-v6.1/tools/perf/pmu-events/arch/x86/jaketown/
D	uncore-power.json	3 "BriefDescription": "pclk Cycles", 7 …CU runs off a fixed 800 MHz clock. This event counts the number of pclk cycles measured while the… 11 "BriefDescription": "Core C State Transition Cycles", 17 …"PublicDescription": "Number of cycles spent performing core C state transitions. There is one ev… 21 "BriefDescription": "Core C State Transition Cycles", 27 …"PublicDescription": "Number of cycles spent performing core C state transitions. There is one ev… 31 "BriefDescription": "Core C State Transition Cycles", 37 …"PublicDescription": "Number of cycles spent performing core C state transitions. There is one ev… 41 "BriefDescription": "Core C State Transition Cycles", 47 …"PublicDescription": "Number of cycles spent performing core C state transitions. There is one ev… [all …]
D	uncore-memory.json	128 "BriefDescription": "Cycles in a Major Mode; Isoch Major Mode", 133 …"PublicDescription": "Counts the total number of cycles spent in a major mode (selected by a filte… 138 "BriefDescription": "Cycles in a Major Mode; Partial Major Mode", 143 …"PublicDescription": "Counts the total number of cycles spent in a major mode (selected by a filte… 148 "BriefDescription": "Cycles in a Major Mode; Read Major Mode", 153 …"PublicDescription": "Counts the total number of cycles spent in a major mode (selected by a filte… 158 "BriefDescription": "Cycles in a Major Mode; Write Major Mode", 163 …"PublicDescription": "Counts the total number of cycles spent in a major mode (selected by a filte… 168 "BriefDescription": "Channel DLLOFF Cycles", 173 …"PublicDescription": "Number of cycles when all the ranks in the channel are in CKE Slow (DLLOFF) … [all …]
/Linux-v6.1/arch/alpha/include/asm/
D	xor.h	`73 xor $0,$1,$0 # 7 cycles from $1 load \n\ 130 xor $0,$1,$1 # 8 cycles from $0 load \n\ 131 xor $3,$4,$4 # 6 cycles from $4 load \n\ 132 xor $6,$7,$7 # 6 cycles from $7 load \n\ 133 xor $21,$22,$22 # 5 cycles from $22 load \n\ 135 xor $1,$2,$2 # 9 cycles from $2 load \n\ 136 xor $24,$25,$25 # 5 cycles from $25 load \n\ 138 xor $4,$5,$5 # 6 cycles from $5 load \n\ 141 xor $7,$20,$20 # 7 cycles from $20 load \n\ 143 xor $22,$23,$23 # 7 cycles from $23 load \n\ [all …]`
/Linux-v6.1/tools/perf/pmu-events/arch/powerpc/power10/
D	metrics.json	3 "BriefDescription": "Percentage of cycles that are run cycles", 10 "BriefDescription": "Average cycles per completed instruction", 16 …"BriefDescription": "Average cycles per completed instruction when dispatch was stalled for any re… 22 …"BriefDescription": "Average cycles per completed instruction when dispatch was stalled because th… 28 …"BriefDescription": "Average cycles per completed instruction when dispatch was stalled because th… 34 …"BriefDescription": "Average cycles per completed instruction when dispatch was stalled waiting to… 40 …"BriefDescription": "Average cycles per completed instruction when dispatch was stalled waiting to… 46 …"BriefDescription": "Average cycles per completed instruction when dispatch was stalled due to an … 52 …"BriefDescription": "Average cycles per completed instruction when dispatch was stalled while the … 58 …"BriefDescription": "Average cycles per completed instruction when dispatch was stalled while the … [all …]
D	frontend.json	5 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline suffered a TLB miss or… 10 …"BriefDescription": "Cycles in which the NTC instruction is held at dispatch for any other reason." 25 …"BriefDescription": "Cycles when dispatch was stalled for this thread because the MMU was handling… 30 …"BriefDescription": "Cycles when dispatch was stalled while the instruction was fetched from the l… 35 …"BriefDescription": "Cycles in which the NTC instruction is held at dispatch because of power mana… 40 …"BriefDescription": "Cycles in which the NTC instruction is held at dispatch because the STF mappe… 50 …"BriefDescription": "Cycles when dispatch was stalled while the instruction was fetched from the l… 65 "BriefDescription": "Cycles in which at least one instruction is completed by this thread." 75 …"BriefDescription": "Cycles the ICT has no itags assigned to this thread (no instructions were dis… 80 …"BriefDescription": "Cycles in which the NTC instruction is held at dispatch due to Issue queue fu… [all …]
D	pipeline.json	30 "BriefDescription": "Cycles in which an instruction reload is pending to satisfy a demand miss." 45 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline finished at dispatch a… 60 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was a lwsync waiting t… 75 "BriefDescription": "Cycles when the run latch is set and the core is in ST mode." 80 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was dispatched but not… 85 "BriefDescription": "Cycles when the thread is in Hypervisor state. MSR[S HV PR]=010." 95 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline required special handl… 100 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load… 115 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was executing in the V… 120 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was a stcx waiting for… [all …]
/Linux-v6.1/tools/perf/pmu-events/arch/x86/broadwellde/
D	uncore-power.json	3 "BriefDescription": "pclk Cycles", 7 … PCU runs off a fixed 1 GHz clock. This event counts the number of pclk cycles measured while the… 11 "BriefDescription": "Core C State Transition Cycles", 16 …"PublicDescription": "Number of cycles spent performing core C state transitions. There is one ev… 20 "BriefDescription": "Core C State Transition Cycles", 25 …"PublicDescription": "Number of cycles spent performing core C state transitions. There is one ev… 29 "BriefDescription": "Core C State Transition Cycles", 34 …"PublicDescription": "Number of cycles spent performing core C state transitions. There is one ev… 38 "BriefDescription": "Core C State Transition Cycles", 43 …"PublicDescription": "Number of cycles spent performing core C state transitions. There is one ev… [all …]
D	pipeline.json	3 "BriefDescription": "Cycles when divider is busy executing divide operations", 381 "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)", 392 …"BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalte… 410 "BriefDescription": "Reference cycles when the core is not in halt state.", 414 …"PublicDescription": "This event counts the number of reference cycles when the core is not in a h… 419 "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)", 424 … "PublicDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate).", 430 …"BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalte… 439 "BriefDescription": "Core cycles when the thread is not in halt state", 443 …"PublicDescription": "This event counts the number of core cycles while the thread is not in a hal… [all …]
/Linux-v6.1/tools/perf/pmu-events/arch/x86/ivytown/
D	uncore-power.json	3 "BriefDescription": "pclk Cycles", 7 …CU runs off a fixed 800 MHz clock. This event counts the number of pclk cycles measured while the… 11 "BriefDescription": "Core 0 C State Transition Cycles", 16 …"PublicDescription": "Number of cycles spent performing core C state transitions. There is one ev… 20 "BriefDescription": "Core 10 C State Transition Cycles", 25 …"PublicDescription": "Number of cycles spent performing core C state transitions. There is one ev… 29 "BriefDescription": "Core 11 C State Transition Cycles", 34 …"PublicDescription": "Number of cycles spent performing core C state transitions. There is one ev… 38 "BriefDescription": "Core 12 C State Transition Cycles", 43 …"PublicDescription": "Number of cycles spent performing core C state transitions. There is one ev… [all …]
D	frontend.json	23 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles", 28 "PublicDescription": "Cycles DSB to MITE switches caused delay.", 33 …"BriefDescription": "Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stre… 53 …"BriefDescription": "Cycles where a code-fetch stalled due to L1 instruction-cache miss or an iTLB… 58 …"PublicDescription": "Cycles where a code-fetch stalled due to L1 instruction-cache miss or an iTL… 73 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops", 79 "PublicDescription": "Counts cycles DSB is delivered four uops. Set Cmask = 4.", 84 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop", 90 "PublicDescription": "Counts cycles DSB is delivered at least one uops. Set Cmask = 1.", 95 "BriefDescription": "Cycles MITE is delivering 4 Uops", [all …]
/Linux-v6.1/tools/perf/pmu-events/arch/x86/amdzen3/
D	other.json	5 "BriefDescription": "Cycles where the Micro-Op Queue is empty." 22 …"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a T… 28 …"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a T… 34 …"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a T… 40 …"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a T… 46 …"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a t… 52 …"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a T… 58 …"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a T… 64 …"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a T… 70 …"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a t… [all …]
/Linux-v6.1/Documentation/devicetree/bindings/bus/
D	qcom,ebi2.txt	34 FIXME: the manual mentions "write precharge cycles" and "precharge cycles". 77 - qcom,xmem-recovery-cycles: recovery cycles is the time the memory continues to 82 - qcom,xmem-write-hold-cycles: write hold cycles, these are extra cycles 86 - qcom,xmem-write-delta-cycles: initial latency for write cycles inserted for 88 - qcom,xmem-read-delta-cycles: initial latency for read cycles inserted for the 90 - qcom,xmem-write-wait-cycles: number of wait cycles for every write access, 0=1 92 - qcom,xmem-read-wait-cycles: number of wait cycles for every read access, 0=1 99 - qcom,xmem-adv-to-oe-recovery-cycles: the number of cycles elapsed before an OE 101 2 means 2 cycles between ADV and OE. Valid values 0, 1, 2 or 3. 102 - qcom,xmem-read-hold-cycles: the length in cycles of the first segment of a [all …]
/Linux-v6.1/tools/perf/pmu-events/arch/x86/skylakex/
D	frontend.json	18 …er (DSB) cache and u-arch forced misses.\nNote: Invoking MITE requires two or three cycles delay.", 23 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", 28 …cycles. These cycles do not include uops routed through because of the switch itself, for example,… 115 …er an interval where the front-end delivered no uops for a period of 128 cycles which was not inte… 128 …ter an interval where the front-end delivered no uops for a period of 16 cycles which was not inte… 136 …hat are delivered to the back-end after a front-end stall of at least 16 cycles. During this perio… 142 …fter an interval where the front-end delivered no uops for a period of 2 cycles which was not inte… 155 …er an interval where the front-end delivered no uops for a period of 256 cycles which was not inte… 168 …nterval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not inte… 176 …ack-end after the front-end had at least 1 bubble-slot for a period of 2 cycles. A bubble-slot is … [all …]
D	pipeline.json	3 …"BriefDescription": "Cycles when divide unit is busy executing divide or square root operations. A… 180 …"BriefDescription": "Core crystal clock cycles when this thread is unhalted and the other thread i… 189 "BriefDescription": "Core crystal clock cycles when the thread is unhalted.", 199 …"BriefDescription": "Core crystal clock cycles when at least one thread on the physical core is un… 208 …"BriefDescription": "Core crystal clock cycles when this thread is unhalted and the other thread i… 217 "BriefDescription": "Reference cycles when the core is not in halt state.", 221 …"PublicDescription": "Counts the number of reference cycles when the core is not in a halt state. … 226 "BriefDescription": "Core crystal clock cycles when the thread is unhalted.", 236 …"BriefDescription": "Core crystal clock cycles when at least one thread on the physical core is un… 256 "BriefDescription": "Core cycles when the thread is not in halt state", [all …]
/Linux-v6.1/tools/perf/pmu-events/arch/x86/cascadelakex/
D	frontend.json	18 …er (DSB) cache and u-arch forced misses.\nNote: Invoking MITE requires two or three cycles delay.", 23 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", 28 …cycles. These cycles do not include uops routed through because of the switch itself, for example,… 115 …er an interval where the front-end delivered no uops for a period of 128 cycles which was not inte… 128 …ter an interval where the front-end delivered no uops for a period of 16 cycles which was not inte… 136 …hat are delivered to the back-end after a front-end stall of at least 16 cycles. During this perio… 142 …fter an interval where the front-end delivered no uops for a period of 2 cycles which was not inte… 155 …er an interval where the front-end delivered no uops for a period of 256 cycles which was not inte… 168 …nterval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not inte… 176 …ack-end after the front-end had at least 1 bubble-slot for a period of 2 cycles. A bubble-slot is … [all …]
D	pipeline.json	3 …"BriefDescription": "Cycles when divide unit is busy executing divide or square root operations. A… 180 …"BriefDescription": "Core crystal clock cycles when this thread is unhalted and the other thread i… 189 "BriefDescription": "Core crystal clock cycles when the thread is unhalted.", 199 …"BriefDescription": "Core crystal clock cycles when at least one thread on the physical core is un… 208 …"BriefDescription": "Core crystal clock cycles when this thread is unhalted and the other thread i… 217 "BriefDescription": "Reference cycles when the core is not in halt state.", 221 …"PublicDescription": "Counts the number of reference cycles when the core is not in a halt state. … 226 "BriefDescription": "Core crystal clock cycles when the thread is unhalted.", 236 …"BriefDescription": "Core crystal clock cycles when at least one thread on the physical core is un… 256 "BriefDescription": "Core cycles when the thread is not in halt state", [all …]
/Linux-v6.1/tools/perf/pmu-events/arch/x86/skylake/
D	frontend.json	18 …er (DSB) cache and u-arch forced misses.\nNote: Invoking MITE requires two or three cycles delay.", 23 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", 28 …cycles. These cycles do not include uops routed through because of the switch itself, for example,… 115 …er an interval where the front-end delivered no uops for a period of 128 cycles which was not inte… 128 …ter an interval where the front-end delivered no uops for a period of 16 cycles which was not inte… 136 …hat are delivered to the back-end after a front-end stall of at least 16 cycles. During this perio… 142 …fter an interval where the front-end delivered no uops for a period of 2 cycles which was not inte… 155 …er an interval where the front-end delivered no uops for a period of 256 cycles which was not inte… 168 …nterval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not inte… 176 …ack-end after the front-end had at least 1 bubble-slot for a period of 2 cycles. A bubble-slot is … [all …]
D	pipeline.json	3 …"BriefDescription": "Cycles when divide unit is busy executing divide or square root operations. A… 169 …"BriefDescription": "Core crystal clock cycles when this thread is unhalted and the other thread i… 178 "BriefDescription": "Core crystal clock cycles when the thread is unhalted.", 188 …"BriefDescription": "Core crystal clock cycles when at least one thread on the physical core is un… 197 …"BriefDescription": "Core crystal clock cycles when this thread is unhalted and the other thread i… 206 "BriefDescription": "Reference cycles when the core is not in halt state.", 210 …"PublicDescription": "Counts the number of reference cycles when the core is not in a halt state. … 215 "BriefDescription": "Core crystal clock cycles when the thread is unhalted.", 225 …"BriefDescription": "Core crystal clock cycles when at least one thread on the physical core is un… 245 "BriefDescription": "Core cycles when the thread is not in halt state", [all …]
/Linux-v6.1/tools/perf/pmu-events/arch/x86/ivybridge/
D	frontend.json	23 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles", 28 "PublicDescription": "Cycles DSB to MITE switches caused delay.", 33 …"BriefDescription": "Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stre… 53 …"BriefDescription": "Cycles where a code-fetch stalled due to L1 instruction-cache miss or an iTLB… 58 …"PublicDescription": "Cycles where a code-fetch stalled due to L1 instruction-cache miss or an iTL… 73 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops", 79 "PublicDescription": "Counts cycles DSB is delivered four uops. Set Cmask = 4.", 84 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop", 90 "PublicDescription": "Counts cycles DSB is delivered at least one uops. Set Cmask = 1.", 95 "BriefDescription": "Cycles MITE is delivering 4 Uops", [all …]
/Linux-v6.1/tools/perf/pmu-events/arch/x86/haswellx/
D	pipeline.json	345 "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)", 356 …"BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalte… 361 …"PublicDescription": "Reference cycles when the at least one thread on the physical core is unhalt… 375 "BriefDescription": "Reference cycles when the core is not in halt state.", 379 …"PublicDescription": "This event counts the number of reference cycles when the core is not in a h… 384 "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)", 389 … "PublicDescription": "Reference cycles when the thread is unhalted. (counts at 100 MHz rate)", 395 …"BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalte… 400 …"PublicDescription": "Reference cycles when the at least one thread on the physical core is unhalt… 405 "BriefDescription": "Core cycles when the thread is not in halt state.", [all …]
/Linux-v6.1/tools/perf/pmu-events/arch/x86/haswell/
D	pipeline.json	345 "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)", 356 …"BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalte… 361 …"PublicDescription": "Reference cycles when the at least one thread on the physical core is unhalt… 375 "BriefDescription": "Reference cycles when the core is not in halt state.", 379 …"PublicDescription": "This event counts the number of reference cycles when the core is not in a h… 384 "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)", 389 … "PublicDescription": "Reference cycles when the thread is unhalted. (counts at 100 MHz rate)", 395 …"BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalte… 400 …"PublicDescription": "Reference cycles when the at least one thread on the physical core is unhalt… 405 "BriefDescription": "Core cycles when the thread is not in halt state.", [all …]
/Linux-v6.1/tools/perf/pmu-events/arch/x86/amdzen2/
D	other.json	5 "BriefDescription": "Cycles where the Micro-Op Queue is empty." 28 …"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a t… 34 …"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a t… 40 …"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a t… 46 …"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a t… 52 …"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a t… 58 …"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a t… 64 …"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a t… 70 …"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a t… 76 …"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a t… [all …]
/Linux-v6.1/tools/perf/dlfilters/
D	dlfilter-show-cycles.c	3 * dlfilter-show-cycles.c: Print the number of cycles at the start of each line 19 static __u64 cycles[MAX_CPU][MAX_ENTRY]; variable 30 __u64 cycles[MAX_ENTRY]; member 77 e->cycles[pos] += cnt; in add_entry() 92 cycles[cpu][pos] += sample->cyc_cnt; in filter_event_early() 98 static void print_vals(__u64 cycles, __u64 delta) in print_vals() argument 101 printf("%10llu %10llu ", (unsigned long long)cycles, (unsigned long long)delta); in print_vals() 103 printf("%10llu %10s ", (unsigned long long)cycles, ""); in print_vals() 115 print_vals(cycles[cpu][pos], cycles[cpu][pos] - cycles_rpt[cpu][pos]); in filter_event() 116 cycles_rpt[cpu][pos] = cycles[cpu][pos]; in filter_event() [all …]
/Linux-v6.1/tools/perf/pmu-events/arch/x86/sapphirerapids/
D	frontend.json	9 …"PublicDescription": "Counts cycles that the Instruction Length decoder (ILD) stalls occurred due … 15 "BriefDescription": "Cycles the Microcode Sequencer is busy.", 26 "BriefDescription": "DSB-to-MITE switch true penalty cycles.", 32 …y the legacy x86 decode pipeline (MITE). This event counts fetch penalty cycles when a transition … 128 …er an interval where the front-end delivered no uops for a period of 128 cycles which was not inte… 137 …er an interval where the front-end delivered no uops for a period of 128 cycles which was not inte… 143 …ter an interval where the front-end delivered no uops for a period of 16 cycles which was not inte… 152 …hat are delivered to the back-end after a front-end stall of at least 16 cycles. During this perio… 158 "BriefDescription": "Retired instructions after front-end starvation of at least 2 cycles", 167 …nterval where the front-end delivered no uops for a period of at least 2 cycles which was not inte… [all …]

12 3 4 5 6 7 8 9 10 >>...54