Lines Matching full:cycles

30     "BriefDescription": "Cycles in which an instruction reload is pending to satisfy a demand miss."
45 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline finished at dispatch a…
60 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was a lwsync waiting t…
75     "BriefDescription": "Cycles when the run latch is set and the core is in ST mode."
80 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was dispatched but not…
85     "BriefDescription": "Cycles when the thread is in Hypervisor state. MSR[S HV PR]=010."
95 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline required special handl…
100 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load…
115 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was executing in the V…
120 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was a stcx waiting for…
125 …Cycles in which the oldest instruction in the pipeline was executing in any unit before it was flu…
135 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline (NTC) finishes. Note t…
145     "BriefDescription": "Processor cycles gated by the run latch."
150 …ption": "Cycles in which the oldest instruction in the pipeline was waiting to finish in one of th…
175 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for the no…
180 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was a simple fixed poi…
185 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was not allowed to com…
215 …"BriefDescription": "Cycles in which both instructions in the ICT entry pair show as finished. The…
225 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline suffered an ERAT miss …
230 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline cannot complete becaus…
240 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was executing in the B…
245 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was a hwsync waiting f…
250 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was a TLBIEL instructi…
255 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline completed without an n…
285     "BriefDescription": "Cycles at least one Instr Dispatched."