| /Linux-v5.10/Documentation/devicetree/bindings/clock/ |
| D | brcm,kona-ccu.txt | 4 clock control units (CCUs). A CCU is a clock provider that manages
5 a set of clock signals. Each CCU is represented by a node in the
8 This binding uses the common clock binding:
9 Documentation/devicetree/bindings/clock/clock-bindings.txt
12 - compatible
13 Shall have a value of the form "brcm,<model>-<which>-ccu",
16 "brcm,bcm11351-root-ccu"
19 - reg
21 containing clock control registers
22 - #clock-cells
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| D | silabs,si5351.txt | 1 Binding for Silicon Labs Si5351a/b/c programmable i2c clock generator.
7 The Si5351a/b/c are programmable i2c clock generators with up to 8 output
8 clocks. Si5351a also has a reduced pin-count package (MSOP10) where only
9 3 output clocks are accessible. The internal structure of the clock
15 - compatible: shall be one of the following:
16 "silabs,si5351a" - Si5351a, QFN20 package
17 "silabs,si5351a-msop" - Si5351a, MSOP10 package
18 "silabs,si5351b" - Si5351b, QFN20 package
19 "silabs,si5351c" - Si5351c, QFN20 package
20 - reg: i2c device address, shall be 0x60 or 0x61.
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| /Linux-v5.10/drivers/spi/ |
| D | spi-cadence.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Cadence SPI controller driver (master mode only)
5 * Copyright (C) 2008 - 2014 Xilinx, Inc.
7 * based on Blackfin On-Chip SPI Driver (spi_bfin5xx.c)
23 #define CDNS_SPI_NAME "cdns-spi"
46 #define CDNS_SPI_CR_CPHA 0x00000004 /* Clock Phase Control */
47 #define CDNS_SPI_CR_CPOL 0x00000002 /* Clock Polarity Control */
51 #define CDNS_SPI_CR_MSTREN 0x00000001 /* Master Enable Mask */
61 * SPI Configuration Register - Baud rate and slave select
102 * struct cdns_spi - This definition defines spi driver instance
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| D | spi-jcore.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * J-Core SPI controller driver
5 * Copyright (C) 2012-2016 Smart Energy Instruments, Inc.
36 struct spi_master *master; member
52 } while (--timeout); in jcore_spi_wait()
54 return -EBUSY; in jcore_spi_wait()
59 void __iomem *ctrl_reg = hw->base + CTRL_REG; in jcore_spi_program()
62 dev_err(hw->master->dev.parent, in jcore_spi_program()
65 writel(hw->cs_reg | hw->speed_reg, ctrl_reg); in jcore_spi_program()
70 struct jcore_spi *hw = spi_master_get_devdata(spi->master); in jcore_spi_chipsel()
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| D | spi-ppc4xx.c | 1 // SPDX-License-Identifier: GPL-2.0-only
39 #include <asm/dcr-regs.h>
41 /* bits in mode register - bit 0 is MSb */
44 * SPI_PPC4XX_MODE_SCP = 0 means "data latched on trailing edge of clock"
45 * SPI_PPC4XX_MODE_SCP = 1 means "data latched on leading edge of clock"
54 * SPI_PPC4XX_MODE_RD = 0 means "MSB first" - this is the normal mode
55 * SPI_PPC4XX_MODE_RD = 1 means "LSB first" - this is bit-reversed mode
61 * SPI_PPC4XX_MODE_CI = 0 means "clock idles low"
62 * SPI_PPC4XX_MODE_CI = 1 means "clock idles high"
83 /* clock settings (SCP and CI) for various SPI modes */
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| D | spi-sifive.c | 1 // SPDX-License-Identifier: GPL-2.0
5 // SiFive SPI controller driver (master mode only)
26 #define SIFIVE_SPI_REG_SCKDIV 0x00 /* Serial clock divisor */
27 #define SIFIVE_SPI_REG_SCKMODE 0x04 /* Serial clock mode */
93 struct clk *clk; /* bus clock */
96 struct completion done; /* wake-up from interrupt */
101 iowrite32(value, spi->regs + offset); in sifive_spi_write()
106 return ioread32(spi->regs + offset); in sifive_spi_read()
126 /* Exit specialized memory-mapped SPI flash mode */ in sifive_spi_init()
131 sifive_spi_prepare_message(struct spi_master *master, struct spi_message *msg) in sifive_spi_prepare_message() argument
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| D | spi-uniphier.c | 1 // SPDX-License-Identifier: GPL-2.0
2 // spi-uniphier.c - Socionext UniPhier SPI controller driver
4 // Copyright 2016-2018 Socionext Inc.
29 struct spi_master *master; member
113 val = readl(priv->base + SSI_IE); in uniphier_spi_irq_enable()
115 writel(val, priv->base + SSI_IE); in uniphier_spi_irq_enable()
123 val = readl(priv->base + SSI_IE); in uniphier_spi_irq_disable()
125 writel(val, priv->base + SSI_IE); in uniphier_spi_irq_disable()
130 struct uniphier_spi_priv *priv = spi_master_get_devdata(spi->master); in uniphier_spi_set_mode()
134 * clock setting in uniphier_spi_set_mode()
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| D | spi-sun4i.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2012 - 2014 Allwinner Tech
7 * Maxime Ripard <maxime.ripard@free-electrons.com>
78 struct spi_master *master; member
92 return readl(sspi->base_addr + reg); in sun4i_spi_read()
97 writel(value, sspi->base_addr + reg); in sun4i_spi_write()
138 while (len--) { in sun4i_spi_drain_fifo()
139 byte = readb(sspi->base_addr + SUN4I_RXDATA_REG); in sun4i_spi_drain_fifo()
140 if (sspi->rx_buf) in sun4i_spi_drain_fifo()
141 *sspi->rx_buf++ = byte; in sun4i_spi_drain_fifo()
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| /Linux-v5.10/sound/soc/sh/ |
| D | fsi.c | 1 // SPDX-License-Identifier: GPL-2.0
3 // Fifo-attached Serial Interface (FSI) support for SH7724
12 #include <linux/dma-mapping.h>
42 /* master register */
102 #define SE (1 << 0) /* Fix the master clock */
166 * |<-------------------- period--------------------->|
169 * ||<----- frame ----->|<------ frame ----->| ... |
170 * |+--------------------+--------------------+- ... |
172 * |+--------------------+--------------------+- ... |
185 * --> go to codecs
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| /Linux-v5.10/Documentation/sound/soc/ |
| D | clocking.rst | 9 Master Clock
10 ------------
12 Every audio subsystem is driven by a master clock (sometimes referred to as MCLK
13 or SYSCLK). This audio master clock can be derived from a number of sources
14 (e.g. crystal, PLL, CPU clock) and is responsible for producing the correct
17 Some master clocks (e.g. PLLs and CPU based clocks) are configurable in that
19 power). Other master clocks are fixed at a set frequency (i.e. crystals).
23 ----------
24 The Digital Audio Interface is usually driven by a Bit Clock (often referred to
25 as BCLK). This clock is used to drive the digital audio data across the link
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| /Linux-v5.10/Documentation/devicetree/bindings/sound/ |
| D | simple-card.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/sound/simple-card.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
14 frame-master:
15 description: Indicates dai-link frame master.
16 $ref: /schemas/types.yaml#/definitions/phandle-array
19 bitclock-master:
20 description: Indicates dai-link bit clock master
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| D | marvell,mmp-sspa.yaml | 1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/marvell,mmp-sspa.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lubomir Rintel <lkundrak@v3.sk>
14 pattern: "^audio-controller(@.*)?$"
17 const: marvell,mmp-sspa
21 - description: RX block
22 - description: TX block
29 - description: Clock for the Audio block
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| /Linux-v5.10/Documentation/devicetree/bindings/pci/ |
| D | qcom,pcie.txt | 3 - compatible:
7 - "qcom,pcie-ipq8064" for ipq8064
8 - "qcom,pcie-ipq8064-v2" for ipq8064 rev 2 or ipq8065
9 - "qcom,pcie-apq8064" for apq8064
10 - "qcom,pcie-apq8084" for apq8084
11 - "qcom,pcie-msm8996" for msm8996 or apq8096
12 - "qcom,pcie-ipq4019" for ipq4019
13 - "qcom,pcie-ipq8074" for ipq8074
14 - "qcom,pcie-qcs404" for qcs404
15 - "qcom,pcie-sdm845" for sdm845
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| /Linux-v5.10/include/linux/soundwire/ |
| D | sdw.h | 1 /* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
2 /* Copyright(c) 2015-17 Intel Corporation. */
25 /* SDW Master Device Number, not supported yet */
71 * enum sdw_slave_status - Slave status
85 * enum sdw_clk_stop_type: clock stop operations
87 * @SDW_CLK_PRE_PREPARE: pre clock stop prepare
88 * @SDW_CLK_POST_PREPARE: post clock stop prepare
89 * @SDW_CLK_PRE_DEPREPARE: pre clock stop de-prepare
90 * @SDW_CLK_POST_DEPREPARE: post clock stop de-prepare
100 * enum sdw_command_response - Command response as defined by SDW spec
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| /Linux-v5.10/Documentation/spi/ |
| D | spi-summary.rst | 5 02-Feb-2012
8 ------------
12 standardization body. SPI uses a master/slave configuration.
14 The three signal wires hold a clock (SCK, often on the order of 10 MHz),
15 and parallel data lines with "Master Out, Slave In" (MOSI) or "Master In,
17 clocking modes through which data is exchanged; mode-0 and mode-3 are most
18 commonly used. Each clock cycle shifts data out and data in; the clock
26 other signals, often including an interrupt to the master.
32 - SPI may be used for request/response style device protocols, as with
35 - It may also be used to stream data in either direction (half duplex),
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| /Linux-v5.10/Documentation/driver-api/soundwire/ |
| D | summary.rst | 10 SoundWire is a 2-pin multi-drop interface with data and clock line. It
15 commands over a single two-pin interface.
17 (2) Lower clock frequency, and hence lower power consumption, by use of DDR
20 (3) Clock scaling and optional multiple data lanes to give wide flexibility
23 (4) Device status monitoring, including interrupt-style alerts to the Master.
26 interfaces share the common Bus containing data and clock line. Each of the
35 Below figure shows an example of connectivity between a SoundWire Master and
38 +---------------+ +---------------+
39 | | Clock Signal | |
40 | Master |-------+-------------------------------| Slave |
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| /Linux-v5.10/sound/soc/mxs/ |
| D | mxs-saif.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
12 #include <linux/dma-mapping.h>
14 #include <linux/clk-provider.h>
23 #include "mxs-saif.h"
31 * SAIF is a little different with other normal SOC DAIs on clock using.
33 * For MXS, two SAIF modules are instantiated on-chip.
34 * Each SAIF has a set of clock pins and can be operating in master
35 * mode simultaneously if they are connected to different off-chip codecs.
36 * Also, one of the two SAIFs can master or drive the clock pins while the
37 * other SAIF, in slave mode, receives clocking from the master SAIF.
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| /Linux-v5.10/sound/soc/atmel/ |
| D | atmel-i2s.c | 1 // SPDX-License-Identifier: GPL-2.0-only
29 * ---- I2S Controller Register map ----
44 * ---- Control Register (Write-only) ----
48 #define ATMEL_I2SC_CR_CKEN BIT(2) /* Clock Enable */
49 #define ATMEL_I2SC_CR_CKDIS BIT(3) /* Clock Disable */
55 * ---- Mode Register (Read/Write) ----
101 /* Audio Clock to I2SC Master Clock ratio */
106 /* Master Clock to fs ratio */
111 /* Master Clock mode */
113 /* 0: No master clock generated (selected clock drives I2SCK pin) */
[all …]
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| /Linux-v5.10/Documentation/ABI/testing/ |
| D | sysfs-bus-soundwire-master | 1 What: /sys/bus/soundwire/devices/sdw-master-N/revision
2 /sys/bus/soundwire/devices/sdw-master-N/clk_stop_modes
3 /sys/bus/soundwire/devices/sdw-master-N/clk_freq
4 /sys/bus/soundwire/devices/sdw-master-N/clk_gears
5 /sys/bus/soundwire/devices/sdw-master-N/default_col
6 /sys/bus/soundwire/devices/sdw-master-N/default_frame_rate
7 /sys/bus/soundwire/devices/sdw-master-N/default_row
8 /sys/bus/soundwire/devices/sdw-master-N/dynamic_shape
9 /sys/bus/soundwire/devices/sdw-master-N/err_threshold
10 /sys/bus/soundwire/devices/sdw-master-N/max_clk_freq
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| /Linux-v5.10/Documentation/i2c/ |
| D | gpio-fault-injection.rst | 5 The GPIO based I2C bus master driver can be configured to provide fault
7 which is driven by the I2C bus master driver under test. The GPIO fault
9 master driver should handle gracefully.
12 'i2c-fault-injector' subdirectory in the Kernel debugfs filesystem, usually
15 injection. They will be described now along with their intended use-cases.
21 -----
26 because the bus master under test will not be able to clock. It should detect
31 -----
36 master under test should detect this condition and trigger a bus recovery (see
52 in a bus master driver, make sure you checked your hardware setup for such
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| /Linux-v5.10/Documentation/devicetree/bindings/iommu/ |
| D | msm,iommu-v0.txt | 5 of the CPU, each connected to the IOMMU through a port called micro-TLB.
9 - compatible: Must contain "qcom,apq8064-iommu".
10 - reg: Base address and size of the IOMMU registers.
11 - interrupts: Specifiers for the MMU fault interrupts. For instances that
12 support secure mode two interrupts must be specified, for non-secure and
15 - #iommu-cells: The number of cells needed to specify the stream id. This
17 - qcom,ncb: The total number of context banks in the IOMMU.
18 - clocks : List of clocks to be used during SMMU register access. See
19 Documentation/devicetree/bindings/clock/clock-bindings.txt
20 for information about the format. For each clock specified
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| /Linux-v5.10/Documentation/devicetree/bindings/dma/ |
| D | arm-pl08x.txt | 4 - compatible: "arm,pl080", "arm,primecell";
7 - arm,primecell-periphid: on the FTDMAC020 the primecell ID is not hard-coded
11 - reg: Address range of the PL08x registers
12 - interrupt: The PL08x interrupt number
13 - clocks: The clock running the IP core clock
14 - clock-names: Must contain "apb_pclk"
15 - lli-bus-interface-ahb1: if AHB master 1 is eligible for fetching LLIs
16 - lli-bus-interface-ahb2: if AHB master 2 is eligible for fetching LLIs
17 - mem-bus-interface-ahb1: if AHB master 1 is eligible for fetching memory contents
18 - mem-bus-interface-ahb2: if AHB master 2 is eligible for fetching memory contents
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| /Linux-v5.10/include/linux/clk/ |
| D | at91_pmc.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
8 * Power Management Controller (PMC) - System peripherals registers.
18 #define AT91_PMC_SCER 0x00 /* System Clock Enable Register */
19 #define AT91_PMC_SCDR 0x04 /* System Clock Disable Register */
21 #define AT91_PMC_SCSR 0x08 /* System Clock Status Register */
22 #define AT91_PMC_PCK (1 << 0) /* Processor Clock */
23 #define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */
24 #define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Susp…
25 #define AT91RM9200_PMC_UHP (1 << 4) /* USB Host Port Clock [AT91RM9200 only] */
26 #define AT91SAM926x_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91SAM926x only] */
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| /Linux-v5.10/Documentation/devicetree/bindings/media/i2c/ |
| D | max2175.txt | 2 -----------------------------------------
4 The MAX2175 IC is an advanced analog/digital hybrid-radio receiver with
5 RF to Bits® front-end designed for software-defined radio solutions.
8 --------------------
9 - compatible: "maxim,max2175" for MAX2175 RF-to-bits tuner.
10 - clocks: clock specifier.
11 - port: child port node corresponding to the I2S output, in accordance with
13 Documentation/devicetree/bindings/media/video-interfaces.txt. The port
17 --------------------
18 - maxim,master : phandle to the master tuner if it is a slave. This
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| /Linux-v5.10/drivers/net/phy/ |
| D | dp83640.c | 1 // SPDX-License-Identifier: GPL-2.0+
99 struct dp83640_clock *clock; member
125 /* we create one clock instance per MII bus */
139 /* reference to our PTP hardware clock */
157 static int chosen_phy = -1;
166 "The address of the PHY to use for the ancillary clock features");
186 index = gpio_tab[CALIBRATE_GPIO] - 1; in dp83640_gpio_defaults()
190 index = gpio_tab[PEROUT_GPIO] - 1; in dp83640_gpio_defaults()
195 index = gpio_tab[i] - 1; in dp83640_gpio_defaults()
197 pd[index].chan = i - EXTTS0_GPIO; in dp83640_gpio_defaults()
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