Lines Matching +full:clock +full:- +full:master
10 SoundWire is a 2-pin multi-drop interface with data and clock line. It
15 commands over a single two-pin interface.
17 (2) Lower clock frequency, and hence lower power consumption, by use of DDR
20 (3) Clock scaling and optional multiple data lanes to give wide flexibility
23 (4) Device status monitoring, including interrupt-style alerts to the Master.
26 interfaces share the common Bus containing data and clock line. Each of the
35 Below figure shows an example of connectivity between a SoundWire Master and
38 +---------------+ +---------------+
39 | | Clock Signal | |
40 | Master |-------+-------------------------------| Slave |
42 | |-------|-------+-----------------------| |
43 +---------------+ | | +---------------+
47 +--+-------+--+
52 +-------------+
58 The MIPI SoundWire specification uses the term 'device' to refer to a Master
64 3rd-party vendors to enable implementation-defined functionality while
69 Programs all the MIPI-defined Slave registers. Represents a SoundWire
70 Master. Multiple instances of Bus may be present in a system.
77 Driver controlling the Slave device. MIPI-specified registers are controlled
78 directly by the Bus (and transmitted through the Master driver/interface).
79 Any implementation-defined Slave register is controlled by Slave driver. In
83 Programming interfaces (SoundWire Master interface Driver)
86 SoundWire Bus supports programming interfaces for the SoundWire Master
90 Each of the SoundWire Master interfaces needs to be registered to the Bus.
91 Bus implements API to read standard Master MIPI properties and also provides
92 callback in Master ops for Master driver to implement its own functions that
97 The Master interface along with the Master interface capabilities are
102 .. code-block:: c
110 mutex_init(&bus->lock);
111 INIT_LIST_HEAD(&bus->slaves);
122 This will initialize sdw_bus object for Master device. "sdw_master_ops" and
127 read/write messages on Bus, setting up clock frequency & Stream
129 hardware details of the Master from the Bus.
132 Master interface Port. Master interface Port register map is not defined by
135 set", "Port enable and disable". The implementation of the Master driver can
136 then perform hardware-specific configurations.
142 48-bit identifier, stored in 6 read-only dev_id registers. This dev_id
149 driver id. A parent/child relationship is enforced between Master and Slave
153 The information on Master/Slave dependencies is stored in platform data,
154 board-file, ACPI or DT. The MIPI Software specification defines additional
155 link_id parameters for controllers that have multiple Master interfaces. The
161 .. code-block:: c
199 https://members.mipi.org/wg/All-Members/document/70290
203 https://www.mipi.org/specifications/mipi-disco-soundwire