Lines Matching +full:clock +full:- +full:master
1 /* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
2 /* Copyright(c) 2015-17 Intel Corporation. */
25 /* SDW Master Device Number, not supported yet */
71 * enum sdw_slave_status - Slave status
85 * enum sdw_clk_stop_type: clock stop operations
87 * @SDW_CLK_PRE_PREPARE: pre clock stop prepare
88 * @SDW_CLK_POST_PREPARE: post clock stop prepare
89 * @SDW_CLK_PRE_DEPREPARE: pre clock stop de-prepare
90 * @SDW_CLK_POST_DEPREPARE: post clock stop de-prepare
100 * enum sdw_command_response - Command response as defined by SDW spec
180 * enum sdw_p15_behave - Slave Port 15 behaviour when the Master attempts a
191 * enum sdw_dpn_type - Data port types
206 * enum sdw_clk_stop_mode - Clock Stop modes
207 * @SDW_CLK_STOP_MODE0: Slave can continue operation seamlessly on clock
209 * @SDW_CLK_STOP_MODE1: Slave may have entered a deeper power-saving mode,
210 * not capable of continuing operation seamlessly when the clock restarts
218 * struct sdw_dp0_prop - DP0 properties
229 * implementation-defined interrupts
246 * struct sdw_dpn_audio_mode - Audio mode properties for DPn
256 * sequence and bus clock configuration
257 * If 0, Channel Prepare can happen at any Bus clock rate
258 * If 1, Channel Prepare sequence shall happen only after Bus clock is
278 * struct sdw_dpn_prop - Data Port DPn properties
291 * @ch_prep_timeout: Port-specific timeout value, in milliseconds
293 * implementation-defined interrupts
334 * struct sdw_slave_prop - SoundWire Slave properties
336 * @wake_capable: Wake-up events are supported
338 * @clk_stop_mode1: Clock-Stop Mode 1 is supported
339 * @simple_clk_stop_capable: Simple clock mode is supported
340 * @clk_stop_timeout: Worst-case latency of the Clock Stop Prepare State
342 * @ch_prep_timeout: Worst-case latency of the Channel Prepare State Machine
345 * state machine (P=1 SCSP_SM) after exit from clock-stop mode1
351 * @p15_behave: Slave behavior when the Master attempts a read to the Port15
390 * struct sdw_master_prop - Master properties
392 * @clk_stop_modes: Bitmap, bit N set when clock-stop-modeN supported
393 * @max_clk_freq: Maximum Bus clock frequency, in Hz
394 * @num_clk_gears: Number of clock gears supported
395 * @clk_gears: Clock gears supported
396 * @num_clk_freq: Number of clock frequencies supported, in Hz
397 * @clk_freq: Clock frequencies supported, in Hz
404 * @mclk_freq: clock reference passed to SoundWire Master, in Hz.
405 * @hw_disabled: if true, the Master is not functional, typically due to pin-mux
434 * struct sdw_slave_id - Slave ID
452 * Helper macros to extract the MIPI-defined IDs
481 * struct sdw_slave_intr_status - Slave interrupt status
491 * sdw_reg_bank - SoundWire register banks
503 * @clk_freq: Clock frequency, in Hz
516 * struct sdw_prepare_ch: Prepare/De-prepare Data Port channel
520 * @prepare: Prepare (true) /de-prepare (false) channel
521 * @bank: Register bank, which bank Slave/Master driver should program for
552 * @max_dr_freq: Maximum double rate clock frequency supported, in Hz
553 * @curr_dr_freq: Current double rate clock frequency, in Hz
558 * @m_data_mode: NORMAL, STATIC or PRBS mode for all Master ports. The value
603 * struct sdw_slave - SoundWire Slave
614 * @dev_num_sticky: one-time static Device Number assigned by Bus
618 * Slave state changes/implementation-defined interrupts
624 * @unattach_request: mask field to keep track why the Slave re-attached and
625 * was re-initialized. This is useful to deal with potential race conditions
626 * between the Master suspending and the codec resuming, and make sure that
627 * when the Master triggered a reset the Slave is properly enumerated and
658 * struct sdw_master_device - SoundWire 'Master Device' representation
659 * @dev: Linux device for this Master
696 * SDW master structures and APIs
763 * struct sdw_master_port_ops: Callback functions from bus to Master
764 * driver to set Master Data ports.
766 * @dpn_set_port_params: Set the Port parameters for the Master Port.
768 * @dpn_set_port_transport_params: Set transport parameters for the Master
770 * @dpn_port_prep: Port prepare operations for the Master Data Port.
771 * @dpn_port_enable_ch: Enable the channels of Master Port.
789 * struct sdw_defer - SDW deffered message
801 * struct sdw_master_ops - Master driver ops
802 * @read_prop: Read Master properties
828 * struct sdw_bus - SoundWire bus
829 * @dev: Shortcut to &bus->md->dev to avoid changing the entire code.
830 * @md: Master device
831 * @link_id: Link id number, can be 0 to N, unique for each Master
832 * @id: bus system-wide unique id
839 * @ops: Master callback ops
840 * @port_ops: Master port callback ops
842 * @prop: Master properties
843 * @m_rt_list: List of Master instance of all stream(s) running on Bus. This
844 * is used to compute and program bus bandwidth, clock, frame shape,
848 * @clk_stop_timeout: Clock stop timeout computed
854 * hardware-based synchronization is required. This value is only
855 * meaningful if multi_link is set. If set to 1, hardware-based
889 * sdw_port_config: Master or Slave Port configuration
900 * sdw_stream_config: Master or Slave stream configuration
924 * @SDW_STREAM_DEPREPARED: Stream de-prepared
957 * @master_list: List of Master runtime(s) in this stream.
958 * master_list can contain only one m_rt per Master instance
960 * @m_rt_count: Count of Master runtime(s) in this stream