Lines Matching +full:clock +full:- +full:master
3 - compatible:
7 - "qcom,pcie-ipq8064" for ipq8064
8 - "qcom,pcie-ipq8064-v2" for ipq8064 rev 2 or ipq8065
9 - "qcom,pcie-apq8064" for apq8064
10 - "qcom,pcie-apq8084" for apq8084
11 - "qcom,pcie-msm8996" for msm8996 or apq8096
12 - "qcom,pcie-ipq4019" for ipq4019
13 - "qcom,pcie-ipq8074" for ipq8074
14 - "qcom,pcie-qcs404" for qcs404
15 - "qcom,pcie-sdm845" for sdm845
17 - reg:
19 Value type: <prop-encoded-array>
20 Definition: Register ranges as listed in the reg-names property
22 - reg-names:
26 - "parf" Qualcomm specific registers
27 - "dbi" DesignWare PCIe registers
28 - "elbi" External local bus interface registers
29 - "config" PCIe configuration space
31 - device_type:
34 Definition: Should be "pci". As specified in designware-pcie.txt
36 - #address-cells:
39 Definition: Should be 3. As specified in designware-pcie.txt
41 - #size-cells:
44 Definition: Should be 2. As specified in designware-pcie.txt
46 - ranges:
48 Value type: <prop-encoded-array>
49 Definition: As specified in designware-pcie.txt
51 - interrupts:
53 Value type: <prop-encoded-array>
56 - interrupt-names:
61 - #interrupt-cells:
64 Definition: Should be 1. As specified in designware-pcie.txt
66 - interrupt-map-mask:
68 Value type: <prop-encoded-array>
69 Definition: As specified in designware-pcie.txt
71 - interrupt-map:
73 Value type: <prop-encoded-array>
74 Definition: As specified in designware-pcie.txt
76 - clocks:
78 Value type: <prop-encoded-array>
79 Definition: List of phandle and clock specifier pairs as listed
80 in clock-names property
82 - clock-names:
86 - "iface" Configuration AHB clock
88 - clock-names:
92 - "core" Clocks the pcie hw block
93 - "phy" Clocks the pcie PHY block
94 - "aux" Clocks the pcie AUX block
95 - "ref" Clocks the pcie ref block
96 - clock-names:
100 - "aux" Auxiliary (AUX) clock
101 - "bus_master" Master AXI clock
102 - "bus_slave" Slave AXI clock
104 - clock-names:
108 - "pipe" Pipe Clock driving internal logic
109 - "aux" Auxiliary (AUX) clock
110 - "cfg" Configuration clock
111 - "bus_master" Master AXI clock
112 - "bus_slave" Slave AXI clock
114 - clock-names:
118 - "iface" PCIe to SysNOC BIU clock
119 - "axi_m" AXI Master clock
120 - "axi_s" AXI Slave clock
121 - "ahb" AHB clock
122 - "aux" Auxiliary clock
124 - clock-names:
128 - "iface" AHB clock
129 - "aux" Auxiliary clock
130 - "master_bus" AXI Master clock
131 - "slave_bus" AXI Slave clock
133 -clock-names:
137 - "aux" Auxiliary clock
138 - "cfg" Configuration clock
139 - "bus_master" Master AXI clock
140 - "bus_slave" Slave AXI clock
141 - "slave_q2a" Slave Q2A clock
142 - "tbu" PCIe TBU clock
143 - "pipe" PIPE clock
145 - resets:
147 Value type: <prop-encoded-array>
149 in reset-names property
151 - reset-names:
155 - "axi" AXI reset
156 - "ahb" AHB reset
157 - "por" POR reset
158 - "pci" PCI reset
159 - "phy" PHY reset
161 - reset-names:
165 - "core" Core reset
167 - reset-names:
171 - "axi_m" AXI master reset
172 - "axi_s" AXI slave reset
173 - "pipe" PIPE reset
174 - "axi_m_vmid" VMID reset
175 - "axi_s_xpu" XPU reset
176 - "parf" PARF reset
177 - "phy" PHY reset
178 - "axi_m_sticky" AXI sticky reset
179 - "pipe_sticky" PIPE sticky reset
180 - "pwr" PWR reset
181 - "ahb" AHB reset
182 - "phy_ahb" PHY AHB reset
183 - "ext" EXT reset
185 - reset-names:
189 - "pipe" PIPE reset
190 - "sleep" Sleep reset
191 - "sticky" Core Sticky reset
192 - "axi_m" AXI Master reset
193 - "axi_s" AXI Slave reset
194 - "ahb" AHB Reset
195 - "axi_m_sticky" AXI Master Sticky reset
197 - reset-names:
201 - "axi_m" AXI Master reset
202 - "axi_s" AXI Slave reset
203 - "axi_m_sticky" AXI Master Sticky reset
204 - "pipe_sticky" PIPE sticky reset
205 - "pwr" PWR reset
206 - "ahb" AHB reset
208 - reset-names:
212 - "pci" PCIe core reset
214 - power-domains:
216 Value type: <prop-encoded-array>
221 - vdda-supply:
226 - vdda_phy-supply:
231 - vdda_refclk-supply:
235 reference clock
236 - vddpe-3v3-supply:
241 - phys:
244 Definition: List of phandle(s) as listed in phy-names property
246 - phy-names:
251 - <name>-gpios:
253 Value type: <prop-encoded-array>
255 - "perst-gpios" PCIe endpoint reset signal line
256 - "wake-gpios" PCIe endpoint wake signal line
260 compatible = "qcom,pcie-apq8064", "qcom,pcie-ipq8064", "snps,dw-pcie";
265 reg-names = "dbi", "elbi", "parf", "config";
267 linux,pci-domain = <0>;
268 bus-range = <0x00 0xff>;
269 num-lanes = <1>;
270 #address-cells = <3>;
271 #size-cells = <2>;
275 interrupt-names = "msi";
276 #interrupt-cells = <1>;
277 interrupt-map-mask = <0 0 0 0x7>;
278 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
287 clock-names = "core", "iface", "phy", "aux", "ref";
294 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
295 pinctrl-0 = <&pcie_pins_default>;
296 pinctrl-names = "default";
301 compatible = "qcom,pcie-apq8084", "snps,dw-pcie";
306 reg-names = "parf", "dbi", "elbi", "config";
308 linux,pci-domain = <0>;
309 bus-range = <0x00 0xff>;
310 num-lanes = <1>;
311 #address-cells = <3>;
312 #size-cells = <2>;
316 interrupt-names = "msi";
317 #interrupt-cells = <1>;
318 interrupt-map-mask = <0 0 0 0x7>;
319 interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
327 clock-names = "iface", "master_bus", "slave_bus", "aux";
329 reset-names = "core";
330 power-domains = <&gcc PCIE0_GDSC>;
331 vdda-supply = <&pma8084_l3>;
333 phy-names = "pciephy";
334 perst-gpio = <&tlmm 70 GPIO_ACTIVE_LOW>;
335 pinctrl-0 = <&pcie0_pins_default>;
336 pinctrl-names = "default";