| /Linux-v6.1/tools/perf/pmu-events/arch/s390/cf_z16/ |
| D | extended.json | 3 "Unit": "CPU-M-CF",
6 "BriefDescription": "L1D Read-only Exclusive Writes",
7 …Level-1 Data cache where the line was originally in a Read-Only state in the cache but has been up…
10 "Unit": "CPU-M-CF",
14 …nslation Lookaside Buffer 2 (TLB2) and the request was made by the Level-1 Data cache. This is a r…
17 "Unit": "CPU-M-CF",
21 …s for a request made by the Level-1 Data cache. Incremented by one for every TLB2 miss in progress…
24 "Unit": "CPU-M-CF",
28 …en into the Combined Region and Segment Table Entry array in the Level-2 TLB for a one-megabyte pa…
31 "Unit": "CPU-M-CF",
[all …]
|
| D | basic.json | 3 "Unit": "CPU-M-CF",
10 "Unit": "CPU-M-CF",
17 "Unit": "CPU-M-CF",
20 "BriefDescription": "Level-1 I-Cache Directory Write Count",
21 …Description": "This counter counts the total number of level-1 instruction-cache or unified-cache …
24 "Unit": "CPU-M-CF",
27 "BriefDescription": "Level-1 I-Cache Penalty Cycle Count",
28 …: "This counter counts the total number of cache penalty cycles for level-1 instruction cache or u…
31 "Unit": "CPU-M-CF",
34 "BriefDescription": "Level-1 D-Cache Directory Write Count",
[all …]
|
| /Linux-v6.1/tools/perf/pmu-events/arch/arm64/arm/cortex-a65-e1/ |
| D | cache.json | 111 …tion": "Level 1 data cache refill started due to prefetch. Counts any linefills from the prefetche…
114 …tion": "Level 1 data cache refill started due to prefetch. Counts any linefills from the prefetche…
117 …Level 2 cache refill due to prefetch. +//0 If the core is configured with a per-core L2 cache: Thi…
120 …Level 2 cache refill due to prefetch. +//0 If the core is configured with a per-core L2 cache: Thi…
123 …Level 3 cache refill due to prefetch. This event counts any linefills from the hardware prefetcher…
126 …Level 3 cache refill due to prefetch. This event counts any linefills from the hardware prefetcher…
141 …Level 2 cache write streaming mode. This event counts for each cycle where the core is in write-st…
144 …Level 2 cache write streaming mode. This event counts for each cycle where the core is in write-st…
147 …Level 3 cache write streaming mode. This event counts for each cycle where the core is in write-st…
150 …Level 3 cache write streaming mode. This event counts for each cycle where the core is in write-st…
[all …]
|
| /Linux-v6.1/tools/perf/pmu-events/arch/s390/cf_z13/ |
| D | extended.json | 3 "Unit": "CPU-M-CF",
6 "BriefDescription": "L1D Read-only Exclusive Writes",
7 …Level-1 Data cache where the line was originally in a Read-Only state in the cache but has been up…
10 "Unit": "CPU-M-CF",
14 …"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookasi…
17 "Unit": "CPU-M-CF",
21 …"PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle a DTLB…
24 "Unit": "CPU-M-CF",
27 "BriefDescription": "DTLB1 One-Megabyte Page Writes",
28 …on": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer for a …
[all …]
|
| D | basic.json | 3 "Unit": "CPU-M-CF",
10 "Unit": "CPU-M-CF",
17 "Unit": "CPU-M-CF",
20 "BriefDescription": "Level-1 I-Cache Directory Write Count",
21 …Description": "This counter counts the total number of level-1 instruction-cache or unified-cache …
24 "Unit": "CPU-M-CF",
27 "BriefDescription": "Level-1 I-Cache Penalty Cycle Count",
28 …: "This counter counts the total number of cache penalty cycles for level-1 instruction cache or u…
31 "Unit": "CPU-M-CF",
34 "BriefDescription": "Level-1 D-Cache Directory Write Count",
[all …]
|
| /Linux-v6.1/tools/perf/pmu-events/arch/s390/cf_z14/ |
| D | extended.json | 3 "Unit": "CPU-M-CF",
6 "BriefDescription": "L1D Read-only Exclusive Writes",
7 …Level-1 Data cache where the line was originally in a Read-Only state in the cache but has been up…
10 "Unit": "CPU-M-CF",
14 …ranslation Lookaside Buffer 2 (TLB2) and the request was made by the data cache. This is a replace…
17 "Unit": "CPU-M-CF",
21 …ss for a request made by the data cache. Incremented by one for every TLB2 miss in progress for th…
24 "Unit": "CPU-M-CF",
27 "BriefDescription": "DTLB2 One-Megabyte Page Writes",
28 …en into the Combined Region and Segment Table Entry array in the Level-2 TLB for a one-megabyte pa…
[all …]
|
| /Linux-v6.1/tools/perf/pmu-events/arch/arm64/arm/cortex-a55/ |
| D | cache.json | 105 …Level 3 cache refill due to prefetch. This event counts any linefills from the hardware prefetcher…
108 …Level 3 cache refill due to prefetch. This event counts any linefills from the hardware prefetcher…
111 …Level 2 cache refill due to prefetch. +//0 If the core is configured with a per-core L2 cache: Thi…
114 …Level 2 cache refill due to prefetch. +//0 If the core is configured with a per-core L2 cache: Thi…
117 …on": "Level 1 data cache refill due to prefetch. This event counts any linefills from the prefetch…
120 …on": "Level 1 data cache refill due to prefetch. This event counts any linefills from the prefetch…
123 …Level 2 cache write streaming mode. This event counts for each cycle where the core is in write-st…
126 …Level 2 cache write streaming mode. This event counts for each cycle where the core is in write-st…
129 …"PublicDescription": "Level 1 data cache entering write streaming mode.This event counts for each …
132 …"BriefDescription": "Level 1 data cache entering write streaming mode.This event counts for each e…
[all …]
|
| /Linux-v6.1/tools/perf/pmu-events/arch/s390/cf_zec12/ |
| D | extended.json | 3 "Unit": "CPU-M-CF",
7 …"PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle a DTLB…
10 "Unit": "CPU-M-CF",
14 …"PublicDescription": "Level-1 Instruction TLB miss in progress. Incremented by one for every cycle…
17 "Unit": "CPU-M-CF",
21 … directory write to the Level-1 Data cache directory where the returned cache line was sourced fro…
24 "Unit": "CPU-M-CF",
28 …ectory write to the Level-1 Instruction cache directory where the returned cache line was sourced …
31 "Unit": "CPU-M-CF",
35 … "A directory write to the Level-1 Data cache directory where the returned cache line was sourced …
[all …]
|
| D | basic.json | 3 "Unit": "CPU-M-CF",
10 "Unit": "CPU-M-CF",
17 "Unit": "CPU-M-CF",
20 "BriefDescription": "Level-1 I-Cache Directory Write Count",
21 …Description": "This counter counts the total number of level-1 instruction-cache or unified-cache …
24 "Unit": "CPU-M-CF",
27 "BriefDescription": "Level-1 I-Cache Penalty Cycle Count",
28 …: "This counter counts the total number of cache penalty cycles for level-1 instruction cache or u…
31 "Unit": "CPU-M-CF",
34 "BriefDescription": "Level-1 D-Cache Directory Write Count",
[all …]
|
| /Linux-v6.1/tools/perf/pmu-events/arch/s390/cf_z15/ |
| D | extended.json | 3 "Unit": "CPU-M-CF",
6 "BriefDescription": "L1D Read-only Exclusive Writes",
7 …Level-1 Data cache where the line was originally in a Read-Only state in the cache but has been up…
10 "Unit": "CPU-M-CF",
14 …ranslation Lookaside Buffer 2 (TLB2) and the request was made by the data cache. This is a replace…
17 "Unit": "CPU-M-CF",
21 …ss for a request made by the data cache. Incremented by one for every TLB2 miss in progress for th…
24 "Unit": "CPU-M-CF",
27 "BriefDescription": "DTLB2 One-Megabyte Page Writes",
28 …en into the Combined Region and Segment Table Entry array in the Level-2 TLB for a one-megabyte pa…
[all …]
|
| /Linux-v6.1/tools/perf/pmu-events/arch/s390/cf_z196/ |
| D | extended.json | 3 "Unit": "CPU-M-CF",
7 …n": "A directory write to the Level-1 Data Cache directory where the returned cache line was sourc…
10 "Unit": "CPU-M-CF",
14 …"A directory write to the Level-1 Instruction Cache directory where the returned cache line was so…
17 "Unit": "CPU-M-CF",
21 …"PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle a DTLB…
24 "Unit": "CPU-M-CF",
28 …"PublicDescription": "Level-1 Instruction TLB miss in progress. Incremented by one for every cycle…
31 "Unit": "CPU-M-CF",
35 "PublicDescription": "Incremented by one for every store sent to Level-2 cache."
[all …]
|
| D | basic.json | 3 "Unit": "CPU-M-CF",
10 "Unit": "CPU-M-CF",
17 "Unit": "CPU-M-CF",
20 "BriefDescription": "Level-1 I-Cache Directory Write Count",
21 …Description": "This counter counts the total number of level-1 instruction-cache or unified-cache …
24 "Unit": "CPU-M-CF",
27 "BriefDescription": "Level-1 I-Cache Penalty Cycle Count",
28 …: "This counter counts the total number of cache penalty cycles for level-1 instruction cache or u…
31 "Unit": "CPU-M-CF",
34 "BriefDescription": "Level-1 D-Cache Directory Write Count",
[all …]
|
| /Linux-v6.1/tools/perf/pmu-events/arch/s390/cf_z10/ |
| D | extended.json | 3 "Unit": "CPU-M-CF",
7 …directory write to the Level-1 Instruction Cache directory where the returned cache line was sourc…
10 "Unit": "CPU-M-CF",
14 …"A directory write to the Level-1 Data Cache directory where the installed cache line was sourced …
17 "Unit": "CPU-M-CF",
21 …Level-1 Instruction Cache directory where the installed cache line was sourced from the Level-3 ca…
24 "Unit": "CPU-M-CF",
28 …Level-1 Data Cache directory where the installed cache line was source from the Level-3 cache that…
31 "Unit": "CPU-M-CF",
35 …Level-1 Instruction Cache directory where the installed cache line was sourced from a Level-3 cach…
[all …]
|
| D | basic.json | 3 "Unit": "CPU-M-CF",
10 "Unit": "CPU-M-CF",
17 "Unit": "CPU-M-CF",
20 "BriefDescription": "Level-1 I-Cache Directory Write Count",
21 …Description": "This counter counts the total number of level-1 instruction-cache or unified-cache …
24 "Unit": "CPU-M-CF",
27 "BriefDescription": "Level-1 I-Cache Penalty Cycle Count",
28 …: "This counter counts the total number of cache penalty cycles for level-1 instruction cache or u…
31 "Unit": "CPU-M-CF",
34 "BriefDescription": "Level-1 D-Cache Directory Write Count",
[all …]
|
| /Linux-v6.1/arch/powerpc/kernel/ |
| D | cacheinfo.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Processor cache information made available to userspace via sysfs;
26 /* per-cpu object for tracking:
27 * - a "cache" kobject for the top-level directory
28 * - a list of "index" objects representing the cpu's local cache hierarchy
31 struct kobject *kobj; /* bare (not embedded) kobject for cache
36 /* "index" object: each cpu's cache directory has an index
37 * subdirectory corresponding to a cache object associated with the
43 struct cache *cache; member
47 * cache type */
[all …]
|
| /Linux-v6.1/tools/perf/pmu-events/arch/arm64/ |
| D | recommended.json | 3 "PublicDescription": "Attributable Level 1 data cache access, read",
6 "BriefDescription": "L1D cache access, read"
9 "PublicDescription": "Attributable Level 1 data cache access, write",
12 "BriefDescription": "L1D cache access, write"
15 "PublicDescription": "Attributable Level 1 data cache refill, read",
18 "BriefDescription": "L1D cache refill, read"
21 "PublicDescription": "Attributable Level 1 data cache refill, write",
24 "BriefDescription": "L1D cache refill, write"
27 "PublicDescription": "Attributable Level 1 data cache refill, inner",
30 "BriefDescription": "L1D cache refill, inner"
[all …]
|
| D | common-and-microarch.json | 9 "PublicDescription": "Level 1 instruction cache refill",
12 "BriefDescription": "Level 1 instruction cache refill"
15 "PublicDescription": "Attributable Level 1 instruction TLB refill",
18 "BriefDescription": "Attributable Level 1 instruction TLB refill"
21 "PublicDescription": "Level 1 data cache refill",
24 "BriefDescription": "Level 1 data cache refill"
27 "PublicDescription": "Level 1 data cache access",
30 "BriefDescription": "Level 1 data cache access"
33 "PublicDescription": "Attributable Level 1 data TLB refill",
36 "BriefDescription": "Attributable Level 1 data TLB refill"
[all …]
|
| /Linux-v6.1/Documentation/devicetree/bindings/arm/socionext/ |
| D | socionext,uniphier-system-cache.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/arm/socionext/socionext,uniphier-system-cache.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: UniPhier outer cache controller
10 UniPhier ARM 32-bit SoCs are integrated with a full-custom outer cache
11 controller system. All of them have a level 2 cache controller, and some
12 have a level 3 cache controller as well.
15 - Masahiro Yamada <yamada.masahiro@socionext.com>
19 const: socionext,uniphier-system-cache
[all …]
|
| /Linux-v6.1/arch/riscv/kernel/ |
| D | cacheinfo.c | 1 // SPDX-License-Identifier: GPL-2.0-only
22 if (rv_cache_ops && rv_cache_ops->get_priv_group) in cache_get_priv_group()
23 return rv_cache_ops->get_priv_group(this_leaf); in cache_get_priv_group()
27 static struct cacheinfo *get_cacheinfo(u32 level, enum cache_type type) in get_cacheinfo() argument
32 * that cores have a homonogenous view of the cache hierarchy. That in get_cacheinfo()
33 * happens to be the case for the current set of RISC-V systems, but in get_cacheinfo()
42 for (index = 0; index < this_cpu_ci->num_leaves; index++) { in get_cacheinfo()
43 this_leaf = this_cpu_ci->info_list + index; in get_cacheinfo()
44 if (this_leaf->level == level && this_leaf->type == type) in get_cacheinfo()
51 uintptr_t get_cache_size(u32 level, enum cache_type type) in get_cache_size() argument
[all …]
|
| /Linux-v6.1/Documentation/devicetree/bindings/cpufreq/ |
| D | cpufreq-qcom-hw.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/cpufreq/cpufreq-qcom-hw.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
21 - description: v1 of CPUFREQ HW
23 - const: qcom,cpufreq-hw
25 - description: v2 of CPUFREQ HW (EPSS)
27 - enum:
28 - qcom,sm6375-cpufreq-epss
[all …]
|
| /Linux-v6.1/arch/arm64/boot/dts/amazon/ |
| D | alpine-v3.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 compatible = "amazon,al-alpine-v3";
14 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
20 #address-cells = <1>;
21 #size-cells = <0>;
25 compatible = "arm,cortex-a72";
[all …]
|
| /Linux-v6.1/arch/powerpc/boot/dts/fsl/ |
| D | p4080si-pre.dtsi | 4 * Copyright 2011 - 2015 Freescale Semiconductor Inc.
35 /dts-v1/;
41 #address-cells = <2>;
42 #size-cells = <2>;
43 interrupt-parent = <&mpic>;
91 #address-cells = <1>;
92 #size-cells = <0>;
98 next-level-cache = <&L2_0>;
99 fsl,portid-mapping = <0x80000000>;
100 L2_0: l2-cache {
[all …]
|
| /Linux-v6.1/arch/arm64/boot/dts/ti/ |
| D | k3-am654.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/
8 #include "k3-am65.dtsi"
12 #address-cells = <1>;
13 #size-cells = <0>;
14 cpu-map {
37 compatible = "arm,cortex-a53";
40 enable-method = "psci";
41 i-cache-size = <0x8000>;
42 i-cache-line-size = <64>;
[all …]
|
| /Linux-v6.1/drivers/acpi/ |
| D | pptt.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * pptt.c - parsing of Processor Properties Topology Table (PPTT)
8 * which is optionally used to describe the processor and cache topology.
14 * the caches available at that level. Each cache structure optionally
15 * contains properties describing the cache at a given level which can be
33 if (pptt_ref + sizeof(struct acpi_subtable_header) > table_hdr->length) in fetch_pptt_subtable()
38 if (entry->length == 0) in fetch_pptt_subtable()
41 if (pptt_ref + entry->length > table_hdr->length) in fetch_pptt_subtable()
65 if (resource >= node->number_of_priv_resources) in acpi_get_pptt_resource()
81 * acpi_pptt_walk_cache() - Attempt to find the requested acpi_pptt_cache
[all …]
|
| /Linux-v6.1/Documentation/devicetree/bindings/riscv/ |
| D | sifive,ccache0.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: SiFive Composable Cache Controller
11 - Sagar Kadam <sagar.kadam@sifive.com>
12 - Paul Walmsley <paul.walmsley@sifive.com>
15 The SiFive Composable Cache Controller is used to provide access to fast copies
16 of memory for masters in a Core Complex. The Composable Cache Controller also
17 acts as directory-based coherency manager.
25 - sifive,ccache0
[all …]
|
