Lines Matching +full:cache +full:- +full:level
1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: SiFive Composable Cache Controller
11 - Sagar Kadam <sagar.kadam@sifive.com>
12 - Paul Walmsley <paul.walmsley@sifive.com>
15 The SiFive Composable Cache Controller is used to provide access to fast copies
16 of memory for masters in a Core Complex. The Composable Cache Controller also
17 acts as directory-based coherency manager.
25 - sifive,ccache0
26 - sifive,fu540-c000-ccache
27 - sifive,fu740-c000-ccache
30 - compatible
35 - items:
36 - enum:
37 - sifive,ccache0
38 - sifive,fu540-c000-ccache
39 - sifive,fu740-c000-ccache
40 - const: cache
41 - items:
42 - const: microchip,mpfs-ccache
43 - const: sifive,fu540-c000-ccache
44 - const: cache
46 cache-block-size:
49 cache-level:
52 cache-sets:
55 cache-size:
58 cache-unified: true
63 - description: DirError interrupt
64 - description: DataError interrupt
65 - description: DataFail interrupt
66 - description: DirFail interrupt
71 next-level-cache: true
73 memory-region:
76 The reference to the reserved-memory for the L2 Loosely Integrated Memory region.
77 The reserved memory node should be defined as per the bindings in reserved-memory.txt.
80 - $ref: /schemas/cache-controller.yaml#
82 - if:
87 - sifive,fu740-c000-ccache
88 - microchip,mpfs-ccache
104 - if:
108 const: sifive,fu740-c000-ccache
112 cache-sets:
117 cache-sets:
120 - if:
128 cache-level:
133 cache-level:
139 - compatible
140 - cache-block-size
141 - cache-level
142 - cache-sets
143 - cache-size
144 - cache-unified
145 - interrupts
146 - reg
149 - |
150 cache-controller@2010000 {
151 compatible = "sifive,fu540-c000-ccache", "cache";
152 cache-block-size = <64>;
153 cache-level = <2>;
154 cache-sets = <1024>;
155 cache-size = <2097152>;
156 cache-unified;
158 interrupt-parent = <&plic0>;
162 next-level-cache = <&L25>;
163 memory-region = <&l2_lim>;