Lines Matching +full:cache +full:- +full:level

1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/cpufreq/cpufreq-qcom-hw.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
21       - description: v1 of CPUFREQ HW
23           - const: qcom,cpufreq-hw
25       - description: v2 of CPUFREQ HW (EPSS)
27           - enum:
28               - qcom,sm6375-cpufreq-epss
29               - qcom,sm8250-cpufreq-epss
30           - const: qcom,cpufreq-epss
35       - description: Frequency domain 0 register region
36       - description: Frequency domain 1 register region
37       - description: Frequency domain 2 register region
39   reg-names:
42       - const: freq-domain0
43       - const: freq-domain1
44       - const: freq-domain2
48       - description: XO Clock
49       - description: GPLL0 Clock
51   clock-names:
53       - const: xo
54       - const: alternate
56   '#freq-domain-cells':
60   - compatible
61   - reg
62   - clocks
63   - clock-names
64   - '#freq-domain-cells'
69   - |
70     #include <dt-bindings/clock/qcom,gcc-sdm845.h>
71     #include <dt-bindings/clock/qcom,rpmh.h>
73     // Example 1: Dual-cluster, Quad-core per cluster. CPUs within a cluster
76       #address-cells = <2>;
77       #size-cells = <0>;
83         enable-method = "psci";
84         next-level-cache = <&L2_0>;
85         qcom,freq-domain = <&cpufreq_hw 0>;
86         L2_0: l2-cache {
87           compatible = "cache";
88           next-level-cache = <&L3_0>;
89           L3_0: l3-cache {
90             compatible = "cache";
99         enable-method = "psci";
100         next-level-cache = <&L2_100>;
101         qcom,freq-domain = <&cpufreq_hw 0>;
102         L2_100: l2-cache {
103           compatible = "cache";
104           next-level-cache = <&L3_0>;
112         enable-method = "psci";
113         next-level-cache = <&L2_200>;
114         qcom,freq-domain = <&cpufreq_hw 0>;
115         L2_200: l2-cache {
116           compatible = "cache";
117           next-level-cache = <&L3_0>;
125         enable-method = "psci";
126         next-level-cache = <&L2_300>;
127         qcom,freq-domain = <&cpufreq_hw 0>;
128         L2_300: l2-cache {
129           compatible = "cache";
130           next-level-cache = <&L3_0>;
138         enable-method = "psci";
139         next-level-cache = <&L2_400>;
140         qcom,freq-domain = <&cpufreq_hw 1>;
141         L2_400: l2-cache {
142           compatible = "cache";
143           next-level-cache = <&L3_0>;
151         enable-method = "psci";
152         next-level-cache = <&L2_500>;
153         qcom,freq-domain = <&cpufreq_hw 1>;
154         L2_500: l2-cache {
155           compatible = "cache";
156           next-level-cache = <&L3_0>;
164         enable-method = "psci";
165         next-level-cache = <&L2_600>;
166         qcom,freq-domain = <&cpufreq_hw 1>;
167         L2_600: l2-cache {
168           compatible = "cache";
169           next-level-cache = <&L3_0>;
177         enable-method = "psci";
178         next-level-cache = <&L2_700>;
179         qcom,freq-domain = <&cpufreq_hw 1>;
180         L2_700: l2-cache {
181           compatible = "cache";
182           next-level-cache = <&L3_0>;
188       #address-cells = <1>;
189       #size-cells = <1>;
192         compatible = "qcom,cpufreq-hw";
194         reg-names = "freq-domain0", "freq-domain1";
197         clock-names = "xo", "alternate";
199         #freq-domain-cells = <1>;