Lines Matching +full:cache +full:- +full:level
4 * Copyright 2011 - 2015 Freescale Semiconductor Inc.
35 /dts-v1/;
41 #address-cells = <2>;
42 #size-cells = <2>;
43 interrupt-parent = <&mpic>;
91 #address-cells = <1>;
92 #size-cells = <0>;
98 next-level-cache = <&L2_0>;
99 fsl,portid-mapping = <0x80000000>;
100 L2_0: l2-cache {
101 next-level-cache = <&cpc>;
108 next-level-cache = <&L2_1>;
109 fsl,portid-mapping = <0x40000000>;
110 L2_1: l2-cache {
111 next-level-cache = <&cpc>;
118 next-level-cache = <&L2_2>;
119 fsl,portid-mapping = <0x20000000>;
120 L2_2: l2-cache {
121 next-level-cache = <&cpc>;
128 next-level-cache = <&L2_3>;
129 fsl,portid-mapping = <0x10000000>;
130 L2_3: l2-cache {
131 next-level-cache = <&cpc>;
138 next-level-cache = <&L2_4>;
139 fsl,portid-mapping = <0x08000000>;
140 L2_4: l2-cache {
141 next-level-cache = <&cpc>;
148 next-level-cache = <&L2_5>;
149 fsl,portid-mapping = <0x04000000>;
150 L2_5: l2-cache {
151 next-level-cache = <&cpc>;
158 next-level-cache = <&L2_6>;
159 fsl,portid-mapping = <0x02000000>;
160 L2_6: l2-cache {
161 next-level-cache = <&cpc>;
168 next-level-cache = <&L2_7>;
169 fsl,portid-mapping = <0x01000000>;
170 L2_7: l2-cache {
171 next-level-cache = <&cpc>;