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/Linux-v6.1/drivers/net/ethernet/microchip/sparx5/
Dsparx5_mactable.c2 /* Microchip Sparx5 Switch driver
44 static int sparx5_mact_get_status(struct sparx5 *sparx5) in sparx5_mact_get_status() argument
46 return spx5_rd(sparx5, LRN_COMMON_ACCESS_CTRL); in sparx5_mact_get_status()
49 static int sparx5_mact_wait_for_completion(struct sparx5 *sparx5) in sparx5_mact_wait_for_completion() argument
54 sparx5, val, in sparx5_mact_wait_for_completion()
59 static void sparx5_mact_select(struct sparx5 *sparx5, in sparx5_mact_select() argument
76 spx5_wr(mach, sparx5, LRN_MAC_ACCESS_CFG_0); in sparx5_mact_select()
77 spx5_wr(macl, sparx5, LRN_MAC_ACCESS_CFG_1); in sparx5_mact_select()
80 int sparx5_mact_learn(struct sparx5 *sparx5, int pgid, in sparx5_mact_learn() argument
94 mutex_lock(&sparx5->lock); in sparx5_mact_learn()
[all …]
Dsparx5_ptp.c2 /* Microchip Sparx5 Switch driver
6 * The Sparx5 Chip Register Model can be browsed at this location:
27 static u64 sparx5_ptp_get_1ppm(struct sparx5 *sparx5) in sparx5_ptp_get_1ppm() argument
37 switch (sparx5->coreclock) { in sparx5_ptp_get_1ppm()
55 static u64 sparx5_ptp_get_nominal_value(struct sparx5 *sparx5) in sparx5_ptp_get_nominal_value() argument
59 switch (sparx5->coreclock) { in sparx5_ptp_get_nominal_value()
79 struct sparx5 *sparx5 = port->sparx5; in sparx5_ptp_hwtstamp_set() local
88 if (test_bit(port->portno, sparx5->bridge_mask)) in sparx5_ptp_hwtstamp_set()
132 mutex_lock(&sparx5->ptp_lock); in sparx5_ptp_hwtstamp_set()
133 phc = &sparx5->phc[SPARX5_PHC_PORT]; in sparx5_ptp_hwtstamp_set()
[all …]
Dsparx5_main.c2 /* Microchip Sparx5 Switch driver
6 * The Sparx5 Chip Register Model can be browsed at this location:
214 static int sparx5_create_targets(struct sparx5 *sparx5) in sparx5_create_targets() argument
231 iores[idx] = platform_get_resource(sparx5->pdev, IORESOURCE_MEM, in sparx5_create_targets()
234 dev_err(sparx5->dev, "Invalid resource\n"); in sparx5_create_targets()
237 iomem[idx] = devm_ioremap(sparx5->dev, in sparx5_create_targets()
241 dev_err(sparx5->dev, "Unable to get switch registers: %s\n", in sparx5_create_targets()
250 sparx5->regs[iomap->id] = begin[iomap->range] + iomap->offset; in sparx5_create_targets()
255 static int sparx5_create_port(struct sparx5 *sparx5, in sparx5_create_port() argument
263 ndev = sparx5_create_netdev(sparx5, config->portno); in sparx5_create_port()
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Dsparx5_vlan.c2 /* Microchip Sparx5 Switch driver
10 static int sparx5_vlant_set_mask(struct sparx5 *sparx5, u16 vid) in sparx5_vlant_set_mask() argument
15 bitmap_to_arr32(mask, sparx5->vlan_mask[vid], SPX5_PORTS); in sparx5_vlant_set_mask()
18 spx5_wr(mask[0], sparx5, ANA_L3_VLAN_MASK_CFG(vid)); in sparx5_vlant_set_mask()
19 spx5_wr(mask[1], sparx5, ANA_L3_VLAN_MASK_CFG1(vid)); in sparx5_vlant_set_mask()
20 spx5_wr(mask[2], sparx5, ANA_L3_VLAN_MASK_CFG2(vid)); in sparx5_vlant_set_mask()
25 void sparx5_vlan_init(struct sparx5 *sparx5) in sparx5_vlan_init() argument
31 sparx5, in sparx5_vlan_init()
38 sparx5, in sparx5_vlan_init()
42 void sparx5_vlan_port_setup(struct sparx5 *sparx5, int portno) in sparx5_vlan_port_setup() argument
[all …]
Dsparx5_qos.c2 /* Microchip Sparx5 Switch driver
22 static u32 sparx5_lg_get_leak_time(struct sparx5 *sparx5, u32 layer, u32 group) in sparx5_lg_get_leak_time() argument
26 value = spx5_rd(sparx5, HSCH_HSCH_TIMER_CFG(layer, group)); in sparx5_lg_get_leak_time()
30 static void sparx5_lg_set_leak_time(struct sparx5 *sparx5, u32 layer, u32 group, in sparx5_lg_set_leak_time() argument
33 spx5_wr(HSCH_HSCH_TIMER_CFG_LEAK_TIME_SET(leak_time), sparx5, in sparx5_lg_set_leak_time()
37 static u32 sparx5_lg_get_first(struct sparx5 *sparx5, u32 layer, u32 group) in sparx5_lg_get_first() argument
41 value = spx5_rd(sparx5, HSCH_HSCH_LEAK_CFG(layer, group)); in sparx5_lg_get_first()
45 static u32 sparx5_lg_get_next(struct sparx5 *sparx5, u32 layer, u32 group, in sparx5_lg_get_next() argument
51 value = spx5_rd(sparx5, HSCH_SE_CONNECT(idx)); in sparx5_lg_get_next()
55 static u32 sparx5_lg_get_last(struct sparx5 *sparx5, u32 layer, u32 group) in sparx5_lg_get_last() argument
[all …]
Dsparx5_fdma.c2 /* Microchip Sparx5 Switch driver
6 * The Sparx5 Chip Register Model can be browsed at this location:
113 static void sparx5_fdma_rx_activate(struct sparx5 *sparx5, struct sparx5_rx *rx) in sparx5_fdma_rx_activate() argument
116 spx5_wr(((u64)rx->dma) & GENMASK(31, 0), sparx5, in sparx5_fdma_rx_activate()
118 spx5_wr(((u64)rx->dma) >> 32, sparx5, FDMA_DCB_LLP1(rx->channel_id)); in sparx5_fdma_rx_activate()
124 sparx5, FDMA_CH_CFG(rx->channel_id)); in sparx5_fdma_rx_activate()
128 sparx5, in sparx5_fdma_rx_activate()
133 sparx5, FDMA_PORT_CTRL(0)); in sparx5_fdma_rx_activate()
138 sparx5, FDMA_INTR_DB_ENA); in sparx5_fdma_rx_activate()
141 spx5_wr(BIT(rx->channel_id), sparx5, FDMA_CH_ACTIVATE); in sparx5_fdma_rx_activate()
[all …]
Dsparx5_main.h2 /* Microchip Sparx5 Switch driver
99 struct sparx5;
168 struct sparx5 *sparx5; member
207 struct sparx5 *sparx5; member
232 struct sparx5 { struct
296 int sparx5_register_notifier_blocks(struct sparx5 *sparx5); argument
297 void sparx5_unregister_notifier_blocks(struct sparx5 *sparx5);
305 void sparx5_xtr_flush(struct sparx5 *sparx5, u8 grp);
309 int sparx5_manual_injection_mode(struct sparx5 *sparx5);
313 int sparx5_fdma_start(struct sparx5 *sparx5);
[all …]
Dsparx5_switchdev.c2 /* Microchip Sparx5 Switch driver
19 struct sparx5 *sparx5; member
58 struct sparx5 *sparx5 = port->sparx5; in sparx5_attr_stp_state_set() local
60 if (!test_bit(port->portno, sparx5->bridge_mask)) { in sparx5_attr_stp_state_set()
68 set_bit(port->portno, sparx5->bridge_fwd_mask); in sparx5_attr_stp_state_set()
71 set_bit(port->portno, sparx5->bridge_lrn_mask); in sparx5_attr_stp_state_set()
76 clear_bit(port->portno, sparx5->bridge_fwd_mask); in sparx5_attr_stp_state_set()
77 clear_bit(port->portno, sparx5->bridge_lrn_mask); in sparx5_attr_stp_state_set()
82 sparx5_update_fwd(sparx5); in sparx5_attr_stp_state_set()
91 sparx5_set_ageing(port->sparx5, ageing_time); in sparx5_port_attr_ageing_set()
[all …]
Dsparx5_port.c2 /* Microchip Sparx5 Switch driver
77 static int sparx5_get_dev2g5_status(struct sparx5 *sparx5, in sparx5_get_dev2g5_status() argument
86 value = spx5_rd(sparx5, DEV2G5_PCS1G_STICKY(portno)); in sparx5_get_dev2g5_status()
89 spx5_wr(value, sparx5, DEV2G5_PCS1G_STICKY(portno)); in sparx5_get_dev2g5_status()
92 value = spx5_rd(sparx5, DEV2G5_PCS1G_LINK_STATUS(portno)); in sparx5_get_dev2g5_status()
104 value = spx5_rd(sparx5, DEV2G5_PCS1G_ANEG_STATUS(portno)); in sparx5_get_dev2g5_status()
112 value = spx5_rd(sparx5, DEV2G5_PCS1G_ANEG_CFG(portno)); in sparx5_get_dev2g5_status()
120 static int sparx5_get_sfi_status(struct sparx5 *sparx5, in sparx5_get_sfi_status() argument
136 inst = spx5_inst_get(sparx5, dev, tinst); in sparx5_get_sfi_status()
159 int sparx5_get_port_status(struct sparx5 *sparx5, in sparx5_get_port_status() argument
[all …]
Dsparx5_ethtool.c2 /* Microchip Sparx5 Switch driver
201 static void sparx5_get_queue_sys_stats(struct sparx5 *sparx5, int portno) in sparx5_get_queue_sys_stats() argument
208 portstats = &sparx5->stats[portno * sparx5->num_stats]; in sparx5_get_queue_sys_stats()
209 mutex_lock(&sparx5->queue_stats_lock); in sparx5_get_queue_sys_stats()
210 spx5_wr(XQS_STAT_CFG_STAT_VIEW_SET(portno), sparx5, XQS_STAT_CFG); in sparx5_get_queue_sys_stats()
214 sparx5_update_counter(stats, spx5_rd(sparx5, XQS_CNT(addr))); in sparx5_get_queue_sys_stats()
218 sparx5_update_counter(stats, spx5_rd(sparx5, XQS_CNT(addr))); in sparx5_get_queue_sys_stats()
222 sparx5_update_counter(stats, spx5_rd(sparx5, XQS_CNT(addr))); in sparx5_get_queue_sys_stats()
224 spx5_rd(sparx5, XQS_CNT(32))); in sparx5_get_queue_sys_stats()
226 spx5_rd(sparx5, XQS_CNT(272))); in sparx5_get_queue_sys_stats()
[all …]
Dsparx5_packet.c2 /* Microchip Sparx5 Switch driver
23 void sparx5_xtr_flush(struct sparx5 *sparx5, u8 grp) in sparx5_xtr_flush() argument
26 spx5_wr(QS_XTR_FLUSH_FLUSH_SET(BIT(grp)), sparx5, QS_XTR_FLUSH); in sparx5_xtr_flush()
32 spx5_wr(0, sparx5, QS_XTR_FLUSH); in sparx5_xtr_flush()
55 static void sparx5_xtr_grp(struct sparx5 *sparx5, u8 grp, bool byte_swap) in sparx5_xtr_grp() argument
68 ifh[i] = spx5_rd(sparx5, QS_XTR_RD(grp)); in sparx5_xtr_grp()
75 sparx5->ports[fi.src_port] : NULL; in sparx5_xtr_grp()
77 dev_err(sparx5->dev, "Data on inactive port %d\n", fi.src_port); in sparx5_xtr_grp()
78 sparx5_xtr_flush(sparx5, grp); in sparx5_xtr_grp()
86 sparx5_xtr_flush(sparx5, grp); in sparx5_xtr_grp()
[all …]
Dsparx5_netdev.c2 /* Microchip Sparx5 Switch driver
116 err = sparx5_serdes_set(port->sparx5, port, &port->conf); in sparx5_port_open()
149 err = sparx5_serdes_set(port->sparx5, port, &port->conf); in sparx5_port_stop()
161 struct sparx5 *sparx5 = port->sparx5; in sparx5_set_rx_mode() local
163 if (!test_bit(port->portno, sparx5->bridge_mask)) in sparx5_set_rx_mode()
183 struct sparx5 *sparx5 = port->sparx5; in sparx5_set_mac_address() local
190 sparx5_mact_forget(sparx5, dev->dev_addr, port->pvid); in sparx5_set_mac_address()
193 sparx5_mact_learn(sparx5, PGID_CPU, addr->sa_data, port->pvid); in sparx5_set_mac_address()
205 struct sparx5 *sparx5 = sparx5_port->sparx5; in sparx5_get_port_parent_id() local
207 ppid->id_len = sizeof(sparx5->base_mac); in sparx5_get_port_parent_id()
[all …]
Dsparx5_calendar.c2 /* Microchip Sparx5 Switch driver
53 static u32 sparx5_target_bandwidth(struct sparx5 *sparx5) in sparx5_target_bandwidth() argument
55 switch (sparx5->target_ct) { in sparx5_target_bandwidth()
129 static enum sparx5_cal_bw sparx5_get_port_cal_speed(struct sparx5 *sparx5, in sparx5_get_port_cal_speed() argument
153 port = sparx5->ports[portno]; in sparx5_get_port_cal_speed()
160 int sparx5_config_auto_calendar(struct sparx5 *sparx5) in sparx5_config_auto_calendar() argument
170 max_core_bw = sparx5_clk_to_bandwidth(sparx5->coreclock); in sparx5_config_auto_calendar()
172 dev_err(sparx5->dev, "Core clock not supported"); in sparx5_config_auto_calendar()
180 spd = sparx5_get_port_cal_speed(sparx5, portno); in sparx5_config_auto_calendar()
196 if (used_port_bw > sparx5_target_bandwidth(sparx5)) { in sparx5_config_auto_calendar()
[all …]
Dsparx5_port.h2 /* Microchip Sparx5 Switch driver
62 int sparx5_port_init(struct sparx5 *sparx5,
66 int sparx5_port_config(struct sparx5 *sparx5,
70 int sparx5_port_pcs_set(struct sparx5 *sparx5,
74 int sparx5_serdes_set(struct sparx5 *sparx5,
87 int sparx5_get_port_status(struct sparx5 *sparx5,
92 int sparx5_port_fwd_urg(struct sparx5 *sparx5, u32 speed);
DMakefile3 # Makefile for the Microchip Sparx5 network device drivers.
6 obj-$(CONFIG_SPARX5_SWITCH) += sparx5-switch.o
8 sparx5-switch-objs := sparx5_main.o sparx5_packet.o \
/Linux-v6.1/Documentation/devicetree/bindings/arm/
Dmicrochip,sparx5.yaml4 $id: http://devicetree.org/schemas/arm/microchip,sparx5.yaml#
7 title: Microchip Sparx5 Boards
13 The Microchip Sparx5 SoC is a ARMv8-based used in a family of
27 - description: The Sparx5 pcb125 board is a modular board,
31 - const: microchip,sparx5-pcb125
32 - const: microchip,sparx5
34 - description: The Sparx5 pcb134 is a pizzabox form factor
38 - const: microchip,sparx5-pcb134
39 - const: microchip,sparx5
41 - description: The Sparx5 pcb135 is a pizzabox form factor
[all …]
/Linux-v6.1/arch/arm64/boot/dts/microchip/
Dsparx5.dtsi8 #include <dt-bindings/clock/microchip,sparx5.h>
11 compatible = "microchip,sparx5";
84 compatible = "microchip,sparx5-dpll";
123 compatible = "microchip,sparx5-cpu-syscon", "syscon",
139 compatible = "microchip,sparx5-switch-reset";
175 compatible = "microchip,sparx5-spi";
194 compatible = "microchip,dw-sparx5-sdhci";
208 compatible = "microchip,sparx5-pinctrl";
301 compatible = "microchip,sparx5-sgpio";
310 compatible = "microchip,sparx5-sgpio-bank";
[all …]
Dsparx5_pcb134.dts11 model = "Sparx5 PCB134 Reference Board (NAND)";
12 compatible = "microchip,sparx5-pcb134", "microchip,sparx5";
Dsparx5_pcb135.dts11 model = "Sparx5 PCB135 Reference Board (NAND)";
12 compatible = "microchip,sparx5-pcb135", "microchip,sparx5";
/Linux-v6.1/Documentation/devicetree/bindings/hwmon/
Dmicrochip,sparx5-temp.yaml4 $id: http://devicetree.org/schemas/hwmon/microchip,sparx5-temp.yaml#
7 title: Microchip Sparx5 Temperature Monitor
13 Microchip Sparx5 embedded temperature monitor
18 - microchip,sparx5-temp
40 compatible = "microchip,sparx5-temp";
/Linux-v6.1/Documentation/devicetree/bindings/clock/
Dmicrochip,sparx5-dpll.yaml4 $id: http://devicetree.org/schemas/clock/microchip,sparx5-dpll.yaml#
7 title: Microchip Sparx5 DPLL Clock
13 The Sparx5 DPLL clock controller generates and supplies clock to
18 const: microchip,sparx5-dpll
46 compatible = "microchip,sparx5-dpll";
/Linux-v6.1/Documentation/devicetree/bindings/mmc/
Dmicrochip,dw-sparx5-sdhci.yaml4 $id: http://devicetree.org/schemas/mmc/microchip,dw-sparx5-sdhci.yaml#
7 title: Microchip Sparx5 Mobile Storage Host Controller Binding
18 const: microchip,dw-sparx5-sdhci
54 #include <dt-bindings/clock/microchip,sparx5.h>
56 compatible = "microchip,dw-sparx5-sdhci";
/Linux-v6.1/Documentation/devicetree/bindings/pinctrl/
Dmicrochip,sparx5-sgpio.yaml4 $id: http://devicetree.org/schemas/pinctrl/microchip,sparx5-sgpio.yaml#
25 - microchip,sparx5-sgpio
83 const: microchip,sparx5-sgpio-bank
144 compatible = "microchip,sparx5-sgpio";
153 compatible = "microchip,sparx5-sgpio-bank";
162 compatible = "microchip,sparx5-sgpio-bank";
/Linux-v6.1/Documentation/devicetree/bindings/reset/
Dmicrochip,rst.yaml7 title: Microchip Sparx5 Switch Reset Controller
14 The Microchip Sparx5 Switch provides reset control and implements the following
24 - microchip,sparx5-switch-reset
54 compatible = "microchip,sparx5-switch-reset";
/Linux-v6.1/Documentation/devicetree/bindings/phy/
Dmicrochip,sparx5-serdes.yaml4 $id: http://devicetree.org/schemas/phy/microchip,sparx5-serdes.yaml#
7 title: Microchip Sparx5 Serdes controller
13 The Sparx5 SERDES interfaces share the same basic functionality, but
70 const: microchip,sparx5-serdes
94 compatible = "microchip,sparx5-serdes";

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