Lines Matching full:sparx5
2 /* Microchip Sparx5 Switch driver
6 * The Sparx5 Chip Register Model can be browsed at this location:
113 static void sparx5_fdma_rx_activate(struct sparx5 *sparx5, struct sparx5_rx *rx) in sparx5_fdma_rx_activate() argument
116 spx5_wr(((u64)rx->dma) & GENMASK(31, 0), sparx5, in sparx5_fdma_rx_activate()
118 spx5_wr(((u64)rx->dma) >> 32, sparx5, FDMA_DCB_LLP1(rx->channel_id)); in sparx5_fdma_rx_activate()
124 sparx5, FDMA_CH_CFG(rx->channel_id)); in sparx5_fdma_rx_activate()
128 sparx5, in sparx5_fdma_rx_activate()
133 sparx5, FDMA_PORT_CTRL(0)); in sparx5_fdma_rx_activate()
138 sparx5, FDMA_INTR_DB_ENA); in sparx5_fdma_rx_activate()
141 spx5_wr(BIT(rx->channel_id), sparx5, FDMA_CH_ACTIVATE); in sparx5_fdma_rx_activate()
144 static void sparx5_fdma_rx_deactivate(struct sparx5 *sparx5, struct sparx5_rx *rx) in sparx5_fdma_rx_deactivate() argument
148 sparx5, FDMA_CH_ACTIVATE); in sparx5_fdma_rx_deactivate()
152 sparx5, FDMA_INTR_DB_ENA); in sparx5_fdma_rx_deactivate()
156 sparx5, FDMA_PORT_CTRL(0)); in sparx5_fdma_rx_deactivate()
159 static void sparx5_fdma_tx_activate(struct sparx5 *sparx5, struct sparx5_tx *tx) in sparx5_fdma_tx_activate() argument
162 spx5_wr(((u64)tx->dma) & GENMASK(31, 0), sparx5, in sparx5_fdma_tx_activate()
164 spx5_wr(((u64)tx->dma) >> 32, sparx5, FDMA_DCB_LLP1(tx->channel_id)); in sparx5_fdma_tx_activate()
170 sparx5, FDMA_CH_CFG(tx->channel_id)); in sparx5_fdma_tx_activate()
174 sparx5, FDMA_PORT_CTRL(0)); in sparx5_fdma_tx_activate()
177 spx5_wr(BIT(tx->channel_id), sparx5, FDMA_CH_ACTIVATE); in sparx5_fdma_tx_activate()
180 static void sparx5_fdma_tx_deactivate(struct sparx5 *sparx5, struct sparx5_tx *tx) in sparx5_fdma_tx_deactivate() argument
184 sparx5, FDMA_CH_ACTIVATE); in sparx5_fdma_tx_deactivate()
187 static void sparx5_fdma_rx_reload(struct sparx5 *sparx5, struct sparx5_rx *rx) in sparx5_fdma_rx_reload() argument
190 spx5_wr(BIT(rx->channel_id), sparx5, FDMA_CH_RELOAD); in sparx5_fdma_rx_reload()
193 static void sparx5_fdma_tx_reload(struct sparx5 *sparx5, struct sparx5_tx *tx) in sparx5_fdma_tx_reload() argument
196 spx5_wr(BIT(tx->channel_id), sparx5, FDMA_CH_RELOAD); in sparx5_fdma_tx_reload()
205 static bool sparx5_fdma_rx_get_frame(struct sparx5 *sparx5, struct sparx5_rx *rx) in sparx5_fdma_rx_get_frame() argument
233 port = fi.src_port < SPX5_PORTS ? sparx5->ports[fi.src_port] : NULL; in sparx5_fdma_rx_get_frame()
235 dev_err(sparx5->dev, "Data on inactive port %d\n", fi.src_port); in sparx5_fdma_rx_get_frame()
236 sparx5_xtr_flush(sparx5, XTR_QUEUE); in sparx5_fdma_rx_get_frame()
244 sparx5_ptp_rxtstamp(sparx5, skb, fi.timestamp); in sparx5_fdma_rx_get_frame()
249 if (test_bit(port->portno, sparx5->bridge_mask)) in sparx5_fdma_rx_get_frame()
261 struct sparx5 *sparx5 = container_of(rx, struct sparx5, rx); in sparx5_fdma_napi_callback() local
264 while (counter < weight && sparx5_fdma_rx_get_frame(sparx5, rx)) { in sparx5_fdma_napi_callback()
288 sparx5, FDMA_INTR_DB_ENA); in sparx5_fdma_napi_callback()
291 sparx5_fdma_rx_reload(sparx5, rx); in sparx5_fdma_napi_callback()
309 int sparx5_fdma_xmit(struct sparx5 *sparx5, u32 *ifh, struct sk_buff *skb) in sparx5_fdma_xmit() argument
312 struct sparx5_tx *tx = &sparx5->tx; in sparx5_fdma_xmit()
336 sparx5_fdma_tx_activate(sparx5, tx); in sparx5_fdma_xmit()
339 sparx5_fdma_tx_reload(sparx5, tx); in sparx5_fdma_xmit()
344 static int sparx5_fdma_rx_alloc(struct sparx5 *sparx5) in sparx5_fdma_rx_alloc() argument
346 struct sparx5_rx *rx = &sparx5->rx; in sparx5_fdma_rx_alloc()
353 rx->dcb_entries = devm_kzalloc(sparx5->dev, size, GFP_KERNEL); in sparx5_fdma_rx_alloc()
387 sparx5_fdma_rx_activate(sparx5, rx); in sparx5_fdma_rx_alloc()
391 static int sparx5_fdma_tx_alloc(struct sparx5 *sparx5) in sparx5_fdma_tx_alloc() argument
393 struct sparx5_tx *tx = &sparx5->tx; in sparx5_fdma_tx_alloc()
400 tx->curr_entry = devm_kzalloc(sparx5->dev, size, GFP_KERNEL); in sparx5_fdma_tx_alloc()
417 cpu_addr = devm_kzalloc(sparx5->dev, in sparx5_fdma_tx_alloc()
425 db = devm_kzalloc(sparx5->dev, sizeof(*db), GFP_KERNEL); in sparx5_fdma_tx_alloc()
439 static void sparx5_fdma_rx_init(struct sparx5 *sparx5, in sparx5_fdma_rx_init() argument
447 struct sparx5_port *port = sparx5->ports[idx]; in sparx5_fdma_rx_init()
456 static void sparx5_fdma_tx_init(struct sparx5 *sparx5, in sparx5_fdma_tx_init() argument
464 struct sparx5 *sparx5 = args; in sparx5_fdma_handler() local
467 db = spx5_rd(sparx5, FDMA_INTR_DB); in sparx5_fdma_handler()
468 err = spx5_rd(sparx5, FDMA_INTR_ERR); in sparx5_fdma_handler()
471 spx5_wr(0, sparx5, FDMA_INTR_DB_ENA); in sparx5_fdma_handler()
472 spx5_wr(db, sparx5, FDMA_INTR_DB); in sparx5_fdma_handler()
473 napi_schedule(&sparx5->rx.napi); in sparx5_fdma_handler()
476 u32 err_type = spx5_rd(sparx5, FDMA_ERRORS); in sparx5_fdma_handler()
478 dev_err_ratelimited(sparx5->dev, in sparx5_fdma_handler()
481 spx5_wr(err, sparx5, FDMA_INTR_ERR); in sparx5_fdma_handler()
482 spx5_wr(err_type, sparx5, FDMA_ERRORS); in sparx5_fdma_handler()
487 static void sparx5_fdma_injection_mode(struct sparx5 *sparx5) in sparx5_fdma_injection_mode() argument
497 sparx5, QS_XTR_GRP_CFG(XTR_QUEUE)); in sparx5_fdma_injection_mode()
500 sparx5, QS_INJ_GRP_CFG(INJ_QUEUE)); in sparx5_fdma_injection_mode()
508 sparx5, ASM_PORT_CFG(portno)); in sparx5_fdma_injection_mode()
513 sparx5, in sparx5_fdma_injection_mode()
519 sparx5, in sparx5_fdma_injection_mode()
523 urgency = sparx5_port_fwd_urg(sparx5, SPEED_2500); in sparx5_fdma_injection_mode()
528 sparx5, in sparx5_fdma_injection_mode()
536 sparx5, in sparx5_fdma_injection_mode()
542 sparx5, in sparx5_fdma_injection_mode()
547 int sparx5_fdma_start(struct sparx5 *sparx5) in sparx5_fdma_start() argument
552 spx5_wr(FDMA_CTRL_NRESET_SET(0), sparx5, FDMA_CTRL); in sparx5_fdma_start()
553 spx5_wr(FDMA_CTRL_NRESET_SET(1), sparx5, FDMA_CTRL); in sparx5_fdma_start()
562 sparx5, CPU_PROC_CTRL); in sparx5_fdma_start()
564 sparx5_fdma_injection_mode(sparx5); in sparx5_fdma_start()
565 sparx5_fdma_rx_init(sparx5, &sparx5->rx, FDMA_XTR_CHANNEL); in sparx5_fdma_start()
566 sparx5_fdma_tx_init(sparx5, &sparx5->tx, FDMA_INJ_CHANNEL); in sparx5_fdma_start()
567 err = sparx5_fdma_rx_alloc(sparx5); in sparx5_fdma_start()
569 dev_err(sparx5->dev, "Could not allocate RX buffers: %d\n", err); in sparx5_fdma_start()
572 err = sparx5_fdma_tx_alloc(sparx5); in sparx5_fdma_start()
574 dev_err(sparx5->dev, "Could not allocate TX buffers: %d\n", err); in sparx5_fdma_start()
580 static u32 sparx5_fdma_port_ctrl(struct sparx5 *sparx5) in sparx5_fdma_port_ctrl() argument
582 return spx5_rd(sparx5, FDMA_PORT_CTRL(0)); in sparx5_fdma_port_ctrl()
585 int sparx5_fdma_stop(struct sparx5 *sparx5) in sparx5_fdma_stop() argument
589 napi_disable(&sparx5->rx.napi); in sparx5_fdma_stop()
591 sparx5_fdma_rx_deactivate(sparx5, &sparx5->rx); in sparx5_fdma_stop()
592 sparx5_fdma_tx_deactivate(sparx5, &sparx5->tx); in sparx5_fdma_stop()
596 500, 10000, 0, sparx5); in sparx5_fdma_stop()