2 /* Microchip Sparx5 Switch driver
23 void sparx5_xtr_flush(struct sparx5 *sparx5, u8 grp)  in sparx5_xtr_flush()  argument
26 	spx5_wr(QS_XTR_FLUSH_FLUSH_SET(BIT(grp)), sparx5, QS_XTR_FLUSH);  in sparx5_xtr_flush()
32 	spx5_wr(0, sparx5, QS_XTR_FLUSH);  in sparx5_xtr_flush()
55 static void sparx5_xtr_grp(struct sparx5 *sparx5, u8 grp, bool byte_swap)  in sparx5_xtr_grp()  argument
68 		ifh[i] = spx5_rd(sparx5, QS_XTR_RD(grp));  in sparx5_xtr_grp()
75 		sparx5->ports[fi.src_port] : NULL;  in sparx5_xtr_grp()
77 		dev_err(sparx5->dev, "Data on inactive port %d\n", fi.src_port);  in sparx5_xtr_grp()
78 		sparx5_xtr_flush(sparx5, grp);  in sparx5_xtr_grp()
86 		sparx5_xtr_flush(sparx5, grp);  in sparx5_xtr_grp()
87 		dev_err(sparx5->dev, "No skb allocated\n");  in sparx5_xtr_grp()
95 		u32 val = spx5_rd(sparx5, QS_XTR_RD(grp));  in sparx5_xtr_grp()
127 			*rxbuf = spx5_rd(sparx5, QS_XTR_RD(grp));  in sparx5_xtr_grp()
149 	if (test_bit(port->portno, sparx5->bridge_mask))  in sparx5_xtr_grp()
155 	sparx5_ptp_rxtstamp(sparx5, skb, fi.timestamp);  in sparx5_xtr_grp()
162 static int sparx5_inject(struct sparx5 *sparx5,  in sparx5_inject()  argument
171 	val = spx5_rd(sparx5, QS_INJ_STATUS);  in sparx5_inject()
181 		sparx5, QS_INJ_CTRL(grp));  in sparx5_inject()
185 		spx5_wr(ifh[w], sparx5, QS_INJ_WR(grp));  in sparx5_inject()
192 		spx5_wr(val, sparx5, QS_INJ_WR(grp));  in sparx5_inject()
197 		spx5_wr(0, sparx5, QS_INJ_WR(grp));  in sparx5_inject()
205 		sparx5, QS_INJ_CTRL(grp));  in sparx5_inject()
208 	spx5_wr(0, sparx5, QS_INJ_WR(grp));  in sparx5_inject()
211 	val = spx5_rd(sparx5, QS_INJ_STATUS);  in sparx5_inject()
229 	struct sparx5 *sparx5 = port->sparx5;  in sparx5_port_xmit_impl()  local
236 	if (sparx5->ptp && skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) {  in sparx5_port_xmit_impl()
247 	if (sparx5->fdma_irq > 0)  in sparx5_port_xmit_impl()
248 		ret = sparx5_fdma_xmit(sparx5, ifh, skb);  in sparx5_port_xmit_impl()
250 		ret = sparx5_inject(sparx5, ifh, skb, dev);  in sparx5_port_xmit_impl()
259 	sparx5->tx.packets++;  in sparx5_port_xmit_impl()
269 	sparx5->tx.dropped++;  in sparx5_port_xmit_impl()
286 	val = spx5_rd(port->sparx5, QS_INJ_STATUS);  in sparx5_injection_timeout()
292 			 port->sparx5,  in sparx5_injection_timeout()
299 int sparx5_manual_injection_mode(struct sparx5 *sparx5)  in sparx5_manual_injection_mode()  argument
308 		sparx5, QS_XTR_GRP_CFG(XTR_QUEUE));  in sparx5_manual_injection_mode()
311 		sparx5, QS_INJ_GRP_CFG(INJ_QUEUE));  in sparx5_manual_injection_mode()
319 			sparx5, ASM_PORT_CFG(portno));  in sparx5_manual_injection_mode()
324 			 sparx5,  in sparx5_manual_injection_mode()
330 			 sparx5,  in sparx5_manual_injection_mode()
337 			 sparx5,  in sparx5_manual_injection_mode()
345 	struct sparx5 *s5 = _sparx5;  in sparx5_xtr_handler()