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/Linux-v5.15/drivers/pci/controller/dwc/
Dpcie-tegra194.c3 * PCIe host controller driver for Tegra194 SoC
33 #include "pcie-designware.h"
301 static inline void appl_writel(struct tegra_pcie_dw *pcie, const u32 value, in appl_writel() argument
304 writel_relaxed(value, pcie->appl_base + reg); in appl_writel()
307 static inline u32 appl_readl(struct tegra_pcie_dw *pcie, const u32 reg) in appl_readl() argument
309 return readl_relaxed(pcie->appl_base + reg); in appl_readl()
319 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci); in apply_bad_link_workaround() local
328 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA); in apply_bad_link_workaround()
332 if (pcie->init_link_width > current_link_width) { in apply_bad_link_workaround()
333 dev_warn(pci->dev, "PCIe link is bad, width reduced\n"); in apply_bad_link_workaround()
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Dpcie-visconti.c3 * DWC PCIe RC driver for Toshiba Visconti ARM SoC
24 #include "pcie-designware.h"
96 /* Access registers in PCIe ulreg */
97 static void visconti_ulreg_writel(struct visconti_pcie *pcie, u32 val, u32 reg) in visconti_ulreg_writel() argument
99 writel_relaxed(val, pcie->ulreg_base + reg); in visconti_ulreg_writel()
102 static u32 visconti_ulreg_readl(struct visconti_pcie *pcie, u32 reg) in visconti_ulreg_readl() argument
104 return readl_relaxed(pcie->ulreg_base + reg); in visconti_ulreg_readl()
107 /* Access registers in PCIe smu */
108 static void visconti_smu_writel(struct visconti_pcie *pcie, u32 val, u32 reg) in visconti_smu_writel() argument
110 writel_relaxed(val, pcie->smu_base + reg); in visconti_smu_writel()
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DKconfig23 bool "TI DRA7xx PCIe controller Host Mode"
31 Enables support for the PCIe controller in the DRA7xx SoC to work in
32 host mode. There are two instances of PCIe controller in DRA7xx.
39 bool "TI DRA7xx PCIe controller Endpoint Mode"
46 Enables support for the PCIe controller in the DRA7xx SoC to work in
47 endpoint mode. There are two instances of PCIe controller in DRA7xx.
57 bool "Platform bus based DesignWare PCIe Controller - Host mode"
62 Enables support for the PCIe controller in the Designware IP to
63 work in host mode. There are two instances of PCIe controller in
71 bool "Platform bus based DesignWare PCIe Controller - Endpoint mode"
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Dpcie-keembay.c3 * PCIe controller driver for Intel Keem Bay
22 #include "pcie-designware.h"
72 static void keembay_ep_reset_assert(struct keembay_pcie *pcie) in keembay_ep_reset_assert() argument
74 gpiod_set_value_cansleep(pcie->reset, 1); in keembay_ep_reset_assert()
78 static void keembay_ep_reset_deassert(struct keembay_pcie *pcie) in keembay_ep_reset_deassert() argument
88 gpiod_set_value_cansleep(pcie->reset, 0); in keembay_ep_reset_deassert()
92 static void keembay_pcie_ltssm_set(struct keembay_pcie *pcie, bool enable) in keembay_pcie_ltssm_set() argument
96 val = readl(pcie->apb_base + PCIE_REGS_PCIE_APP_CNTRL); in keembay_pcie_ltssm_set()
101 writel(val, pcie->apb_base + PCIE_REGS_PCIE_APP_CNTRL); in keembay_pcie_ltssm_set()
106 struct keembay_pcie *pcie = dev_get_drvdata(pci->dev); in keembay_pcie_link_up() local
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Dpci-layerscape.c3 * PCIe host controller driver for Freescale Layerscape SoCs
23 #include "pcie-designware.h"
56 static bool ls_pcie_is_bridge(struct ls_pcie *pcie) in ls_pcie_is_bridge() argument
58 struct dw_pcie *pci = pcie->pci; in ls_pcie_is_bridge()
68 static void ls_pcie_clear_multifunction(struct ls_pcie *pcie) in ls_pcie_clear_multifunction() argument
70 struct dw_pcie *pci = pcie->pci; in ls_pcie_clear_multifunction()
76 static void ls_pcie_drop_msg_tlp(struct ls_pcie *pcie) in ls_pcie_drop_msg_tlp() argument
79 struct dw_pcie *pci = pcie->pci; in ls_pcie_drop_msg_tlp()
89 struct ls_pcie *pcie = to_ls_pcie(pci); in ls1021_pcie_link_up() local
91 if (!pcie->scfg) in ls1021_pcie_link_up()
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Dpcie-qcom.c3 * Qualcomm PCIe root complex driver
32 #include "pcie-designware.h"
183 int (*get_resources)(struct qcom_pcie *pcie);
184 int (*init)(struct qcom_pcie *pcie);
185 int (*post_init)(struct qcom_pcie *pcie);
186 void (*deinit)(struct qcom_pcie *pcie);
187 void (*post_deinit)(struct qcom_pcie *pcie);
188 void (*ltssm_enable)(struct qcom_pcie *pcie);
189 int (*config_sid)(struct qcom_pcie *pcie);
204 static void qcom_ep_reset_assert(struct qcom_pcie *pcie) in qcom_ep_reset_assert() argument
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Dpcie-armada8k.c3 * PCIe host controller driver for Marvell Armada-8K SoCs
5 * Armada-8K PCIe Glue Layer Source Code
26 #include "pcie-designware.h"
74 static void armada8k_pcie_disable_phys(struct armada8k_pcie *pcie) in armada8k_pcie_disable_phys() argument
79 phy_power_off(pcie->phy[i]); in armada8k_pcie_disable_phys()
80 phy_exit(pcie->phy[i]); in armada8k_pcie_disable_phys()
84 static int armada8k_pcie_enable_phys(struct armada8k_pcie *pcie) in armada8k_pcie_enable_phys() argument
90 ret = phy_init(pcie->phy[i]); in armada8k_pcie_enable_phys()
94 ret = phy_set_mode_ext(pcie->phy[i], PHY_MODE_PCIE, in armada8k_pcie_enable_phys()
95 pcie->phy_count); in armada8k_pcie_enable_phys()
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/Linux-v5.15/drivers/pci/controller/
Dpcie-altera.c6 * Description: Altera PCIe host controller driver
45 #define S10_RP_CFG_ADDR(pcie, reg) \ argument
46 (((pcie)->hip_base) + (reg) + (1 << 20))
47 #define S10_RP_SECONDARY(pcie) \ argument
48 readb(S10_RP_CFG_ADDR(pcie, PCI_SECONDARY_BUS))
60 #define TLP_CFG_DW0(pcie, cfg) \ argument
63 #define TLP_CFG_DW1(pcie, tag, be) \ argument
64 (((TLP_REQ_ID(pcie->root_bus_nr, RP_DEVFN)) << 16) | (tag << 8) | (be))
99 int (*tlp_read_pkt)(struct altera_pcie *pcie, u32 *value);
100 void (*tlp_write_pkt)(struct altera_pcie *pcie, u32 *headers,
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Dpci-aardvark.c3 * Driver for the Aardvark PCIe controller, used on Marvell Armada
31 /* PCIe core registers */
122 /* PCIe window configuration */
171 /* PCIe core controller registers */
179 /* PCIe Central Interrupts Registers */
250 static inline void advk_writel(struct advk_pcie *pcie, u32 val, u64 reg) in advk_writel() argument
252 writel(val, pcie->base + reg); in advk_writel()
255 static inline u32 advk_readl(struct advk_pcie *pcie, u64 reg) in advk_readl() argument
257 return readl(pcie->base + reg); in advk_readl()
260 static inline u16 advk_read16(struct advk_pcie *pcie, u64 reg) in advk_read16() argument
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Dpci-tegra.c3 * PCIe host controller driver for Tegra SoCs
8 * Based on NVIDIA PCIe driver
11 * Bits taken from arch/arm/mach-dove/pcie.c
257 * entries, one entry per PCIe port. These field definitions and desired
362 struct tegra_pcie *pcie; member
375 static inline void afi_writel(struct tegra_pcie *pcie, u32 value, in afi_writel() argument
378 writel(value, pcie->afi + offset); in afi_writel()
381 static inline u32 afi_readl(struct tegra_pcie *pcie, unsigned long offset) in afi_readl() argument
383 return readl(pcie->afi + offset); in afi_readl()
386 static inline void pads_writel(struct tegra_pcie *pcie, u32 value, in pads_writel() argument
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Dpcie-xilinx-nwl.c3 * PCIe host controller driver for NWL PCIe Bridge
4 * Based on pcie-xilinx.c, pci-tegra.c
162 phys_addr_t phys_pcie_reg_base; /* Physical PCIe Controller Base */
177 static inline u32 nwl_bridge_readl(struct nwl_pcie *pcie, u32 off) in nwl_bridge_readl() argument
179 return readl(pcie->breg_base + off); in nwl_bridge_readl()
182 static inline void nwl_bridge_writel(struct nwl_pcie *pcie, u32 val, u32 off) in nwl_bridge_writel() argument
184 writel(val, pcie->breg_base + off); in nwl_bridge_writel()
187 static bool nwl_pcie_link_up(struct nwl_pcie *pcie) in nwl_pcie_link_up() argument
189 if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PCIE_PHY_LINKUP_BIT) in nwl_pcie_link_up()
194 static bool nwl_phy_link_up(struct nwl_pcie *pcie) in nwl_phy_link_up() argument
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Dpcie-rcar-host.c3 * PCIe driver for Renesas R-Car SoCs
7 * arch/sh/drivers/pci/pcie-sh7786.c
35 #include "pcie-rcar.h"
48 * Here we keep a static copy of the remapped PCIe controller address.
50 * PCIe controller, to provide quick access to the PCIe controller in
61 /* Structure representing the PCIe interface */
63 struct rcar_pcie pcie; member
75 static u32 rcar_read_conf(struct rcar_pcie *pcie, int where) in rcar_read_conf() argument
78 u32 val = rcar_pci_read_reg(pcie, where & ~3); in rcar_read_conf()
88 struct rcar_pcie *pcie = &host->pcie; in rcar_pcie_config_access() local
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Dpcie-brcmstb.c38 /* Broadcom STB PCIe Register Offsets */
142 /* PCIe parameters */
173 #define IDX_ADDR(pcie) (pcie->reg_offsets[EXT_CFG_INDEX]) argument
174 #define DATA_ADDR(pcie) (pcie->reg_offsets[EXT_CFG_DATA]) argument
175 #define PCIE_RGR1_SW_INIT_1(pcie) (pcie->reg_offsets[RGR1_SW_INIT_1]) argument
189 static inline void brcm_pcie_bridge_sw_init_set_7278(struct brcm_pcie *pcie, u32 val);
190 static inline void brcm_pcie_bridge_sw_init_set_generic(struct brcm_pcie *pcie, u32 val);
191 static inline void brcm_pcie_perst_set_4908(struct brcm_pcie *pcie, u32 val);
192 static inline void brcm_pcie_perst_set_7278(struct brcm_pcie *pcie, u32 val);
193 static inline void brcm_pcie_perst_set_generic(struct brcm_pcie *pcie, u32 val);
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Dpcie-iproc.c25 #include "pcie-iproc.h"
92 * struct iproc_pcie_ob_map - iProc PCIe outbound mapping controller-specific
139 * enum iproc_pcie_ib_map_type - iProc PCIe inbound mapping type
151 * struct iproc_pcie_ib_map - iProc PCIe inbound mapping controller-specific
230 * iProc PCIe host registers
307 /* iProc PCIe PAXB BCMA registers */
318 /* iProc PCIe PAXB registers */
334 /* iProc PCIe PAXB v2 registers */
365 /* iProc PCIe PAXC v1 registers */
374 /* iProc PCIe PAXC v2 registers */
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Dpcie-rcar-ep.c3 * PCIe endpoint driver for Renesas R-Car SoCs
20 #include "pcie-rcar.h"
24 /* Structure representing the PCIe interface */
26 struct rcar_pcie pcie; member
36 static void rcar_pcie_ep_hw_init(struct rcar_pcie *pcie) in rcar_pcie_ep_hw_init() argument
40 rcar_pci_write_reg(pcie, 0, PCIETCTLR); in rcar_pcie_ep_hw_init()
43 rcar_pci_write_reg(pcie, 0, PCIEMSR); in rcar_pcie_ep_hw_init()
46 rcar_rmw32(pcie, REXPCAP(0), 0xff, PCI_CAP_ID_EXP); in rcar_pcie_ep_hw_init()
47 rcar_rmw32(pcie, REXPCAP(PCI_EXP_FLAGS), in rcar_pcie_ep_hw_init()
49 rcar_rmw32(pcie, RCONF(PCI_HEADER_TYPE), 0x7f, in rcar_pcie_ep_hw_init()
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Dpcie-iproc-platform.c20 #include "pcie-iproc.h"
24 .compatible = "brcm,iproc-pcie",
27 .compatible = "brcm,iproc-pcie-paxb-v2",
30 .compatible = "brcm,iproc-pcie-paxc",
33 .compatible = "brcm,iproc-pcie-paxc-v2",
43 struct iproc_pcie *pcie; in iproc_pcie_pltfm_probe() local
49 bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie)); in iproc_pcie_pltfm_probe()
53 pcie = pci_host_bridge_priv(bridge); in iproc_pcie_pltfm_probe()
55 pcie->dev = dev; in iproc_pcie_pltfm_probe()
56 pcie->type = (enum iproc_pcie_type) of_device_get_match_data(dev); in iproc_pcie_pltfm_probe()
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DKconfig7 bool "Marvell EBU PCIe controller"
15 tristate "Aardvark PCIe controller"
21 Add support for Aardvark 64bit PCIe Host Controller. This
26 bool "NWL PCIe Core"
31 NWL PCIe controller. The controller can act as Root Port
50 bool "NVIDIA Tegra PCIe controller"
54 Say Y here if you want support for the PCIe host controller found
67 bool "Renesas R-Car PCIe host controller"
71 Say Y here if you want PCIe controller support on R-Car SoCs in host
75 bool "Renesas R-Car PCIe endpoint controller"
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/Linux-v5.15/drivers/pci/controller/mobiveil/
Dpcie-mobiveil-host.c3 * PCIe host controller driver for Mobiveil PCIe Host controller
28 #include "pcie-mobiveil.h"
53 struct mobiveil_pcie *pcie = bus->sysdata; in mobiveil_pcie_map_bus() local
54 struct mobiveil_root_port *rp = &pcie->rp; in mobiveil_pcie_map_bus()
62 return pcie->csr_axi_slave_base + where; in mobiveil_pcie_map_bus()
74 mobiveil_csr_writel(pcie, value, PAB_AXI_AMAP_PEX_WIN_L(WIN_NUM_0)); in mobiveil_pcie_map_bus()
88 struct mobiveil_pcie *pcie = irq_desc_get_handler_data(desc); in mobiveil_pcie_isr() local
89 struct device *dev = &pcie->pdev->dev; in mobiveil_pcie_isr()
90 struct mobiveil_root_port *rp = &pcie->rp; in mobiveil_pcie_isr()
105 val = mobiveil_csr_readl(pcie, PAB_INTP_AMBA_MISC_STAT); in mobiveil_pcie_isr()
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Dpcie-mobiveil.c3 * PCIe host controller driver for Mobiveil PCIe Host controller
18 #include "pcie-mobiveil.h"
28 static void mobiveil_pcie_sel_page(struct mobiveil_pcie *pcie, u8 pg_idx) in mobiveil_pcie_sel_page() argument
32 val = readl(pcie->csr_axi_slave_base + PAB_CTRL); in mobiveil_pcie_sel_page()
36 writel(val, pcie->csr_axi_slave_base + PAB_CTRL); in mobiveil_pcie_sel_page()
39 static void __iomem *mobiveil_pcie_comp_addr(struct mobiveil_pcie *pcie, in mobiveil_pcie_comp_addr() argument
44 mobiveil_pcie_sel_page(pcie, 0); in mobiveil_pcie_comp_addr()
45 return pcie->csr_axi_slave_base + off; in mobiveil_pcie_comp_addr()
48 mobiveil_pcie_sel_page(pcie, OFFSET_TO_PAGE_IDX(off)); in mobiveil_pcie_comp_addr()
49 return pcie->csr_axi_slave_base + OFFSET_TO_PAGE_ADDR(off); in mobiveil_pcie_comp_addr()
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Dpcie-layerscape-gen4.c3 * PCIe Gen4 host controller driver for NXP Layerscape SoCs
23 #include "pcie-mobiveil.h"
45 static inline u32 ls_pcie_g4_pf_readl(struct ls_pcie_g4 *pcie, u32 off) in ls_pcie_g4_pf_readl() argument
47 return ioread32(pcie->pci.csr_axi_slave_base + PCIE_PF_OFF + off); in ls_pcie_g4_pf_readl()
50 static inline void ls_pcie_g4_pf_writel(struct ls_pcie_g4 *pcie, in ls_pcie_g4_pf_writel() argument
53 iowrite32(val, pcie->pci.csr_axi_slave_base + PCIE_PF_OFF + off); in ls_pcie_g4_pf_writel()
58 struct ls_pcie_g4 *pcie = to_ls_pcie_g4(pci); in ls_pcie_g4_link_up() local
61 state = ls_pcie_g4_pf_readl(pcie, PCIE_PF_DBG); in ls_pcie_g4_link_up()
70 static void ls_pcie_g4_disable_interrupt(struct ls_pcie_g4 *pcie) in ls_pcie_g4_disable_interrupt() argument
72 struct mobiveil_pcie *mv_pci = &pcie->pci; in ls_pcie_g4_disable_interrupt()
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/Linux-v5.15/drivers/staging/mt7621-pci/
Dpci-mt7621.c12 * support RT2880/RT3883 PCIe
15 * support RT6855/MT7620 PCIe
46 /* PCIe RC control registers */
64 * struct mt7621_pcie_port - PCIe port information
67 * @pcie: pointer to PCIe host info
78 struct mt7621_pcie *pcie; member
88 * struct mt7621_pcie - PCIe host information
90 * @dev: Pointer to PCIe device
91 * @ports: pointer to PCIe port information
102 static inline u32 pcie_read(struct mt7621_pcie *pcie, u32 reg) in pcie_read() argument
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/Linux-v5.15/drivers/pci/controller/cadence/
Dpcie-cadence.c3 // Cadence PCIe controller driver.
8 #include "pcie-cadence.h"
10 void cdns_pcie_detect_quiet_min_delay_set(struct cdns_pcie *pcie) in cdns_pcie_detect_quiet_min_delay_set() argument
18 ltssm_control_cap = cdns_pcie_readl(pcie, CDNS_PCIE_LTSSM_CONTROL_CAP); in cdns_pcie_detect_quiet_min_delay_set()
23 cdns_pcie_writel(pcie, CDNS_PCIE_LTSSM_CONTROL_CAP, ltssm_control_cap); in cdns_pcie_detect_quiet_min_delay_set()
26 void cdns_pcie_set_outbound_region(struct cdns_pcie *pcie, u8 busnr, u8 fn, in cdns_pcie_set_outbound_region() argument
46 cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_PCI_ADDR0(r), addr0); in cdns_pcie_set_outbound_region()
47 cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_PCI_ADDR1(r), addr1); in cdns_pcie_set_outbound_region()
49 /* Set the PCIe header descriptor */ in cdns_pcie_set_outbound_region()
58 * PCIe descriptor, the PCI function number must be set into in cdns_pcie_set_outbound_region()
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Dpcie-cadence-ep.c3 // Cadence PCIe endpoint controller driver.
13 #include "pcie-cadence.h"
19 static u8 cdns_pcie_get_fn_from_vfn(struct cdns_pcie *pcie, u8 fn, u8 vfn) in cdns_pcie_get_fn_from_vfn() argument
27 first_vf_offset = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_SRIOV_VF_OFFSET); in cdns_pcie_get_fn_from_vfn()
28 stride = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_SRIOV_VF_STRIDE); in cdns_pcie_get_fn_from_vfn()
39 struct cdns_pcie *pcie = &ep->pcie; in cdns_pcie_ep_write_header() local
47 cdns_pcie_ep_fn_writew(pcie, fn, reg, hdr->deviceid); in cdns_pcie_ep_write_header()
51 cdns_pcie_ep_fn_writew(pcie, fn, PCI_DEVICE_ID, hdr->deviceid); in cdns_pcie_ep_write_header()
52 cdns_pcie_ep_fn_writeb(pcie, fn, PCI_REVISION_ID, hdr->revid); in cdns_pcie_ep_write_header()
53 cdns_pcie_ep_fn_writeb(pcie, fn, PCI_CLASS_PROG, hdr->progif_code); in cdns_pcie_ep_write_header()
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Dpci-j721e.c3 * pci-j721e - PCIe controller driver for TI's J721E SoCs
24 #include "pcie-cadence.h"
77 static inline u32 j721e_pcie_user_readl(struct j721e_pcie *pcie, u32 offset) in j721e_pcie_user_readl() argument
79 return readl(pcie->user_cfg_base + offset); in j721e_pcie_user_readl()
82 static inline void j721e_pcie_user_writel(struct j721e_pcie *pcie, u32 offset, in j721e_pcie_user_writel() argument
85 writel(value, pcie->user_cfg_base + offset); in j721e_pcie_user_writel()
88 static inline u32 j721e_pcie_intd_readl(struct j721e_pcie *pcie, u32 offset) in j721e_pcie_intd_readl() argument
90 return readl(pcie->intd_cfg_base + offset); in j721e_pcie_intd_readl()
93 static inline void j721e_pcie_intd_writel(struct j721e_pcie *pcie, u32 offset, in j721e_pcie_intd_writel() argument
96 writel(value, pcie->intd_cfg_base + offset); in j721e_pcie_intd_writel()
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/Linux-v5.15/Documentation/devicetree/bindings/pci/
Dlayerscape-pci.txt1 Freescale Layerscape PCIe controller
3 This PCIe host controller is based on the Synopsys DesignWare PCIe IP
4 and thus inherits all the common properties defined in snps,dw-pcie.yaml.
10 register available in the Freescale PCIe controller register set,
11 which can allow determining the underlying DesignWare PCIe controller version
17 "fsl,ls1021a-pcie"
18 "fsl,ls2080a-pcie", "fsl,ls2085a-pcie"
19 "fsl,ls2088a-pcie"
20 "fsl,ls1088a-pcie"
21 "fsl,ls1046a-pcie"
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