Lines Matching full:pcie
38 /* Broadcom STB PCIe Register Offsets */
142 /* PCIe parameters */
173 #define IDX_ADDR(pcie) (pcie->reg_offsets[EXT_CFG_INDEX]) argument
174 #define DATA_ADDR(pcie) (pcie->reg_offsets[EXT_CFG_DATA]) argument
175 #define PCIE_RGR1_SW_INIT_1(pcie) (pcie->reg_offsets[RGR1_SW_INIT_1]) argument
189 static inline void brcm_pcie_bridge_sw_init_set_7278(struct brcm_pcie *pcie, u32 val);
190 static inline void brcm_pcie_bridge_sw_init_set_generic(struct brcm_pcie *pcie, u32 val);
191 static inline void brcm_pcie_perst_set_4908(struct brcm_pcie *pcie, u32 val);
192 static inline void brcm_pcie_perst_set_7278(struct brcm_pcie *pcie, u32 val);
193 static inline void brcm_pcie_perst_set_generic(struct brcm_pcie *pcie, u32 val);
216 void (*perst_set)(struct brcm_pcie *pcie, u32 val);
217 void (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val);
279 /* Internal PCIe Host Controller Information.*/
296 void (*perst_set)(struct brcm_pcie *pcie, u32 val);
297 void (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val);
374 static int brcm_pcie_set_ssc(struct brcm_pcie *pcie) in brcm_pcie_set_ssc() argument
380 ret = brcm_pcie_mdio_write(pcie->base, MDIO_PORT0, SET_ADDR_OFFSET, in brcm_pcie_set_ssc()
385 ret = brcm_pcie_mdio_read(pcie->base, MDIO_PORT0, in brcm_pcie_set_ssc()
392 ret = brcm_pcie_mdio_write(pcie->base, MDIO_PORT0, in brcm_pcie_set_ssc()
398 ret = brcm_pcie_mdio_read(pcie->base, MDIO_PORT0, in brcm_pcie_set_ssc()
410 static void brcm_pcie_set_gen(struct brcm_pcie *pcie, int gen) in brcm_pcie_set_gen() argument
412 u16 lnkctl2 = readw(pcie->base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCTL2); in brcm_pcie_set_gen()
413 u32 lnkcap = readl(pcie->base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCAP); in brcm_pcie_set_gen()
416 writel(lnkcap, pcie->base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCAP); in brcm_pcie_set_gen()
419 writew(lnkctl2, pcie->base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCTL2); in brcm_pcie_set_gen()
422 static void brcm_pcie_set_outbound_win(struct brcm_pcie *pcie, in brcm_pcie_set_outbound_win() argument
432 writel(lower_32_bits(pcie_addr), pcie->base + PCIE_MEM_WIN0_LO(win)); in brcm_pcie_set_outbound_win()
433 writel(upper_32_bits(pcie_addr), pcie->base + PCIE_MEM_WIN0_HI(win)); in brcm_pcie_set_outbound_win()
439 tmp = readl(pcie->base + PCIE_MEM_WIN0_BASE_LIMIT(win)); in brcm_pcie_set_outbound_win()
444 writel(tmp, pcie->base + PCIE_MEM_WIN0_BASE_LIMIT(win)); in brcm_pcie_set_outbound_win()
451 tmp = readl(pcie->base + PCIE_MEM_WIN0_BASE_HI(win)); in brcm_pcie_set_outbound_win()
454 writel(tmp, pcie->base + PCIE_MEM_WIN0_BASE_HI(win)); in brcm_pcie_set_outbound_win()
457 tmp = readl(pcie->base + PCIE_MEM_WIN0_LIMIT_HI(win)); in brcm_pcie_set_outbound_win()
460 writel(tmp, pcie->base + PCIE_MEM_WIN0_LIMIT_HI(win)); in brcm_pcie_set_outbound_win()
464 .name = "BRCM STB PCIe MSI",
610 static void brcm_msi_remove(struct brcm_pcie *pcie) in brcm_msi_remove() argument
612 struct brcm_msi *msi = pcie->msi; in brcm_msi_remove()
640 static int brcm_pcie_enable_msi(struct brcm_pcie *pcie) in brcm_pcie_enable_msi() argument
644 struct device *dev = pcie->dev; in brcm_pcie_enable_msi()
658 msi->base = pcie->base; in brcm_pcie_enable_msi()
659 msi->np = pcie->np; in brcm_pcie_enable_msi()
660 msi->target_addr = pcie->msi_target_addr; in brcm_pcie_enable_msi()
662 msi->legacy = pcie->hw_rev < BRCM_PCIE_HW_REV_33; in brcm_pcie_enable_msi()
681 pcie->msi = msi; in brcm_pcie_enable_msi()
687 static bool brcm_pcie_rc_mode(struct brcm_pcie *pcie) in brcm_pcie_rc_mode() argument
689 void __iomem *base = pcie->base; in brcm_pcie_rc_mode()
695 static bool brcm_pcie_link_up(struct brcm_pcie *pcie) in brcm_pcie_link_up() argument
697 u32 val = readl(pcie->base + PCIE_MISC_PCIE_STATUS); in brcm_pcie_link_up()
707 struct brcm_pcie *pcie = bus->sysdata; in brcm_pcie_map_conf() local
708 void __iomem *base = pcie->base; in brcm_pcie_map_conf()
717 writel(idx, pcie->base + PCIE_EXT_CFG_INDEX); in brcm_pcie_map_conf()
727 static inline void brcm_pcie_bridge_sw_init_set_generic(struct brcm_pcie *pcie, u32 val) in brcm_pcie_bridge_sw_init_set_generic() argument
732 tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); in brcm_pcie_bridge_sw_init_set_generic()
734 writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); in brcm_pcie_bridge_sw_init_set_generic()
737 static inline void brcm_pcie_bridge_sw_init_set_7278(struct brcm_pcie *pcie, u32 val) in brcm_pcie_bridge_sw_init_set_7278() argument
742 tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); in brcm_pcie_bridge_sw_init_set_7278()
744 writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); in brcm_pcie_bridge_sw_init_set_7278()
747 static inline void brcm_pcie_perst_set_4908(struct brcm_pcie *pcie, u32 val) in brcm_pcie_perst_set_4908() argument
749 if (WARN_ONCE(!pcie->perst_reset, "missing PERST# reset controller\n")) in brcm_pcie_perst_set_4908()
753 reset_control_assert(pcie->perst_reset); in brcm_pcie_perst_set_4908()
755 reset_control_deassert(pcie->perst_reset); in brcm_pcie_perst_set_4908()
758 static inline void brcm_pcie_perst_set_7278(struct brcm_pcie *pcie, u32 val) in brcm_pcie_perst_set_7278() argument
763 tmp = readl(pcie->base + PCIE_MISC_PCIE_CTRL); in brcm_pcie_perst_set_7278()
765 writel(tmp, pcie->base + PCIE_MISC_PCIE_CTRL); in brcm_pcie_perst_set_7278()
768 static inline void brcm_pcie_perst_set_generic(struct brcm_pcie *pcie, u32 val) in brcm_pcie_perst_set_generic() argument
772 tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); in brcm_pcie_perst_set_generic()
774 writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); in brcm_pcie_perst_set_generic()
777 static inline int brcm_pcie_get_rc_bar2_size_and_offset(struct brcm_pcie *pcie, in brcm_pcie_get_rc_bar2_size_and_offset() argument
781 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie); in brcm_pcie_get_rc_bar2_size_and_offset()
783 struct device *dev = pcie->dev; in brcm_pcie_get_rc_bar2_size_and_offset()
801 ret = of_property_read_variable_u64_array(pcie->np, "brcm,scb-sizes", pcie->memc_size, 1, in brcm_pcie_get_rc_bar2_size_and_offset()
806 pcie->num_memc = 1; in brcm_pcie_get_rc_bar2_size_and_offset()
807 pcie->memc_size[0] = 1ULL << fls64(size - 1); in brcm_pcie_get_rc_bar2_size_and_offset()
809 pcie->num_memc = ret; in brcm_pcie_get_rc_bar2_size_and_offset()
813 for (i = 0, size = 0; i < pcie->num_memc; i++) in brcm_pcie_get_rc_bar2_size_and_offset()
814 size += pcie->memc_size[i]; in brcm_pcie_get_rc_bar2_size_and_offset()
816 /* System memory starts at this address in PCIe-space */ in brcm_pcie_get_rc_bar2_size_and_offset()
826 * PCIe controller integration, which prohibits any access above the in brcm_pcie_get_rc_bar2_size_and_offset()
831 * The PCIe host controller by design must set the inbound viewport to in brcm_pcie_get_rc_bar2_size_and_offset()
834 * matters, the viewport must start on a pcie-address that is aligned in brcm_pcie_get_rc_bar2_size_and_offset()
845 * region in the first 4GB of pcie-space, as some legacy devices can in brcm_pcie_get_rc_bar2_size_and_offset()
864 static int brcm_pcie_setup(struct brcm_pcie *pcie) in brcm_pcie_setup() argument
866 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie); in brcm_pcie_setup()
868 void __iomem *base = pcie->base; in brcm_pcie_setup()
869 struct device *dev = pcie->dev; in brcm_pcie_setup()
879 pcie->bridge_sw_init_set(pcie, 1); in brcm_pcie_setup()
883 pcie->bridge_sw_init_set(pcie, 0); in brcm_pcie_setup()
896 if (pcie->type == BCM2711) in brcm_pcie_setup()
898 else if (pcie->type == BCM7278) in brcm_pcie_setup()
910 ret = brcm_pcie_get_rc_bar2_size_and_offset(pcie, &rc_bar2_size, in brcm_pcie_setup()
923 for (memc = 0; memc < pcie->num_memc; memc++) { in brcm_pcie_setup()
924 u32 scb_size_val = ilog2(pcie->memc_size[memc]) - 15; in brcm_pcie_setup()
943 pcie->msi_target_addr = BRCM_MSI_TARGET_ADDR_LT_4GB; in brcm_pcie_setup()
945 pcie->msi_target_addr = BRCM_MSI_TARGET_ADDR_GT_4GB; in brcm_pcie_setup()
947 /* disable the PCIe->GISB memory window (RC_BAR1) */ in brcm_pcie_setup()
952 /* disable the PCIe->SCB memory window (RC_BAR3) */ in brcm_pcie_setup()
957 if (pcie->gen) in brcm_pcie_setup()
958 brcm_pcie_set_gen(pcie, pcie->gen); in brcm_pcie_setup()
961 pcie->perst_set(pcie, 0); in brcm_pcie_setup()
967 for (i = 0; i < 100 && !brcm_pcie_link_up(pcie); i += 5) in brcm_pcie_setup()
970 if (!brcm_pcie_link_up(pcie)) { in brcm_pcie_setup()
975 if (!brcm_pcie_rc_mode(pcie)) { in brcm_pcie_setup()
976 dev_err(dev, "PCIe misconfigured; is in EP mode\n"); in brcm_pcie_setup()
987 dev_err(pcie->dev, "too many outbound wins\n"); in brcm_pcie_setup()
991 brcm_pcie_set_outbound_win(pcie, num_out_wins, res->start, in brcm_pcie_setup()
999 if (!of_property_read_bool(pcie->np, "aspm-no-l0s")) in brcm_pcie_setup()
1008 * a PCIe-PCIe bridge (the default setting is to be EP mode). in brcm_pcie_setup()
1015 if (pcie->ssc) { in brcm_pcie_setup()
1016 ret = brcm_pcie_set_ssc(pcie); in brcm_pcie_setup()
1030 /* PCIe->SCB endian mode for BAR */ in brcm_pcie_setup()
1047 /* L23 is a low-power PCIe link state */
1048 static void brcm_pcie_enter_l23(struct brcm_pcie *pcie) in brcm_pcie_enter_l23() argument
1050 void __iomem *base = pcie->base; in brcm_pcie_enter_l23()
1070 dev_err(pcie->dev, "failed to enter low-power link state\n"); in brcm_pcie_enter_l23()
1073 static int brcm_phy_cntl(struct brcm_pcie *pcie, const int start) in brcm_phy_cntl() argument
1087 void __iomem *base = pcie->base; in brcm_phy_cntl()
1104 dev_err(pcie->dev, "failed to %s phy\n", (start ? "start" : "stop")); in brcm_phy_cntl()
1109 static inline int brcm_phy_start(struct brcm_pcie *pcie) in brcm_phy_start() argument
1111 return pcie->rescal ? brcm_phy_cntl(pcie, 1) : 0; in brcm_phy_start()
1114 static inline int brcm_phy_stop(struct brcm_pcie *pcie) in brcm_phy_stop() argument
1116 return pcie->rescal ? brcm_phy_cntl(pcie, 0) : 0; in brcm_phy_stop()
1119 static void brcm_pcie_turn_off(struct brcm_pcie *pcie) in brcm_pcie_turn_off() argument
1121 void __iomem *base = pcie->base; in brcm_pcie_turn_off()
1124 if (brcm_pcie_link_up(pcie)) in brcm_pcie_turn_off()
1125 brcm_pcie_enter_l23(pcie); in brcm_pcie_turn_off()
1127 pcie->perst_set(pcie, 1); in brcm_pcie_turn_off()
1139 /* Shutdown PCIe bridge */ in brcm_pcie_turn_off()
1140 pcie->bridge_sw_init_set(pcie, 1); in brcm_pcie_turn_off()
1145 struct brcm_pcie *pcie = dev_get_drvdata(dev); in brcm_pcie_suspend() local
1148 brcm_pcie_turn_off(pcie); in brcm_pcie_suspend()
1149 ret = brcm_phy_stop(pcie); in brcm_pcie_suspend()
1150 reset_control_rearm(pcie->rescal); in brcm_pcie_suspend()
1151 clk_disable_unprepare(pcie->clk); in brcm_pcie_suspend()
1158 struct brcm_pcie *pcie = dev_get_drvdata(dev); in brcm_pcie_resume() local
1163 base = pcie->base; in brcm_pcie_resume()
1164 clk_prepare_enable(pcie->clk); in brcm_pcie_resume()
1166 ret = reset_control_reset(pcie->rescal); in brcm_pcie_resume()
1170 ret = brcm_phy_start(pcie); in brcm_pcie_resume()
1175 pcie->bridge_sw_init_set(pcie, 0); in brcm_pcie_resume()
1185 ret = brcm_pcie_setup(pcie); in brcm_pcie_resume()
1189 if (pcie->msi) in brcm_pcie_resume()
1190 brcm_msi_set_regs(pcie->msi); in brcm_pcie_resume()
1195 reset_control_rearm(pcie->rescal); in brcm_pcie_resume()
1197 clk_disable_unprepare(pcie->clk); in brcm_pcie_resume()
1201 static void __brcm_pcie_remove(struct brcm_pcie *pcie) in __brcm_pcie_remove() argument
1203 brcm_msi_remove(pcie); in __brcm_pcie_remove()
1204 brcm_pcie_turn_off(pcie); in __brcm_pcie_remove()
1205 brcm_phy_stop(pcie); in __brcm_pcie_remove()
1206 reset_control_rearm(pcie->rescal); in __brcm_pcie_remove()
1207 clk_disable_unprepare(pcie->clk); in __brcm_pcie_remove()
1212 struct brcm_pcie *pcie = platform_get_drvdata(pdev); in brcm_pcie_remove() local
1213 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie); in brcm_pcie_remove()
1217 __brcm_pcie_remove(pcie); in brcm_pcie_remove()
1223 { .compatible = "brcm,bcm2711-pcie", .data = &bcm2711_cfg },
1224 { .compatible = "brcm,bcm4908-pcie", .data = &bcm4908_cfg },
1225 { .compatible = "brcm,bcm7211-pcie", .data = &generic_cfg },
1226 { .compatible = "brcm,bcm7278-pcie", .data = &bcm7278_cfg },
1227 { .compatible = "brcm,bcm7216-pcie", .data = &bcm7278_cfg },
1228 { .compatible = "brcm,bcm7445-pcie", .data = &generic_cfg },
1237 struct brcm_pcie *pcie; in brcm_pcie_probe() local
1240 bridge = devm_pci_alloc_host_bridge(&pdev->dev, sizeof(*pcie)); in brcm_pcie_probe()
1250 pcie = pci_host_bridge_priv(bridge); in brcm_pcie_probe()
1251 pcie->dev = &pdev->dev; in brcm_pcie_probe()
1252 pcie->np = np; in brcm_pcie_probe()
1253 pcie->reg_offsets = data->offsets; in brcm_pcie_probe()
1254 pcie->type = data->type; in brcm_pcie_probe()
1255 pcie->perst_set = data->perst_set; in brcm_pcie_probe()
1256 pcie->bridge_sw_init_set = data->bridge_sw_init_set; in brcm_pcie_probe()
1258 pcie->base = devm_platform_ioremap_resource(pdev, 0); in brcm_pcie_probe()
1259 if (IS_ERR(pcie->base)) in brcm_pcie_probe()
1260 return PTR_ERR(pcie->base); in brcm_pcie_probe()
1262 pcie->clk = devm_clk_get_optional(&pdev->dev, "sw_pcie"); in brcm_pcie_probe()
1263 if (IS_ERR(pcie->clk)) in brcm_pcie_probe()
1264 return PTR_ERR(pcie->clk); in brcm_pcie_probe()
1267 pcie->gen = (ret < 0) ? 0 : ret; in brcm_pcie_probe()
1269 pcie->ssc = of_property_read_bool(np, "brcm,enable-ssc"); in brcm_pcie_probe()
1271 ret = clk_prepare_enable(pcie->clk); in brcm_pcie_probe()
1276 pcie->rescal = devm_reset_control_get_optional_shared(&pdev->dev, "rescal"); in brcm_pcie_probe()
1277 if (IS_ERR(pcie->rescal)) { in brcm_pcie_probe()
1278 clk_disable_unprepare(pcie->clk); in brcm_pcie_probe()
1279 return PTR_ERR(pcie->rescal); in brcm_pcie_probe()
1281 pcie->perst_reset = devm_reset_control_get_optional_exclusive(&pdev->dev, "perst"); in brcm_pcie_probe()
1282 if (IS_ERR(pcie->perst_reset)) { in brcm_pcie_probe()
1283 clk_disable_unprepare(pcie->clk); in brcm_pcie_probe()
1284 return PTR_ERR(pcie->perst_reset); in brcm_pcie_probe()
1287 ret = reset_control_reset(pcie->rescal); in brcm_pcie_probe()
1291 ret = brcm_phy_start(pcie); in brcm_pcie_probe()
1293 reset_control_rearm(pcie->rescal); in brcm_pcie_probe()
1294 clk_disable_unprepare(pcie->clk); in brcm_pcie_probe()
1298 ret = brcm_pcie_setup(pcie); in brcm_pcie_probe()
1302 pcie->hw_rev = readl(pcie->base + PCIE_MISC_REVISION); in brcm_pcie_probe()
1303 if (pcie->type == BCM4908 && pcie->hw_rev >= BRCM_PCIE_HW_REV_3_20) { in brcm_pcie_probe()
1304 dev_err(pcie->dev, "hardware revision with unsupported PERST# setup\n"); in brcm_pcie_probe()
1309 msi_np = of_parse_phandle(pcie->np, "msi-parent", 0); in brcm_pcie_probe()
1310 if (pci_msi_enabled() && msi_np == pcie->np) { in brcm_pcie_probe()
1311 ret = brcm_pcie_enable_msi(pcie); in brcm_pcie_probe()
1313 dev_err(pcie->dev, "probe of internal MSI failed"); in brcm_pcie_probe()
1319 bridge->sysdata = pcie; in brcm_pcie_probe()
1321 platform_set_drvdata(pdev, pcie); in brcm_pcie_probe()
1325 __brcm_pcie_remove(pcie); in brcm_pcie_probe()
1340 .name = "brcm-pcie",
1348 MODULE_DESCRIPTION("Broadcom STB PCIe RC driver");