3  * PCIe host controller driver for NWL PCIe Bridge
4  * Based on pcie-xilinx.c, pci-tegra.c
162 	phys_addr_t phys_pcie_reg_base;	/* Physical PCIe Controller Base */
177 static inline u32 nwl_bridge_readl(struct nwl_pcie *pcie, u32 off)  in nwl_bridge_readl()  argument
179 	return readl(pcie->breg_base + off);  in nwl_bridge_readl()
182 static inline void nwl_bridge_writel(struct nwl_pcie *pcie, u32 val, u32 off)  in nwl_bridge_writel()  argument
184 	writel(val, pcie->breg_base + off);  in nwl_bridge_writel()
187 static bool nwl_pcie_link_up(struct nwl_pcie *pcie)  in nwl_pcie_link_up()  argument
189 	if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PCIE_PHY_LINKUP_BIT)  in nwl_pcie_link_up()
194 static bool nwl_phy_link_up(struct nwl_pcie *pcie)  in nwl_phy_link_up()  argument
196 	if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PHY_RDY_LINKUP_BIT)  in nwl_phy_link_up()
201 static int nwl_wait_for_link(struct nwl_pcie *pcie)  in nwl_wait_for_link()  argument
203 	struct device *dev = pcie->dev;  in nwl_wait_for_link()
208 		if (nwl_phy_link_up(pcie))  in nwl_wait_for_link()
219 	struct nwl_pcie *pcie = bus->sysdata;  in nwl_pcie_valid_device()  local
223 		if (!nwl_pcie_link_up(pcie))  in nwl_pcie_valid_device()
245 	struct nwl_pcie *pcie = bus->sysdata;  in nwl_pcie_map_bus()  local
250 	return pcie->ecam_base + PCIE_ECAM_OFFSET(bus->number, devfn, where);  in nwl_pcie_map_bus()
253 /* PCIe operations */
262 	struct nwl_pcie *pcie = data;  in nwl_pcie_misc_handler()  local
263 	struct device *dev = pcie->dev;  in nwl_pcie_misc_handler()
267 	misc_stat = nwl_bridge_readl(pcie, MSGF_MISC_STATUS) &  in nwl_pcie_misc_handler()
312 	nwl_bridge_writel(pcie, misc_stat, MSGF_MISC_STATUS);  in nwl_pcie_misc_handler()
320 	struct nwl_pcie *pcie;  in nwl_pcie_leg_handler()  local
325 	pcie = irq_desc_get_handler_data(desc);  in nwl_pcie_leg_handler()
327 	while ((status = nwl_bridge_readl(pcie, MSGF_LEG_STATUS) &  in nwl_pcie_leg_handler()
330 			generic_handle_domain_irq(pcie->legacy_irq_domain, bit);  in nwl_pcie_leg_handler()
336 static void nwl_pcie_handle_msi_irq(struct nwl_pcie *pcie, u32 status_reg)  in nwl_pcie_handle_msi_irq()  argument
342 	msi = &pcie->msi;  in nwl_pcie_handle_msi_irq()
344 	while ((status = nwl_bridge_readl(pcie, status_reg)) != 0) {  in nwl_pcie_handle_msi_irq()
346 			nwl_bridge_writel(pcie, 1 << bit, status_reg);  in nwl_pcie_handle_msi_irq()
355 	struct nwl_pcie *pcie = irq_desc_get_handler_data(desc);  in nwl_pcie_msi_handler_high()  local
358 	nwl_pcie_handle_msi_irq(pcie, MSGF_MSI_STATUS_HI);  in nwl_pcie_msi_handler_high()
365 	struct nwl_pcie *pcie = irq_desc_get_handler_data(desc);  in nwl_pcie_msi_handler_low()  local
368 	nwl_pcie_handle_msi_irq(pcie, MSGF_MSI_STATUS_LO);  in nwl_pcie_msi_handler_low()
374 	struct nwl_pcie *pcie = irq_data_get_irq_chip_data(data);  in nwl_mask_leg_irq()  local
380 	raw_spin_lock_irqsave(&pcie->leg_mask_lock, flags);  in nwl_mask_leg_irq()
381 	val = nwl_bridge_readl(pcie, MSGF_LEG_MASK);  in nwl_mask_leg_irq()
382 	nwl_bridge_writel(pcie, (val & (~mask)), MSGF_LEG_MASK);  in nwl_mask_leg_irq()
383 	raw_spin_unlock_irqrestore(&pcie->leg_mask_lock, flags);  in nwl_mask_leg_irq()
388 	struct nwl_pcie *pcie = irq_data_get_irq_chip_data(data);  in nwl_unmask_leg_irq()  local
394 	raw_spin_lock_irqsave(&pcie->leg_mask_lock, flags);  in nwl_unmask_leg_irq()
395 	val = nwl_bridge_readl(pcie, MSGF_LEG_MASK);  in nwl_unmask_leg_irq()
396 	nwl_bridge_writel(pcie, (val | mask), MSGF_LEG_MASK);  in nwl_unmask_leg_irq()
397 	raw_spin_unlock_irqrestore(&pcie->leg_mask_lock, flags);  in nwl_unmask_leg_irq()
441 	struct nwl_pcie *pcie = irq_data_get_irq_chip_data(data);  in nwl_compose_msi_msg()  local
442 	phys_addr_t msi_addr = pcie->phys_pcie_reg_base;  in nwl_compose_msi_msg()
464 	struct nwl_pcie *pcie = domain->host_data;  in nwl_irq_domain_alloc()  local
465 	struct nwl_msi *msi = &pcie->msi;  in nwl_irq_domain_alloc()
490 	struct nwl_pcie *pcie = irq_data_get_irq_chip_data(data);  in nwl_irq_domain_free()  local
491 	struct nwl_msi *msi = &pcie->msi;  in nwl_irq_domain_free()
504 static int nwl_pcie_init_msi_irq_domain(struct nwl_pcie *pcie)  in nwl_pcie_init_msi_irq_domain()  argument
507 	struct device *dev = pcie->dev;  in nwl_pcie_init_msi_irq_domain()
509 	struct nwl_msi *msi = &pcie->msi;  in nwl_pcie_init_msi_irq_domain()
512 						&dev_msi_domain_ops, pcie);  in nwl_pcie_init_msi_irq_domain()
529 static int nwl_pcie_init_irq_domain(struct nwl_pcie *pcie)  in nwl_pcie_init_irq_domain()  argument
531 	struct device *dev = pcie->dev;  in nwl_pcie_init_irq_domain()
541 	pcie->legacy_irq_domain = irq_domain_add_linear(legacy_intc_node,  in nwl_pcie_init_irq_domain()
544 							pcie);  in nwl_pcie_init_irq_domain()
546 	if (!pcie->legacy_irq_domain) {  in nwl_pcie_init_irq_domain()
551 	raw_spin_lock_init(&pcie->leg_mask_lock);  in nwl_pcie_init_irq_domain()
552 	nwl_pcie_init_msi_irq_domain(pcie);  in nwl_pcie_init_irq_domain()
556 static int nwl_pcie_enable_msi(struct nwl_pcie *pcie)  in nwl_pcie_enable_msi()  argument
558 	struct device *dev = pcie->dev;  in nwl_pcie_enable_msi()
560 	struct nwl_msi *msi = &pcie->msi;  in nwl_pcie_enable_msi()
579 					 nwl_pcie_msi_handler_high, pcie);  in nwl_pcie_enable_msi()
589 					 nwl_pcie_msi_handler_low, pcie);  in nwl_pcie_enable_msi()
592 	ret = nwl_bridge_readl(pcie, I_MSII_CAPABILITIES) & MSII_PRESENT;  in nwl_pcie_enable_msi()
600 	nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, I_MSII_CONTROL) |  in nwl_pcie_enable_msi()
604 	nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, I_MSII_CONTROL) |  in nwl_pcie_enable_msi()
608 	base = pcie->phys_pcie_reg_base;  in nwl_pcie_enable_msi()
609 	nwl_bridge_writel(pcie, lower_32_bits(base), I_MSII_BASE_LO);  in nwl_pcie_enable_msi()
610 	nwl_bridge_writel(pcie, upper_32_bits(base), I_MSII_BASE_HI);  in nwl_pcie_enable_msi()
616 	nwl_bridge_writel(pcie, 0, MSGF_MSI_MASK_HI);  in nwl_pcie_enable_msi()
618 	nwl_bridge_writel(pcie, nwl_bridge_readl(pcie,  MSGF_MSI_STATUS_HI) &  in nwl_pcie_enable_msi()
621 	nwl_bridge_writel(pcie, MSGF_MSI_SR_HI_MASK, MSGF_MSI_MASK_HI);  in nwl_pcie_enable_msi()
627 	nwl_bridge_writel(pcie, 0, MSGF_MSI_MASK_LO);  in nwl_pcie_enable_msi()
629 	nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MSI_STATUS_LO) &  in nwl_pcie_enable_msi()
632 	nwl_bridge_writel(pcie, MSGF_MSI_SR_LO_MASK, MSGF_MSI_MASK_LO);  in nwl_pcie_enable_msi()
641 static int nwl_pcie_bridge_init(struct nwl_pcie *pcie)  in nwl_pcie_bridge_init()  argument
643 	struct device *dev = pcie->dev;  in nwl_pcie_bridge_init()
648 	breg_val = nwl_bridge_readl(pcie, E_BREG_CAPABILITIES) & BREG_PRESENT;  in nwl_pcie_bridge_init()
655 	nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_breg_base),  in nwl_pcie_bridge_init()
657 	nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_breg_base),  in nwl_pcie_bridge_init()
661 	nwl_bridge_writel(pcie, ~BREG_ENABLE_FORCE & BREG_ENABLE,  in nwl_pcie_bridge_init()
665 	nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, BRCFG_PCIE_RX0) |  in nwl_pcie_bridge_init()
669 	nwl_bridge_writel(pcie, SET_ISUB_CONTROL, I_ISUB_CONTROL);  in nwl_pcie_bridge_init()
672 	nwl_bridge_writel(pcie, CFG_ENABLE_MSG_FILTER_MASK,  in nwl_pcie_bridge_init()
675 	/* This routes the PCIe DMA traffic to go through CCI path */  in nwl_pcie_bridge_init()
677 		nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, BRCFG_PCIE_RX1) |  in nwl_pcie_bridge_init()
680 	err = nwl_wait_for_link(pcie);  in nwl_pcie_bridge_init()
684 	ecam_val = nwl_bridge_readl(pcie, E_ECAM_CAPABILITIES) & E_ECAM_PRESENT;  in nwl_pcie_bridge_init()
691 	nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, E_ECAM_CONTROL) |  in nwl_pcie_bridge_init()
694 	nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, E_ECAM_CONTROL) |  in nwl_pcie_bridge_init()
695 			  (pcie->ecam_value << E_ECAM_SIZE_SHIFT),  in nwl_pcie_bridge_init()
698 	nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_ecam_base),  in nwl_pcie_bridge_init()
700 	nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_ecam_base),  in nwl_pcie_bridge_init()
704 	ecam_val = nwl_bridge_readl(pcie, E_ECAM_CONTROL);  in nwl_pcie_bridge_init()
705 	pcie->last_busno = (ecam_val & E_ECAM_SIZE_LOC) >> E_ECAM_SIZE_SHIFT;  in nwl_pcie_bridge_init()
709 	ecam_val |= (pcie->last_busno << E_ECAM_SIZE_SHIFT);  in nwl_pcie_bridge_init()
710 	writel(ecam_val, (pcie->ecam_base + PCI_PRIMARY_BUS));  in nwl_pcie_bridge_init()
712 	if (nwl_pcie_link_up(pcie))  in nwl_pcie_bridge_init()
718 	pcie->irq_misc = platform_get_irq_byname(pdev, "misc");  in nwl_pcie_bridge_init()
719 	if (pcie->irq_misc < 0)  in nwl_pcie_bridge_init()
722 	err = devm_request_irq(dev, pcie->irq_misc,  in nwl_pcie_bridge_init()
724 			       "nwl_pcie:misc", pcie);  in nwl_pcie_bridge_init()
727 			pcie->irq_misc);  in nwl_pcie_bridge_init()
732 	nwl_bridge_writel(pcie, (u32)~MSGF_MISC_SR_MASKALL, MSGF_MISC_MASK);  in nwl_pcie_bridge_init()
735 	nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MISC_STATUS) &  in nwl_pcie_bridge_init()
739 	nwl_bridge_writel(pcie, MSGF_MISC_SR_MASKALL, MSGF_MISC_MASK);  in nwl_pcie_bridge_init()
743 	nwl_bridge_writel(pcie, (u32)~MSGF_LEG_SR_MASKALL, MSGF_LEG_MASK);  in nwl_pcie_bridge_init()
746 	nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_LEG_STATUS) &  in nwl_pcie_bridge_init()
750 	nwl_bridge_writel(pcie, MSGF_LEG_SR_MASKALL, MSGF_LEG_MASK);  in nwl_pcie_bridge_init()
753 	nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, BRCFG_INTERRUPT) |  in nwl_pcie_bridge_init()
759 static int nwl_pcie_parse_dt(struct nwl_pcie *pcie,  in nwl_pcie_parse_dt()  argument
762 	struct device *dev = pcie->dev;  in nwl_pcie_parse_dt()
766 	pcie->breg_base = devm_ioremap_resource(dev, res);  in nwl_pcie_parse_dt()
767 	if (IS_ERR(pcie->breg_base))  in nwl_pcie_parse_dt()
768 		return PTR_ERR(pcie->breg_base);  in nwl_pcie_parse_dt()
769 	pcie->phys_breg_base = res->start;  in nwl_pcie_parse_dt()
772 	pcie->pcireg_base = devm_ioremap_resource(dev, res);  in nwl_pcie_parse_dt()
773 	if (IS_ERR(pcie->pcireg_base))  in nwl_pcie_parse_dt()
774 		return PTR_ERR(pcie->pcireg_base);  in nwl_pcie_parse_dt()
775 	pcie->phys_pcie_reg_base = res->start;  in nwl_pcie_parse_dt()
778 	pcie->ecam_base = devm_pci_remap_cfg_resource(dev, res);  in nwl_pcie_parse_dt()
779 	if (IS_ERR(pcie->ecam_base))  in nwl_pcie_parse_dt()
780 		return PTR_ERR(pcie->ecam_base);  in nwl_pcie_parse_dt()
781 	pcie->phys_ecam_base = res->start;  in nwl_pcie_parse_dt()
784 	pcie->irq_intx = platform_get_irq_byname(pdev, "intx");  in nwl_pcie_parse_dt()
785 	if (pcie->irq_intx < 0)  in nwl_pcie_parse_dt()
786 		return pcie->irq_intx;  in nwl_pcie_parse_dt()
788 	irq_set_chained_handler_and_data(pcie->irq_intx,  in nwl_pcie_parse_dt()
789 					 nwl_pcie_leg_handler, pcie);  in nwl_pcie_parse_dt()
795 	{ .compatible = "xlnx,nwl-pcie-2.11", },
802 	struct nwl_pcie *pcie;  in nwl_pcie_probe()  local
806 	bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie));  in nwl_pcie_probe()
810 	pcie = pci_host_bridge_priv(bridge);  in nwl_pcie_probe()
812 	pcie->dev = dev;  in nwl_pcie_probe()
813 	pcie->ecam_value = NWL_ECAM_VALUE_DEFAULT;  in nwl_pcie_probe()
815 	err = nwl_pcie_parse_dt(pcie, pdev);  in nwl_pcie_probe()
821 	pcie->clk = devm_clk_get(dev, NULL);  in nwl_pcie_probe()
822 	if (IS_ERR(pcie->clk))  in nwl_pcie_probe()
823 		return PTR_ERR(pcie->clk);  in nwl_pcie_probe()
825 	err = clk_prepare_enable(pcie->clk);  in nwl_pcie_probe()
827 		dev_err(dev, "can't enable PCIe ref clock\n");  in nwl_pcie_probe()
831 	err = nwl_pcie_bridge_init(pcie);  in nwl_pcie_probe()
837 	err = nwl_pcie_init_irq_domain(pcie);  in nwl_pcie_probe()
843 	bridge->sysdata = pcie;  in nwl_pcie_probe()
847 		err = nwl_pcie_enable_msi(pcie);  in nwl_pcie_probe()
859 		.name = "nwl-pcie",