Lines Matching full:pcie
3 * Driver for the Aardvark PCIe controller, used on Marvell Armada
31 /* PCIe core registers */
122 /* PCIe window configuration */
171 /* PCIe core controller registers */
179 /* PCIe Central Interrupts Registers */
250 static inline void advk_writel(struct advk_pcie *pcie, u32 val, u64 reg) in advk_writel() argument
252 writel(val, pcie->base + reg); in advk_writel()
255 static inline u32 advk_readl(struct advk_pcie *pcie, u64 reg) in advk_readl() argument
257 return readl(pcie->base + reg); in advk_readl()
260 static inline u16 advk_read16(struct advk_pcie *pcie, u64 reg) in advk_read16() argument
262 return advk_readl(pcie, (reg & ~0x3)) >> ((reg & 0x3) * 8); in advk_read16()
265 static int advk_pcie_link_up(struct advk_pcie *pcie) in advk_pcie_link_up() argument
269 val = advk_readl(pcie, CFG_REG); in advk_pcie_link_up()
274 static int advk_pcie_wait_for_link(struct advk_pcie *pcie) in advk_pcie_wait_for_link() argument
280 if (advk_pcie_link_up(pcie)) in advk_pcie_wait_for_link()
289 static void advk_pcie_wait_for_retrain(struct advk_pcie *pcie) in advk_pcie_wait_for_retrain() argument
294 if (!advk_pcie_link_up(pcie)) in advk_pcie_wait_for_retrain()
300 static void advk_pcie_issue_perst(struct advk_pcie *pcie) in advk_pcie_issue_perst() argument
304 if (!pcie->reset_gpio) in advk_pcie_issue_perst()
315 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); in advk_pcie_issue_perst()
317 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); in advk_pcie_issue_perst()
320 dev_info(&pcie->pdev->dev, "issuing PERST via reset GPIO for 10ms\n"); in advk_pcie_issue_perst()
321 gpiod_set_value_cansleep(pcie->reset_gpio, 1); in advk_pcie_issue_perst()
323 gpiod_set_value_cansleep(pcie->reset_gpio, 0); in advk_pcie_issue_perst()
326 static int advk_pcie_train_at_gen(struct advk_pcie *pcie, int gen) in advk_pcie_train_at_gen() argument
332 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); in advk_pcie_train_at_gen()
340 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); in advk_pcie_train_at_gen()
346 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); in advk_pcie_train_at_gen()
348 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); in advk_pcie_train_at_gen()
354 reg = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + PCI_EXP_LNKCTL); in advk_pcie_train_at_gen()
356 advk_writel(pcie, reg, PCIE_CORE_PCIEXP_CAP + PCI_EXP_LNKCTL); in advk_pcie_train_at_gen()
358 ret = advk_pcie_wait_for_link(pcie); in advk_pcie_train_at_gen()
362 reg = advk_read16(pcie, PCIE_CORE_PCIEXP_CAP + PCI_EXP_LNKSTA); in advk_pcie_train_at_gen()
368 static void advk_pcie_train_link(struct advk_pcie *pcie) in advk_pcie_train_link() argument
370 struct device *dev = &pcie->pdev->dev; in advk_pcie_train_link()
374 * Reset PCIe card via PERST# signal. Some cards are not detected in advk_pcie_train_link()
377 advk_pcie_issue_perst(pcie); in advk_pcie_train_link()
392 for (gen = pcie->link_gen; gen > 0; --gen) { in advk_pcie_train_link()
393 neg_gen = advk_pcie_train_at_gen(pcie, gen); in advk_pcie_train_link()
408 neg_gen = advk_pcie_train_at_gen(pcie, gen); in advk_pcie_train_link()
421 * Set PCIe address window register which could be used for memory
424 static void advk_pcie_set_ob_win(struct advk_pcie *pcie, u8 win_num, in advk_pcie_set_ob_win() argument
428 advk_writel(pcie, OB_WIN_ENABLE | in advk_pcie_set_ob_win()
430 advk_writel(pcie, upper_32_bits(match), OB_WIN_MATCH_MS(win_num)); in advk_pcie_set_ob_win()
431 advk_writel(pcie, lower_32_bits(remap), OB_WIN_REMAP_LS(win_num)); in advk_pcie_set_ob_win()
432 advk_writel(pcie, upper_32_bits(remap), OB_WIN_REMAP_MS(win_num)); in advk_pcie_set_ob_win()
433 advk_writel(pcie, lower_32_bits(mask), OB_WIN_MASK_LS(win_num)); in advk_pcie_set_ob_win()
434 advk_writel(pcie, upper_32_bits(mask), OB_WIN_MASK_MS(win_num)); in advk_pcie_set_ob_win()
435 advk_writel(pcie, actions, OB_WIN_ACTIONS(win_num)); in advk_pcie_set_ob_win()
438 static void advk_pcie_disable_ob_win(struct advk_pcie *pcie, u8 win_num) in advk_pcie_disable_ob_win() argument
440 advk_writel(pcie, 0, OB_WIN_MATCH_LS(win_num)); in advk_pcie_disable_ob_win()
441 advk_writel(pcie, 0, OB_WIN_MATCH_MS(win_num)); in advk_pcie_disable_ob_win()
442 advk_writel(pcie, 0, OB_WIN_REMAP_LS(win_num)); in advk_pcie_disable_ob_win()
443 advk_writel(pcie, 0, OB_WIN_REMAP_MS(win_num)); in advk_pcie_disable_ob_win()
444 advk_writel(pcie, 0, OB_WIN_MASK_LS(win_num)); in advk_pcie_disable_ob_win()
445 advk_writel(pcie, 0, OB_WIN_MASK_MS(win_num)); in advk_pcie_disable_ob_win()
446 advk_writel(pcie, 0, OB_WIN_ACTIONS(win_num)); in advk_pcie_disable_ob_win()
449 static void advk_pcie_setup_hw(struct advk_pcie *pcie) in advk_pcie_setup_hw() argument
455 reg = advk_readl(pcie, PCIE_CORE_REF_CLK_REG); in advk_pcie_setup_hw()
457 advk_writel(pcie, reg, PCIE_CORE_REF_CLK_REG); in advk_pcie_setup_hw()
460 reg = advk_readl(pcie, CTRL_CONFIG_REG); in advk_pcie_setup_hw()
463 advk_writel(pcie, reg, CTRL_CONFIG_REG); in advk_pcie_setup_hw()
466 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); in advk_pcie_setup_hw()
468 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); in advk_pcie_setup_hw()
478 advk_writel(pcie, reg, VENDOR_ID_REG); in advk_pcie_setup_hw()
485 advk_writel(pcie, reg, PCIE_CORE_ERR_CAPCTL_REG); in advk_pcie_setup_hw()
487 /* Set PCIe Device Control register */ in advk_pcie_setup_hw()
488 reg = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + PCI_EXP_DEVCTL); in advk_pcie_setup_hw()
494 advk_writel(pcie, reg, PCIE_CORE_PCIEXP_CAP + PCI_EXP_DEVCTL); in advk_pcie_setup_hw()
496 /* Program PCIe Control 2 to disable strict ordering */ in advk_pcie_setup_hw()
499 advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG); in advk_pcie_setup_hw()
502 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); in advk_pcie_setup_hw()
505 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); in advk_pcie_setup_hw()
508 reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG); in advk_pcie_setup_hw()
510 advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG); in advk_pcie_setup_hw()
513 advk_writel(pcie, PCIE_ISR0_ALL_MASK, PCIE_ISR0_REG); in advk_pcie_setup_hw()
514 advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_REG); in advk_pcie_setup_hw()
515 advk_writel(pcie, PCIE_IRQ_ALL_MASK, HOST_CTRL_INT_STATUS_REG); in advk_pcie_setup_hw()
520 advk_writel(pcie, reg, PCIE_ISR0_MASK_REG); in advk_pcie_setup_hw()
522 advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_MASK_REG); in advk_pcie_setup_hw()
525 advk_writel(pcie, 0, PCIE_MSI_MASK_REG); in advk_pcie_setup_hw()
529 advk_writel(pcie, reg, HOST_CTRL_INT_MASK_REG); in advk_pcie_setup_hw()
536 * the outbound transactions. Thus, PCIe address in advk_pcie_setup_hw()
541 reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG); in advk_pcie_setup_hw()
543 advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG); in advk_pcie_setup_hw()
547 * is not required to configure PCIe address for in advk_pcie_setup_hw()
550 advk_writel(pcie, OB_WIN_TYPE_MEM, OB_WIN_DEFAULT_ACTIONS); in advk_pcie_setup_hw()
558 reg = advk_readl(pcie, PIO_CTRL); in advk_pcie_setup_hw()
560 advk_writel(pcie, reg, PIO_CTRL); in advk_pcie_setup_hw()
563 * Configure PCIe address windows for non-memory or in advk_pcie_setup_hw()
564 * non-transparent access as by default PCIe uses in advk_pcie_setup_hw()
567 for (i = 0; i < pcie->wins_count; i++) in advk_pcie_setup_hw()
568 advk_pcie_set_ob_win(pcie, i, in advk_pcie_setup_hw()
569 pcie->wins[i].match, pcie->wins[i].remap, in advk_pcie_setup_hw()
570 pcie->wins[i].mask, pcie->wins[i].actions); in advk_pcie_setup_hw()
572 /* Disable remaining PCIe outbound windows */ in advk_pcie_setup_hw()
573 for (i = pcie->wins_count; i < OB_WIN_COUNT; i++) in advk_pcie_setup_hw()
574 advk_pcie_disable_ob_win(pcie, i); in advk_pcie_setup_hw()
576 advk_pcie_train_link(pcie); in advk_pcie_setup_hw()
585 reg = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG); in advk_pcie_setup_hw()
589 advk_writel(pcie, reg, PCIE_CORE_CMD_STATUS_REG); in advk_pcie_setup_hw()
592 static int advk_pcie_check_pio_status(struct advk_pcie *pcie, bool allow_crs, u32 *val) in advk_pcie_check_pio_status() argument
594 struct device *dev = &pcie->pdev->dev; in advk_pcie_check_pio_status()
599 reg = advk_readl(pcie, PIO_STAT); in advk_pcie_check_pio_status()
626 *val = advk_readl(pcie, PIO_RD_DATA); in advk_pcie_check_pio_status()
635 /* PCIe r4.0, sec 2.3.2, says: in advk_pcie_check_pio_status()
651 /* PCIe r4.0, sec 2.3.2, says: in advk_pcie_check_pio_status()
686 str_posted, strcomp_status, reg, advk_readl(pcie, PIO_ADDR_LS)); in advk_pcie_check_pio_status()
691 static int advk_pcie_wait_pio(struct advk_pcie *pcie) in advk_pcie_wait_pio() argument
693 struct device *dev = &pcie->pdev->dev; in advk_pcie_wait_pio()
699 start = advk_readl(pcie, PIO_START); in advk_pcie_wait_pio()
700 isr = advk_readl(pcie, PIO_ISR); in advk_pcie_wait_pio()
715 struct advk_pcie *pcie = bridge->data; in advk_pci_bridge_emul_pcie_conf_read() local
724 u32 val = advk_readl(pcie, PCIE_ISR0_MASK_REG); in advk_pci_bridge_emul_pcie_conf_read()
731 u32 isr0 = advk_readl(pcie, PCIE_ISR0_REG); in advk_pci_bridge_emul_pcie_conf_read()
732 u32 msglog = advk_readl(pcie, PCIE_MSG_LOG_REG); in advk_pci_bridge_emul_pcie_conf_read()
739 u32 val = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + reg) & in advk_pci_bridge_emul_pcie_conf_read()
741 if (!advk_pcie_link_up(pcie)) in advk_pci_bridge_emul_pcie_conf_read()
751 *value = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + reg); in advk_pci_bridge_emul_pcie_conf_read()
763 struct advk_pcie *pcie = bridge->data; in advk_pci_bridge_emul_pcie_conf_write() local
767 advk_writel(pcie, new, PCIE_CORE_PCIEXP_CAP + reg); in advk_pci_bridge_emul_pcie_conf_write()
771 advk_writel(pcie, new, PCIE_CORE_PCIEXP_CAP + reg); in advk_pci_bridge_emul_pcie_conf_write()
773 advk_pcie_wait_for_retrain(pcie); in advk_pci_bridge_emul_pcie_conf_write()
778 u32 val = advk_readl(pcie, PCIE_ISR0_MASK_REG) & in advk_pci_bridge_emul_pcie_conf_write()
782 advk_writel(pcie, val, PCIE_ISR0_MASK_REG); in advk_pci_bridge_emul_pcie_conf_write()
788 advk_writel(pcie, new, PCIE_ISR0_REG); in advk_pci_bridge_emul_pcie_conf_write()
803 * associated with the given PCIe interface.
805 static int advk_sw_pci_bridge_init(struct advk_pcie *pcie) in advk_sw_pci_bridge_init() argument
807 struct pci_bridge_emul *bridge = &pcie->bridge; in advk_sw_pci_bridge_init()
811 cpu_to_le16(advk_readl(pcie, PCIE_CORE_DEV_ID_REG) & 0xffff); in advk_sw_pci_bridge_init()
813 cpu_to_le16(advk_readl(pcie, PCIE_CORE_DEV_ID_REG) >> 16); in advk_sw_pci_bridge_init()
815 cpu_to_le32(advk_readl(pcie, PCIE_CORE_DEV_REV_REG) & 0xff); in advk_sw_pci_bridge_init()
829 bridge->data = pcie; in advk_sw_pci_bridge_init()
832 /* PCIe config space can be initialized after pci_bridge_emul_init() */ in advk_sw_pci_bridge_init()
843 static bool advk_pcie_valid_device(struct advk_pcie *pcie, struct pci_bus *bus, in advk_pcie_valid_device() argument
853 if (!pci_is_root_bus(bus) && !advk_pcie_link_up(pcie)) in advk_pcie_valid_device()
859 static bool advk_pcie_pio_is_running(struct advk_pcie *pcie) in advk_pcie_pio_is_running() argument
861 struct device *dev = &pcie->pdev->dev; in advk_pcie_pio_is_running()
880 if (advk_readl(pcie, PIO_START)) { in advk_pcie_pio_is_running()
891 struct advk_pcie *pcie = bus->sysdata; in advk_pcie_rd_conf() local
896 if (!advk_pcie_valid_device(pcie, bus, devfn)) { in advk_pcie_rd_conf()
902 return pci_bridge_emul_conf_read(&pcie->bridge, where, in advk_pcie_rd_conf()
911 (le16_to_cpu(pcie->bridge.pcie_conf.rootctl) & in advk_pcie_rd_conf()
914 if (advk_pcie_pio_is_running(pcie)) { in advk_pcie_rd_conf()
928 reg = advk_readl(pcie, PIO_CTRL); in advk_pcie_rd_conf()
934 advk_writel(pcie, reg, PIO_CTRL); in advk_pcie_rd_conf()
938 advk_writel(pcie, reg, PIO_ADDR_LS); in advk_pcie_rd_conf()
939 advk_writel(pcie, 0, PIO_ADDR_MS); in advk_pcie_rd_conf()
942 advk_writel(pcie, 0xf, PIO_WR_DATA_STRB); in advk_pcie_rd_conf()
945 advk_writel(pcie, 1, PIO_ISR); in advk_pcie_rd_conf()
946 advk_writel(pcie, 1, PIO_START); in advk_pcie_rd_conf()
948 ret = advk_pcie_wait_pio(pcie); in advk_pcie_rd_conf()
963 ret = advk_pcie_check_pio_status(pcie, allow_crs, val); in advk_pcie_rd_conf()
980 struct advk_pcie *pcie = bus->sysdata; in advk_pcie_wr_conf() local
986 if (!advk_pcie_valid_device(pcie, bus, devfn)) in advk_pcie_wr_conf()
990 return pci_bridge_emul_conf_write(&pcie->bridge, where, in advk_pcie_wr_conf()
996 if (advk_pcie_pio_is_running(pcie)) in advk_pcie_wr_conf()
1000 reg = advk_readl(pcie, PIO_CTRL); in advk_pcie_wr_conf()
1006 advk_writel(pcie, reg, PIO_CTRL); in advk_pcie_wr_conf()
1010 advk_writel(pcie, reg, PIO_ADDR_LS); in advk_pcie_wr_conf()
1011 advk_writel(pcie, 0, PIO_ADDR_MS); in advk_pcie_wr_conf()
1019 advk_writel(pcie, reg, PIO_WR_DATA); in advk_pcie_wr_conf()
1022 advk_writel(pcie, data_strobe, PIO_WR_DATA_STRB); in advk_pcie_wr_conf()
1025 advk_writel(pcie, 1, PIO_ISR); in advk_pcie_wr_conf()
1026 advk_writel(pcie, 1, PIO_START); in advk_pcie_wr_conf()
1028 ret = advk_pcie_wait_pio(pcie); in advk_pcie_wr_conf()
1032 ret = advk_pcie_check_pio_status(pcie, false, NULL); in advk_pcie_wr_conf()
1047 struct advk_pcie *pcie = irq_data_get_irq_chip_data(data); in advk_msi_irq_compose_msi_msg() local
1048 phys_addr_t msi_msg = virt_to_phys(&pcie->msi_msg); in advk_msi_irq_compose_msi_msg()
1065 struct advk_pcie *pcie = domain->host_data; in advk_msi_irq_domain_alloc() local
1068 mutex_lock(&pcie->msi_used_lock); in advk_msi_irq_domain_alloc()
1069 hwirq = bitmap_find_next_zero_area(pcie->msi_used, MSI_IRQ_NUM, in advk_msi_irq_domain_alloc()
1072 mutex_unlock(&pcie->msi_used_lock); in advk_msi_irq_domain_alloc()
1076 bitmap_set(pcie->msi_used, hwirq, nr_irqs); in advk_msi_irq_domain_alloc()
1077 mutex_unlock(&pcie->msi_used_lock); in advk_msi_irq_domain_alloc()
1081 &pcie->msi_bottom_irq_chip, in advk_msi_irq_domain_alloc()
1092 struct advk_pcie *pcie = domain->host_data; in advk_msi_irq_domain_free() local
1094 mutex_lock(&pcie->msi_used_lock); in advk_msi_irq_domain_free()
1095 bitmap_clear(pcie->msi_used, d->hwirq, nr_irqs); in advk_msi_irq_domain_free()
1096 mutex_unlock(&pcie->msi_used_lock); in advk_msi_irq_domain_free()
1106 struct advk_pcie *pcie = d->domain->host_data; in advk_pcie_irq_mask() local
1111 raw_spin_lock_irqsave(&pcie->irq_lock, flags); in advk_pcie_irq_mask()
1112 mask = advk_readl(pcie, PCIE_ISR1_MASK_REG); in advk_pcie_irq_mask()
1114 advk_writel(pcie, mask, PCIE_ISR1_MASK_REG); in advk_pcie_irq_mask()
1115 raw_spin_unlock_irqrestore(&pcie->irq_lock, flags); in advk_pcie_irq_mask()
1120 struct advk_pcie *pcie = d->domain->host_data; in advk_pcie_irq_unmask() local
1125 raw_spin_lock_irqsave(&pcie->irq_lock, flags); in advk_pcie_irq_unmask()
1126 mask = advk_readl(pcie, PCIE_ISR1_MASK_REG); in advk_pcie_irq_unmask()
1128 advk_writel(pcie, mask, PCIE_ISR1_MASK_REG); in advk_pcie_irq_unmask()
1129 raw_spin_unlock_irqrestore(&pcie->irq_lock, flags); in advk_pcie_irq_unmask()
1135 struct advk_pcie *pcie = h->host_data; in advk_pcie_irq_map() local
1139 irq_set_chip_and_handler(virq, &pcie->irq_chip, in advk_pcie_irq_map()
1141 irq_set_chip_data(virq, pcie); in advk_pcie_irq_map()
1151 static int advk_pcie_init_msi_irq_domain(struct advk_pcie *pcie) in advk_pcie_init_msi_irq_domain() argument
1153 struct device *dev = &pcie->pdev->dev; in advk_pcie_init_msi_irq_domain()
1159 mutex_init(&pcie->msi_used_lock); in advk_pcie_init_msi_irq_domain()
1161 bottom_ic = &pcie->msi_bottom_irq_chip; in advk_pcie_init_msi_irq_domain()
1167 msi_ic = &pcie->msi_irq_chip; in advk_pcie_init_msi_irq_domain()
1170 msi_di = &pcie->msi_domain_info; in advk_pcie_init_msi_irq_domain()
1175 msi_msg_phys = virt_to_phys(&pcie->msi_msg); in advk_pcie_init_msi_irq_domain()
1177 advk_writel(pcie, lower_32_bits(msi_msg_phys), in advk_pcie_init_msi_irq_domain()
1179 advk_writel(pcie, upper_32_bits(msi_msg_phys), in advk_pcie_init_msi_irq_domain()
1182 pcie->msi_inner_domain = in advk_pcie_init_msi_irq_domain()
1184 &advk_msi_domain_ops, pcie); in advk_pcie_init_msi_irq_domain()
1185 if (!pcie->msi_inner_domain) in advk_pcie_init_msi_irq_domain()
1188 pcie->msi_domain = in advk_pcie_init_msi_irq_domain()
1190 msi_di, pcie->msi_inner_domain); in advk_pcie_init_msi_irq_domain()
1191 if (!pcie->msi_domain) { in advk_pcie_init_msi_irq_domain()
1192 irq_domain_remove(pcie->msi_inner_domain); in advk_pcie_init_msi_irq_domain()
1199 static void advk_pcie_remove_msi_irq_domain(struct advk_pcie *pcie) in advk_pcie_remove_msi_irq_domain() argument
1201 irq_domain_remove(pcie->msi_domain); in advk_pcie_remove_msi_irq_domain()
1202 irq_domain_remove(pcie->msi_inner_domain); in advk_pcie_remove_msi_irq_domain()
1205 static int advk_pcie_init_irq_domain(struct advk_pcie *pcie) in advk_pcie_init_irq_domain() argument
1207 struct device *dev = &pcie->pdev->dev; in advk_pcie_init_irq_domain()
1213 raw_spin_lock_init(&pcie->irq_lock); in advk_pcie_init_irq_domain()
1217 dev_err(dev, "No PCIe Intc node found\n"); in advk_pcie_init_irq_domain()
1221 irq_chip = &pcie->irq_chip; in advk_pcie_init_irq_domain()
1234 pcie->irq_domain = in advk_pcie_init_irq_domain()
1236 &advk_pcie_irq_domain_ops, pcie); in advk_pcie_init_irq_domain()
1237 if (!pcie->irq_domain) { in advk_pcie_init_irq_domain()
1248 static void advk_pcie_remove_irq_domain(struct advk_pcie *pcie) in advk_pcie_remove_irq_domain() argument
1250 irq_domain_remove(pcie->irq_domain); in advk_pcie_remove_irq_domain()
1253 static void advk_pcie_handle_msi(struct advk_pcie *pcie) in advk_pcie_handle_msi() argument
1258 msi_mask = advk_readl(pcie, PCIE_MSI_MASK_REG); in advk_pcie_handle_msi()
1259 msi_val = advk_readl(pcie, PCIE_MSI_STATUS_REG); in advk_pcie_handle_msi()
1266 advk_writel(pcie, BIT(msi_idx), PCIE_MSI_STATUS_REG); in advk_pcie_handle_msi()
1267 msi_data = advk_readl(pcie, PCIE_MSI_PAYLOAD_REG) & 0xFF; in advk_pcie_handle_msi()
1271 advk_writel(pcie, PCIE_ISR0_MSI_INT_PENDING, in advk_pcie_handle_msi()
1275 static void advk_pcie_handle_int(struct advk_pcie *pcie) in advk_pcie_handle_int() argument
1281 isr0_val = advk_readl(pcie, PCIE_ISR0_REG); in advk_pcie_handle_int()
1282 isr0_mask = advk_readl(pcie, PCIE_ISR0_MASK_REG); in advk_pcie_handle_int()
1285 isr1_val = advk_readl(pcie, PCIE_ISR1_REG); in advk_pcie_handle_int()
1286 isr1_mask = advk_readl(pcie, PCIE_ISR1_MASK_REG); in advk_pcie_handle_int()
1290 advk_writel(pcie, isr0_val, PCIE_ISR0_REG); in advk_pcie_handle_int()
1291 advk_writel(pcie, isr1_val, PCIE_ISR1_REG); in advk_pcie_handle_int()
1297 advk_pcie_handle_msi(pcie); in advk_pcie_handle_int()
1304 advk_writel(pcie, PCIE_ISR1_INTX_ASSERT(i), in advk_pcie_handle_int()
1307 generic_handle_domain_irq(pcie->irq_domain, i); in advk_pcie_handle_int()
1313 struct advk_pcie *pcie = arg; in advk_pcie_irq_handler() local
1316 status = advk_readl(pcie, HOST_CTRL_INT_STATUS_REG); in advk_pcie_irq_handler()
1320 advk_pcie_handle_int(pcie); in advk_pcie_irq_handler()
1323 advk_writel(pcie, PCIE_IRQ_CORE_INT, HOST_CTRL_INT_STATUS_REG); in advk_pcie_irq_handler()
1328 static void __maybe_unused advk_pcie_disable_phy(struct advk_pcie *pcie) in advk_pcie_disable_phy() argument
1330 phy_power_off(pcie->phy); in advk_pcie_disable_phy()
1331 phy_exit(pcie->phy); in advk_pcie_disable_phy()
1334 static int advk_pcie_enable_phy(struct advk_pcie *pcie) in advk_pcie_enable_phy() argument
1338 if (!pcie->phy) in advk_pcie_enable_phy()
1341 ret = phy_init(pcie->phy); in advk_pcie_enable_phy()
1345 ret = phy_set_mode(pcie->phy, PHY_MODE_PCIE); in advk_pcie_enable_phy()
1347 phy_exit(pcie->phy); in advk_pcie_enable_phy()
1351 ret = phy_power_on(pcie->phy); in advk_pcie_enable_phy()
1353 dev_warn(&pcie->pdev->dev, "PHY unsupported by firmware\n"); in advk_pcie_enable_phy()
1355 phy_exit(pcie->phy); in advk_pcie_enable_phy()
1362 static int advk_pcie_setup_phy(struct advk_pcie *pcie) in advk_pcie_setup_phy() argument
1364 struct device *dev = &pcie->pdev->dev; in advk_pcie_setup_phy()
1368 pcie->phy = devm_of_phy_get(dev, node, NULL); in advk_pcie_setup_phy()
1369 if (IS_ERR(pcie->phy) && (PTR_ERR(pcie->phy) == -EPROBE_DEFER)) in advk_pcie_setup_phy()
1370 return PTR_ERR(pcie->phy); in advk_pcie_setup_phy()
1373 if (IS_ERR(pcie->phy)) { in advk_pcie_setup_phy()
1374 dev_warn(dev, "PHY unavailable (%ld)\n", PTR_ERR(pcie->phy)); in advk_pcie_setup_phy()
1375 pcie->phy = NULL; in advk_pcie_setup_phy()
1379 ret = advk_pcie_enable_phy(pcie); in advk_pcie_setup_phy()
1389 struct advk_pcie *pcie; in advk_pcie_probe() local
1398 pcie = pci_host_bridge_priv(bridge); in advk_pcie_probe()
1399 pcie->pdev = pdev; in advk_pcie_probe()
1400 platform_set_drvdata(pdev, pcie); in advk_pcie_probe()
1409 * Aardvark hardware allows to configure also PCIe window in advk_pcie_probe()
1412 * not use PCIe window configuration. in advk_pcie_probe()
1428 * The n-th PCIe window is configured by tuple (match, remap, mask) in advk_pcie_probe()
1431 * So every PCIe window size must be a power of two and every start in advk_pcie_probe()
1436 while (pcie->wins_count < OB_WIN_COUNT && size > 0) { in advk_pcie_probe()
1445 "Configuring PCIe window %d: [0x%llx-0x%llx] as %lu\n", in advk_pcie_probe()
1446 pcie->wins_count, (unsigned long long)start, in advk_pcie_probe()
1450 pcie->wins[pcie->wins_count].actions = OB_WIN_TYPE_IO; in advk_pcie_probe()
1451 pcie->wins[pcie->wins_count].match = pci_pio_to_address(start); in advk_pcie_probe()
1453 pcie->wins[pcie->wins_count].actions = OB_WIN_TYPE_MEM; in advk_pcie_probe()
1454 pcie->wins[pcie->wins_count].match = start; in advk_pcie_probe()
1456 pcie->wins[pcie->wins_count].remap = start - entry->offset; in advk_pcie_probe()
1457 pcie->wins[pcie->wins_count].mask = ~(win_size - 1); in advk_pcie_probe()
1459 if (pcie->wins[pcie->wins_count].remap & (win_size - 1)) in advk_pcie_probe()
1464 pcie->wins_count++; in advk_pcie_probe()
1468 dev_err(&pcie->pdev->dev, in advk_pcie_probe()
1469 "Invalid PCIe region [0x%llx-0x%llx]\n", in advk_pcie_probe()
1476 pcie->base = devm_platform_ioremap_resource(pdev, 0); in advk_pcie_probe()
1477 if (IS_ERR(pcie->base)) in advk_pcie_probe()
1478 return PTR_ERR(pcie->base); in advk_pcie_probe()
1485 IRQF_SHARED | IRQF_NO_THREAD, "advk-pcie", in advk_pcie_probe()
1486 pcie); in advk_pcie_probe()
1492 pcie->reset_gpio = devm_gpiod_get_from_of_node(dev, dev->of_node, in advk_pcie_probe()
1496 ret = PTR_ERR_OR_ZERO(pcie->reset_gpio); in advk_pcie_probe()
1499 pcie->reset_gpio = NULL; in advk_pcie_probe()
1510 pcie->link_gen = 3; in advk_pcie_probe()
1512 pcie->link_gen = ret; in advk_pcie_probe()
1514 ret = advk_pcie_setup_phy(pcie); in advk_pcie_probe()
1518 advk_pcie_setup_hw(pcie); in advk_pcie_probe()
1520 ret = advk_sw_pci_bridge_init(pcie); in advk_pcie_probe()
1526 ret = advk_pcie_init_irq_domain(pcie); in advk_pcie_probe()
1532 ret = advk_pcie_init_msi_irq_domain(pcie); in advk_pcie_probe()
1535 advk_pcie_remove_irq_domain(pcie); in advk_pcie_probe()
1539 bridge->sysdata = pcie; in advk_pcie_probe()
1544 advk_pcie_remove_msi_irq_domain(pcie); in advk_pcie_probe()
1545 advk_pcie_remove_irq_domain(pcie); in advk_pcie_probe()
1554 struct advk_pcie *pcie = platform_get_drvdata(pdev); in advk_pcie_remove() local
1555 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie); in advk_pcie_remove()
1563 advk_pcie_remove_msi_irq_domain(pcie); in advk_pcie_remove()
1564 advk_pcie_remove_irq_domain(pcie); in advk_pcie_remove()
1568 advk_pcie_disable_ob_win(pcie, i); in advk_pcie_remove()
1574 { .compatible = "marvell,armada-3700-pcie", },
1581 .name = "advk-pcie",
1589 MODULE_DESCRIPTION("Aardvark PCIe controller");