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/Linux-v6.1/Documentation/devicetree/bindings/clock/ti/
Ddpll.txt1 Binding for Texas Instruments DPLL clock.
6 register-mapped DPLL with usually two selectable input clocks
12 for the actual DPLL clock.
18 "ti,omap3-dpll-clock",
19 "ti,omap3-dpll-core-clock",
20 "ti,omap3-dpll-per-clock",
21 "ti,omap3-dpll-per-j-type-clock",
22 "ti,omap4-dpll-clock",
23 "ti,omap4-dpll-x2-clock",
24 "ti,omap4-dpll-core-clock",
[all …]
/Linux-v6.1/drivers/clk/ti/
Ddpll3xxx.c3 * OMAP3/4 - specific DPLL control functions
46 /* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */
60 /* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */
129 * _omap3_noncore_dpll_lock - instruct a DPLL to lock and wait for readiness
130 * @clk: pointer to a DPLL struct clk
132 * Instructs a non-CORE DPLL to lock. Waits for the DPLL to report
133 * readiness before returning. Will save and restore the DPLL's
134 * autoidle state across the enable, per the CDP code. If the DPLL
135 * locked successfully, return 0; if the DPLL did not lock in the time
145 pr_debug("clock: locking DPLL %s\n", clk_hw_get_name(&clk->hw)); in _omap3_noncore_dpll_lock()
[all …]
Dclkt_dpll.c3 * OMAP2/3/4 DPLL clock functions
25 /* DPLL rate rounding: minimum DPLL multiplier, divider values */
33 * Scale factor to mitigate roundoff errors in DPLL rate rounding.
44 * DPLL valid Fint frequency range for OMAP36xx and OMAP4xxx.
45 * From device data manual section 4.3 "DPLL and DLL Specifications".
57 * _dpll_test_fint - test whether an Fint value is valid for the DPLL
58 * @clk: DPLL struct clk to test
61 * Tests whether a particular divider @n will result in a valid DPLL
62 * internal clock frequency Fint. See the 34xx TRM 4.7.6.2 "DPLL Jitter
75 /* DPLL divider must result in a valid jitter correction val */ in _dpll_test_fint()
[all …]
Ddpll44xx.c3 * OMAP4-specific DPLL control functions
19 * Maximum DPLL input frequency (FINT) and output frequency (FOUT) that
20 * can supported when using the DPLL low-power mode. Frequencies are
79 * omap4_dpll_lpmode_recalc - compute DPLL low-power setting
80 * @dd: pointer to the dpll data structure
104 * omap4_dpll_regm4xen_recalc - compute DPLL rate, considering REGM4XEN bit
106 * @parent_rate: clock rate of the DPLL parent
108 * Compute the output rate for the OMAP4 DPLL represented by @clk.
110 * OMAP4 ABE DPLL. Returns the DPLL's output rate (before M-dividers)
128 /* regm4xen adds a multiplier of 4 to DPLL calculations */ in omap4_dpll_regm4xen_recalc()
[all …]
Ddpll.c3 * OMAP DPLL clock support
145 * _register_dpll - low level registration of a DPLL clock
149 * Finalizes DPLL registration process. In case a failure (clk-ref or
215 * Initializes a DPLL x 2 clock from device tree data.
272 * of_ti_dpll_setup - Setup function for OMAP DPLL clocks
273 * @node: device node containing the DPLL info
274 * @ops: ops for the DPLL
275 * @ddt: DPLL data template to use
277 * Initializes a DPLL clock from device tree data.
322 * Special case for OMAP2 DPLL, register order is different due to in of_ti_dpll_setup()
[all …]
/Linux-v6.1/drivers/gpu/drm/i915/display/
Dintel_dpll.c310 int pnv_calc_dpll_params(int refclk, struct dpll *clock) in pnv_calc_dpll_params()
322 static u32 i9xx_dpll_compute_m(const struct dpll *dpll) in i9xx_dpll_compute_m() argument
324 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); in i9xx_dpll_compute_m()
327 int i9xx_calc_dpll_params(int refclk, struct dpll *clock) in i9xx_calc_dpll_params()
339 int vlv_calc_dpll_params(int refclk, struct dpll *clock) in vlv_calc_dpll_params()
351 int chv_calc_dpll_params(int refclk, struct dpll *clock) in chv_calc_dpll_params()
370 const struct dpll *clock) in intel_pll_is_valid()
441 const struct dpll *match_clock, in i9xx_find_best_dpll()
442 struct dpll *best_clock) in i9xx_find_best_dpll()
445 struct dpll clock; in i9xx_find_best_dpll()
[all …]
Dintel_dpll.h11 struct dpll;
23 int vlv_calc_dpll_params(int refclk, struct dpll *clock);
24 int pnv_calc_dpll_params(int refclk, struct dpll *clock);
25 int i9xx_calc_dpll_params(int refclk, struct dpll *clock);
26 u32 i9xx_dpll_compute_fp(const struct dpll *dpll);
31 const struct dpll *dpll);
41 struct dpll *best_clock);
42 int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
Dintel_dpll_mgr.h49 * enum intel_dpll_id - possible DPLL ids
51 * Enumeration of possible IDs for a DPLL. Real shared dpll ids must be >= 0.
55 * @DPLL_ID_PRIVATE: non-shared dpll in use
60 * @DPLL_ID_PCH_PLL_A: DPLL A in ILK, SNB and IVB
64 * @DPLL_ID_PCH_PLL_B: DPLL B in ILK, SNB and IVB
187 u32 dpll; member
198 * DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in
201 * the DPLL.
235 * struct intel_shared_dpll_state - hold the DPLL atomic state
237 * This structure holds an atomic state for the DPLL, that can represent
[all …]
Dintel_dpll_mgr.c74 * Hook for reading the values currently programmed to the DPLL
116 /* Copy shared dpll state */ in intel_atomic_duplicate_dpll_state()
117 for (i = 0; i < dev_priv->display.dpll.num_shared_dpll; i++) { in intel_atomic_duplicate_dpll_state()
118 struct intel_shared_dpll *pll = &dev_priv->display.dpll.shared_dplls[i]; in intel_atomic_duplicate_dpll_state()
142 * intel_get_shared_dpll_by_id - get a DPLL given its id
147 * A pointer to the DPLL with @id
153 return &dev_priv->display.dpll.shared_dplls[id]; in intel_get_shared_dpll_by_id()
157 * intel_get_shared_dpll_id - get the id of a DPLL
159 * @pll: the DPLL
168 long pll_idx = pll - dev_priv->display.dpll.shared_dplls; in intel_get_shared_dpll_id()
[all …]
/Linux-v6.1/drivers/gpu/drm/gma500/
Dpsb_intel_display.c104 u32 dpll = 0, fp = 0, dspcntr, pipeconf; in psb_intel_crtc_mode_set() local
155 dpll = DPLL_VGA_MODE_DIS; in psb_intel_crtc_mode_set()
157 dpll |= DPLLB_MODE_LVDS; in psb_intel_crtc_mode_set()
158 dpll |= DPLL_DVO_HIGH_SPEED; in psb_intel_crtc_mode_set()
160 dpll |= DPLLB_MODE_DAC_SERIAL; in psb_intel_crtc_mode_set()
164 dpll |= DPLL_DVO_HIGH_SPEED; in psb_intel_crtc_mode_set()
165 dpll |= in psb_intel_crtc_mode_set()
170 dpll |= (1 << (clock.p1 - 1)) << 16; in psb_intel_crtc_mode_set()
173 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; in psb_intel_crtc_mode_set()
176 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; in psb_intel_crtc_mode_set()
[all …]
Doaktrail_crtc.c243 /* Enable the DPLL */ in oaktrail_crtc_dpms()
244 temp = REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
246 REG_WRITE_WITH_AUX(map->dpll, temp, i); in oaktrail_crtc_dpms()
247 REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
250 REG_WRITE_WITH_AUX(map->dpll, in oaktrail_crtc_dpms()
252 REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
255 REG_WRITE_WITH_AUX(map->dpll, in oaktrail_crtc_dpms()
257 REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
316 temp = REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
318 REG_WRITE_WITH_AUX(map->dpll, in oaktrail_crtc_dpms()
[all …]
Dcdv_intel_display.c206 /* Unlike most Intel display engines, on Cedarview the DPLL registers
208 * DPLL reference clock is on in the DPLL control register, but before
209 * the DPLL is enabled in the DPLL control register.
260 DRM_DEBUG_KMS("use their DPLL for pipe A/B\n"); in cdv_dpll_set_clock_cdv()
583 u32 dpll = 0, dspcntr, pipeconf; in cdv_intel_crtc_mode_set() local
664 dpll = DPLL_VGA_MODE_DIS; in cdv_intel_crtc_mode_set()
675 dpll |= DPLL_SYNCLOCK_ENABLE; in cdv_intel_crtc_mode_set()
677 dpll |= DPLLB_MODE_LVDS; in cdv_intel_crtc_mode_set()
679 dpll |= DPLLB_MODE_DAC_SERIAL; */ in cdv_intel_crtc_mode_set()
680 /* dpll |= (2 << 11); */ in cdv_intel_crtc_mode_set()
[all …]
Dgma_display.c220 /* Enable the DPLL */ in gma_crtc_dpms()
221 temp = REG_READ(map->dpll); in gma_crtc_dpms()
223 REG_WRITE(map->dpll, temp); in gma_crtc_dpms()
224 REG_READ(map->dpll); in gma_crtc_dpms()
227 REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE); in gma_crtc_dpms()
228 REG_READ(map->dpll); in gma_crtc_dpms()
231 REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE); in gma_crtc_dpms()
232 REG_READ(map->dpll); in gma_crtc_dpms()
308 /* Disable DPLL */ in gma_crtc_dpms()
309 temp = REG_READ(map->dpll); in gma_crtc_dpms()
[all …]
/Linux-v6.1/include/linux/clk/
Dti.h26 * struct dpll_data - DPLL registers and integration data
27 * @mult_div1_reg: register containing the DPLL M and N bitfields
28 * @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg
29 * @div1_mask: mask of the DPLL N bitfield in @mult_div1_reg
32 * @control_reg: register containing the DPLL mode bitfield
33 * @enable_mask: mask of the DPLL mode bitfield in @control_reg
44 * @max_rate: maximum clock rate for the DPLL
46 * @autoidle_reg: register containing the DPLL autoidle mode bitfield
47 * @idlest_reg: register containing the DPLL idle status bitfield
48 * @autoidle_mask: mask of the DPLL autoidle mode bitfield in @autoidle_reg
[all …]
/Linux-v6.1/arch/arm/mach-omap2/
Dclkt2xxx_dpll.c3 * OMAP2-specific DPLL control functions
21 * _allow_idle - enable DPLL autoidle bits
22 * @clk: struct clk * of the DPLL to operate on
24 * Enable DPLL automatic idle control. The DPLL will enter low-power
26 * REVISIT: DPLL can optionally enter low-power bypass by writing 0x1
38 * _deny_idle - prevent DPLL from automatically idling
39 * @clk: struct clk * of the DPLL to operate on
41 * Disable DPLL automatic idle control. No return value.
Dsleep24xx.S35 * The if the DPLL is going to AutoIdle. It seems like the DPLL may be back on
37 * case the DPLL isn't quite there yet. The code will wait on DLL for DDR even
44 * Post sleep we will shift back to using the DPLL. Apparently,
60 mov r5, #0x2000 @ set delay (DPLL relock + DLL relock)
69 /* The DPLL has to be on before we take the DDR out of self refresh */
Dopp2xxx.h14 * respect to each other. These ratio sets are for a given voltage/DPLL
15 * setting. All configurations can be described by a DPLL setting and a ratio
45 unsigned long dpll_speed; /* dpll: out*xtal*M/(N-1)table_recalc */
65 * Voltage/DPLL ratios
218 * describe DPLL combinations to go along with a ratio.
230 * #5a (ratio1) baseport-target, target DPLL = 266*2 = 532MHz
247 /* #5b (ratio1) target DPLL = 200*2 = 400MHz */
265 * #4 (ratio2), DPLL = 399*2 = 798MHz, L3=133MHz
286 * #3 (ratio2) baseport-target, target DPLL = 330*2 = 660MHz
305 * #2 (ratio1) DPLL = 330*2 = 660MHz, L3=165MHz
[all …]
Dclkt2xxx_dpllcore.c3 * DPLL + CORE_CLK composite clock functions
15 * XXX The DPLL and CORE clocks should be split into two separate clock
46 * sources on OMAP2xxx: the DPLL CLKOUT rate, DPLL CLKOUTX2, or 32KHz
80 if (core_clk_src == CORE_CLK_SRC_DPLL) { /* DPLL clockout */ in omap2_dpllcore_round_rate()
83 } else { /* DPLL clockout x 2 */ in omap2_dpllcore_round_rate()
/Linux-v6.1/Documentation/devicetree/bindings/media/i2c/
Dadv748x.yaml38 - enum: [ dpll, cp, hdmi, edid, repeater, infoframe, cbus, cec, sdp, txa, txb ]
39 - enum: [ dpll, cp, hdmi, edid, repeater, infoframe, cbus, cec, sdp, txa, txb ]
40 - enum: [ dpll, cp, hdmi, edid, repeater, infoframe, cbus, cec, sdp, txa, txb ]
41 - enum: [ dpll, cp, hdmi, edid, repeater, infoframe, cbus, cec, sdp, txa, txb ]
42 - enum: [ dpll, cp, hdmi, edid, repeater, infoframe, cbus, cec, sdp, txa, txb ]
43 - enum: [ dpll, cp, hdmi, edid, repeater, infoframe, cbus, cec, sdp, txa, txb ]
44 - enum: [ dpll, cp, hdmi, edid, repeater, infoframe, cbus, cec, sdp, txa, txb ]
45 - enum: [ dpll, cp, hdmi, edid, repeater, infoframe, cbus, cec, sdp, txa, txb ]
46 - enum: [ dpll, cp, hdmi, edid, repeater, infoframe, cbus, cec, sdp, txa, txb ]
47 - enum: [ dpll, cp, hdmi, edid, repeater, infoframe, cbus, cec, sdp, txa, txb ]
[all …]
/Linux-v6.1/arch/arm/boot/dts/
Ddra7xx-clocks.dtsi229 compatible = "ti,omap4-dpll-m4xen-clock";
235 dpll_abe_x2_ck: clock-dpll-abe-x2 {
237 compatible = "ti,omap4-dpll-x2-clock";
242 dpll_abe_m2x2_ck: clock-dpll-abe-m2x2-8@1f0 {
264 dpll_abe_m2_ck: clock-dpll-abe-m2-8@1f0 {
276 dpll_abe_m3x2_ck: clock-dpll-abe-m3x2-8@1f4 {
288 dpll_core_byp_mux: clock-dpll-core-byp-mux-23@12c {
299 compatible = "ti,omap4-dpll-core-clock";
305 dpll_core_x2_ck: clock-dpll-core-x2 {
307 compatible = "ti,omap4-dpll-x2-clock";
[all …]
Dam43xx-clocks.dtsi231 compatible = "ti,am3-dpll-core-clock";
237 dpll_core_x2_ck: clock-dpll-core-x2 {
239 compatible = "ti,am3-dpll-x2-clock";
244 dpll_core_m4_ck: clock-dpll-core-m4-8@2d38 {
256 dpll_core_m5_ck: clock-dpll-core-m5-8@2d3c {
268 dpll_core_m6_ck: clock-dpll-core-m6-8@2d40 {
282 compatible = "ti,am3-dpll-clock";
288 dpll_mpu_m2_ck: clock-dpll-mpu-m2-8@2d70 {
311 compatible = "ti,am3-dpll-clock";
317 dpll_ddr_m2_ck: clock-dpll-ddr-m2-8@2db0 {
[all …]
Dam33xx-clocks.dtsi190 compatible = "ti,am3-dpll-core-clock";
196 dpll_core_x2_ck: clock-dpll-core-x2 {
198 compatible = "ti,am3-dpll-x2-clock";
203 dpll_core_m4_ck: clock-dpll-core-m4@480 {
213 dpll_core_m5_ck: clock-dpll-core-m5@484 {
223 dpll_core_m6_ck: clock-dpll-core-m6@4d8 {
235 compatible = "ti,am3-dpll-clock";
241 dpll_mpu_m2_ck: clock-dpll-mpu-m2@4a8 {
253 compatible = "ti,am3-dpll-no-gate-clock";
259 dpll_ddr_m2_ck: clock-dpll-ddr-m2@4a0 {
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/clock/
Dmicrochip,sparx5-dpll.yaml4 $id: http://devicetree.org/schemas/clock/microchip,sparx5-dpll.yaml#
7 title: Microchip Sparx5 DPLL Clock
13 The Sparx5 DPLL clock controller generates and supplies clock to
18 const: microchip,sparx5-dpll
46 compatible = "microchip,sparx5-dpll";
/Linux-v6.1/drivers/ata/
Dpata_hpt3x2n.c61 /* 66MHz DPLL clocks */
263 * We must use the DPLL for
299 /* See if we should use the DPLL */ in hpt3x2n_use_dpll()
312 int dpll = hpt3x2n_use_dpll(ap, qc->tf.flags & ATA_TFLAG_WRITE); in hpt3x2n_qc_defer() local
319 if ((flags & USE_DPLL) != dpll && alt->qc_active) in hpt3x2n_qc_defer()
328 int dpll = hpt3x2n_use_dpll(ap, qc->tf.flags & ATA_TFLAG_WRITE); in hpt3x2n_qc_issue() local
330 if ((flags & USE_DPLL) != dpll) { in hpt3x2n_qc_issue()
332 flags |= dpll; in hpt3x2n_qc_issue()
335 hpt3x2n_set_clock(ap, dpll ? 0x21 : 0x23); in hpt3x2n_qc_issue()
372 * hpt3xn_calibrate_dpll - Calibrate the DPLL loop
[all …]
/Linux-v6.1/arch/arm/mach-omap1/
Dsram.S36 strh r0, [r2] @ set dpll into bypass mode
41 strh r0, [r2] @ write new dpll value
49 lock: ldrh r4, [r2], #0 @ read back dpll value
52 tst r4, #1 << 0 @ dpll rate locked?

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