243 			/* Enable the DPLL */  in oaktrail_crtc_dpms()
244 			temp = REG_READ_WITH_AUX(map->dpll, i);  in oaktrail_crtc_dpms()
246 				REG_WRITE_WITH_AUX(map->dpll, temp, i);  in oaktrail_crtc_dpms()
247 				REG_READ_WITH_AUX(map->dpll, i);  in oaktrail_crtc_dpms()
250 				REG_WRITE_WITH_AUX(map->dpll,  in oaktrail_crtc_dpms()
252 				REG_READ_WITH_AUX(map->dpll, i);  in oaktrail_crtc_dpms()
255 				REG_WRITE_WITH_AUX(map->dpll,  in oaktrail_crtc_dpms()
257 				REG_READ_WITH_AUX(map->dpll, i);  in oaktrail_crtc_dpms()
316 			temp = REG_READ_WITH_AUX(map->dpll, i);  in oaktrail_crtc_dpms()
318 				REG_WRITE_WITH_AUX(map->dpll,  in oaktrail_crtc_dpms()
320 				REG_READ_WITH_AUX(map->dpll, i);  in oaktrail_crtc_dpms()
372 	u32 dpll = 0, fp = 0, dspcntr, pipeconf;  in oaktrail_crtc_mode_set()  local
502 	dpll = 0;		/*BIT16 = 0 for 100MHz reference */  in oaktrail_crtc_mode_set()
526 	dpll |= DPLL_VGA_MODE_DIS;  in oaktrail_crtc_mode_set()
529 	dpll |= DPLL_VCO_ENABLE;  in oaktrail_crtc_mode_set()
532 		dpll |= DPLLA_MODE_LVDS;  in oaktrail_crtc_mode_set()
534 		dpll |= DPLLB_MODE_DAC_SERIAL;  in oaktrail_crtc_mode_set()
540 		dpll |= DPLL_DVO_HIGH_SPEED;  in oaktrail_crtc_mode_set()
541 		dpll |=  in oaktrail_crtc_mode_set()
549 		dpll |= clock.p1 << 16; // dpll |= (1 << (clock.p1 - 1)) << 16;  in oaktrail_crtc_mode_set()
551 		dpll |= (1 << (clock.p1 - 2)) << 17;  in oaktrail_crtc_mode_set()
553 	dpll |= DPLL_VCO_ENABLE;  in oaktrail_crtc_mode_set()
555 	if (dpll & DPLL_VCO_ENABLE) {  in oaktrail_crtc_mode_set()
558 			REG_WRITE_WITH_AUX(map->dpll, dpll & ~DPLL_VCO_ENABLE, i);  in oaktrail_crtc_mode_set()
559 			REG_READ_WITH_AUX(map->dpll, i);  in oaktrail_crtc_mode_set()
567 		REG_WRITE_WITH_AUX(map->dpll, dpll, i);  in oaktrail_crtc_mode_set()
568 		REG_READ_WITH_AUX(map->dpll, i);  in oaktrail_crtc_mode_set()
573 		REG_WRITE_WITH_AUX(map->dpll, dpll, i);  in oaktrail_crtc_mode_set()
574 		REG_READ_WITH_AUX(map->dpll, i);  in oaktrail_crtc_mode_set()