Lines Matching full:dpll
74 * Hook for reading the values currently programmed to the DPLL
116 /* Copy shared dpll state */ in intel_atomic_duplicate_dpll_state()
117 for (i = 0; i < dev_priv->display.dpll.num_shared_dpll; i++) { in intel_atomic_duplicate_dpll_state()
118 struct intel_shared_dpll *pll = &dev_priv->display.dpll.shared_dplls[i]; in intel_atomic_duplicate_dpll_state()
142 * intel_get_shared_dpll_by_id - get a DPLL given its id
147 * A pointer to the DPLL with @id
153 return &dev_priv->display.dpll.shared_dplls[id]; in intel_get_shared_dpll_by_id()
157 * intel_get_shared_dpll_id - get the id of a DPLL
159 * @pll: the DPLL
168 long pll_idx = pll - dev_priv->display.dpll.shared_dplls; in intel_get_shared_dpll_id()
172 pll_idx >= dev_priv->display.dpll.num_shared_dpll)) in intel_get_shared_dpll_id()
187 "asserting DPLL %s with no DPLL\n", str_on_off(state))) in assert_shared_dpll()
233 * intel_enable_shared_dpll - enable a CRTC's shared DPLL
234 * @crtc_state: CRTC, and its state, which has a shared DPLL
236 * Enable the shared DPLL used by @crtc.
249 mutex_lock(&dev_priv->display.dpll.lock); in intel_enable_shared_dpll()
275 mutex_unlock(&dev_priv->display.dpll.lock); in intel_enable_shared_dpll()
279 * intel_disable_shared_dpll - disable a CRTC's shared DPLL
280 * @crtc_state: CRTC, and its state, which has a shared DPLL
282 * Disable the shared DPLL used by @crtc.
298 mutex_lock(&dev_priv->display.dpll.lock); in intel_disable_shared_dpll()
321 mutex_unlock(&dev_priv->display.dpll.lock); in intel_disable_shared_dpll()
340 pll = &dev_priv->display.dpll.shared_dplls[i]; in intel_find_shared_dpll()
421 * intel_shared_dpll_swap_state - make atomic DPLL configuration effective
424 * This is the dpll version of drm_atomic_helper_swap_state() since the
440 for (i = 0; i < dev_priv->display.dpll.num_shared_dpll; i++) { in intel_shared_dpll_swap_state()
442 &dev_priv->display.dpll.shared_dplls[i]; in intel_shared_dpll_swap_state()
462 hw_state->dpll = val; in ibx_pch_dpll_get_hw_state()
495 intel_de_write(dev_priv, PCH_DPLL(id), pll->state.hw_state.dpll); in ibx_pch_dpll_enable()
502 * DPLL is enabled and the clocks are stable. in ibx_pch_dpll_enable()
506 intel_de_write(dev_priv, PCH_DPLL(id), pll->state.hw_state.dpll); in ibx_pch_dpll_enable()
541 pll = &dev_priv->display.dpll.shared_dplls[i]; in ibx_get_dpll()
570 "dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, " in ibx_dump_hw_state()
572 hw_state->dpll, in ibx_dump_hw_state()
585 { "PCH DPLL A", &ibx_pch_dpll_funcs, DPLL_ID_PCH_PLL_A, 0 },
586 { "PCH DPLL B", &ibx_pch_dpll_funcs, DPLL_ID_PCH_PLL_B, 0 },
921 refclk = dev_priv->display.dpll.ref_clks.nssc; in hsw_ddi_wrpll_get_freq()
931 refclk = dev_priv->display.dpll.ref_clks.ssc; in hsw_ddi_wrpll_get_freq()
1153 i915->display.dpll.ref_clks.ssc = 135000; in hsw_update_dpll_ref_clks()
1156 i915->display.dpll.ref_clks.nssc = 24000; in hsw_update_dpll_ref_clks()
1158 i915->display.dpll.ref_clks.nssc = 135000; in hsw_update_dpll_ref_clks()
1232 /* DPLL 0 */
1234 /* DPLL 0 doesn't support HDMI mode */
1237 /* DPLL 1 */
1243 /* DPLL 2 */
1249 /* DPLL 3 */
1291 drm_err(&dev_priv->drm, "DPLL %d not locked\n", id); in skl_ddi_pll_enable()
1630 int ref_clock = i915->display.dpll.ref_clks.nssc; in skl_ddi_wrpll_get_freq()
1706 * as the DPLL id in this function. in skl_ddi_hdmi_pll_dividers()
1713 i915->display.dpll.ref_clks.nssc, &wrpll_params); in skl_ddi_hdmi_pll_dividers()
1744 * as the DPLL id in this function. in skl_ddi_dp_set_dpll_hw_state()
1869 i915->display.dpll.ref_clks.nssc = i915->display.cdclk.hw.ref; in skl_update_dpll_ref_clks()
1897 { "DPLL 0", &skl_ddi_dpll0_funcs, DPLL_ID_SKL_DPLL0, INTEL_DPLL_ALWAYS_ON },
1898 { "DPLL 1", &skl_ddi_pll_funcs, DPLL_ID_SKL_DPLL1, 0 },
1899 { "DPLL 2", &skl_ddi_pll_funcs, DPLL_ID_SKL_DPLL2, 0 },
1900 { "DPLL 3", &skl_ddi_pll_funcs, DPLL_ID_SKL_DPLL3, 0 },
2138 static const struct dpll bxt_dp_clk_val[] = {
2151 struct dpll *clk_div) in bxt_ddi_hdmi_pll_dividers()
2169 struct dpll *clk_div) in bxt_ddi_dp_pll_dividers()
2182 chv_calc_dpll_params(i915->display.dpll.ref_clks.nssc, clk_div); in bxt_ddi_dp_pll_dividers()
2189 const struct dpll *clk_div) in bxt_ddi_set_dpll_hw_state()
2260 struct dpll clock; in bxt_ddi_pll_get_freq()
2270 return chv_calc_dpll_params(i915->display.dpll.ref_clks.nssc, &clock); in bxt_ddi_pll_get_freq()
2276 struct dpll clk_div = {}; in bxt_ddi_dp_set_dpll_hw_state()
2287 struct dpll clk_div = {}; in bxt_ddi_hdmi_set_dpll_hw_state()
2344 i915->display.dpll.ref_clks.ssc = 100000; in bxt_update_dpll_ref_clks()
2345 i915->display.dpll.ref_clks.nssc = 100000; in bxt_update_dpll_ref_clks()
2488 i915->display.dpll.ref_clks.nssc == 38400; in ehl_combo_pll_div_frac_wa_needed()
2582 dev_priv->display.dpll.ref_clks.nssc == 24000 ? in icl_calc_dp_combo_pll()
2605 switch (dev_priv->display.dpll.ref_clks.nssc) { in icl_calc_tbt_pll()
2607 MISSING_CASE(dev_priv->display.dpll.ref_clks.nssc); in icl_calc_tbt_pll()
2618 switch (dev_priv->display.dpll.ref_clks.nssc) { in icl_calc_tbt_pll()
2620 MISSING_CASE(dev_priv->display.dpll.ref_clks.nssc); in icl_calc_tbt_pll()
2650 int ref_clock = i915->display.dpll.ref_clks.nssc; in icl_wrpll_ref_clock()
2654 * use 19.2 because the DPLL automatically divides that by 2. in icl_wrpll_ref_clock()
2877 int refclk_khz = dev_priv->display.dpll.ref_clks.nssc; in icl_calc_mg_pll_state()
3083 ref_clock = dev_priv->display.dpll.ref_clks.nssc; in icl_ddi_mg_pll_get_freq()
3149 * icl_set_active_port_dpll - select the active port DPLL for a given CRTC
3150 * @crtc_state: state for the CRTC to select the DPLL for
3472 if (dev_priv->display.dpll.ref_clks.nssc == 38400) { in mg_pll_get_hw_state()
3860 * We need to disable DC states when this DPLL is enabled. in combo_pll_enable()
3993 i915->display.dpll.ref_clks.nssc = i915->display.cdclk.hw.ref; in icl_update_dpll_ref_clks()
4042 { "DPLL 0", &combo_pll_funcs, DPLL_ID_ICL_DPLL0, 0 },
4043 { "DPLL 1", &combo_pll_funcs, DPLL_ID_ICL_DPLL1, 0 },
4063 { "DPLL 0", &combo_pll_funcs, DPLL_ID_ICL_DPLL0, 0 },
4064 { "DPLL 1", &combo_pll_funcs, DPLL_ID_ICL_DPLL1, 0 },
4065 { "DPLL 4", &combo_pll_funcs, DPLL_ID_EHL_DPLL4, 0 },
4086 { "DPLL 0", &combo_pll_funcs, DPLL_ID_ICL_DPLL0, 0 },
4087 { "DPLL 1", &combo_pll_funcs, DPLL_ID_ICL_DPLL1, 0 },
4109 { "DPLL 0", &combo_pll_funcs, DPLL_ID_ICL_DPLL0, 0 },
4110 { "DPLL 1", &combo_pll_funcs, DPLL_ID_ICL_DPLL1, 0 },
4111 { "DPLL 4", &combo_pll_funcs, DPLL_ID_EHL_DPLL4, 0 },
4125 { "DPLL 0", &combo_pll_funcs, DPLL_ID_DG1_DPLL0, 0 },
4126 { "DPLL 1", &combo_pll_funcs, DPLL_ID_DG1_DPLL1, 0 },
4127 { "DPLL 2", &combo_pll_funcs, DPLL_ID_DG1_DPLL2, 0 },
4128 { "DPLL 3", &combo_pll_funcs, DPLL_ID_DG1_DPLL3, 0 },
4142 { "DPLL 0", &combo_pll_funcs, DPLL_ID_ICL_DPLL0, 0 },
4143 { "DPLL 1", &combo_pll_funcs, DPLL_ID_ICL_DPLL1, 0 },
4144 { "DPLL 2", &combo_pll_funcs, DPLL_ID_DG1_DPLL2, 0 },
4145 { "DPLL 3", &combo_pll_funcs, DPLL_ID_DG1_DPLL3, 0 },
4159 { "DPLL 0", &combo_pll_funcs, DPLL_ID_ICL_DPLL0, 0 },
4160 { "DPLL 1", &combo_pll_funcs, DPLL_ID_ICL_DPLL1, 0 },
4218 dev_priv->display.dpll.num_shared_dpll = 0; in intel_shared_dpll_init()
4226 i >= ARRAY_SIZE(dev_priv->display.dpll.shared_dplls))) in intel_shared_dpll_init()
4230 dev_priv->display.dpll.shared_dplls[i].info = &dpll_info[i]; in intel_shared_dpll_init()
4233 dev_priv->display.dpll.mgr = dpll_mgr; in intel_shared_dpll_init()
4234 dev_priv->display.dpll.num_shared_dpll = i; in intel_shared_dpll_init()
4235 mutex_init(&dev_priv->display.dpll.lock); in intel_shared_dpll_init()
4239 * intel_compute_shared_dplls - compute DPLL state CRTC and encoder combination
4244 * This function computes the DPLL state for the given CRTC and encoder.
4257 const struct intel_dpll_mgr *dpll_mgr = dev_priv->display.dpll.mgr; in intel_compute_shared_dplls()
4290 const struct intel_dpll_mgr *dpll_mgr = dev_priv->display.dpll.mgr; in intel_reserve_shared_dplls()
4313 const struct intel_dpll_mgr *dpll_mgr = dev_priv->display.dpll.mgr; in intel_release_shared_dplls()
4318 * the shared DPLL framework and intel_reserve_shared_dplls() is not in intel_release_shared_dplls()
4328 * intel_update_active_dpll - update the active DPLL for a CRTC/encoder
4330 * @crtc: the CRTC for which to update the active DPLL
4331 * @encoder: encoder determining the type of port DPLL
4333 * Update the active DPLL for the given @crtc/@encoder in @crtc's atomic state,
4335 * DPLL selected will be based on the current mode of the encoder's port.
4342 const struct intel_dpll_mgr *dpll_mgr = dev_priv->display.dpll.mgr; in intel_update_active_dpll()
4351 * intel_dpll_get_freq - calculate the DPLL's output frequency
4353 * @pll: DPLL for which to calculate the output frequency
4354 * @pll_state: DPLL state from which to calculate the output frequency
4369 * intel_dpll_get_hw_state - readout the DPLL's hardware state
4371 * @pll: DPLL for which to calculate the output frequency
4372 * @hw_state: DPLL's hardware state
4413 if (i915->display.dpll.mgr && i915->display.dpll.mgr->update_ref_clks) in intel_dpll_update_ref_clks()
4414 i915->display.dpll.mgr->update_ref_clks(i915); in intel_dpll_update_ref_clks()
4421 for (i = 0; i < i915->display.dpll.num_shared_dpll; i++) in intel_dpll_readout_hw_state()
4422 readout_dpll_hw_state(i915, &i915->display.dpll.shared_dplls[i]); in intel_dpll_readout_hw_state()
4448 for (i = 0; i < i915->display.dpll.num_shared_dpll; i++) in intel_dpll_sanitize_state()
4449 sanitize_dpll_state(i915, &i915->display.dpll.shared_dplls[i]); in intel_dpll_sanitize_state()
4462 if (dev_priv->display.dpll.mgr) { in intel_dpll_dump_hw_state()
4463 dev_priv->display.dpll.mgr->dump_hw_state(dev_priv, hw_state); in intel_dpll_dump_hw_state()
4465 /* fallback for platforms that don't use the shared dpll in intel_dpll_dump_hw_state()
4469 "dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, " in intel_dpll_dump_hw_state()
4471 hw_state->dpll, in intel_dpll_dump_hw_state()
4561 for (i = 0; i < i915->display.dpll.num_shared_dpll; i++) in intel_shared_dpll_verify_disabled()
4562 verify_single_dpll_state(i915, &i915->display.dpll.shared_dplls[i], in intel_shared_dpll_verify_disabled()