Lines Matching full:dpll
3 * OMAP DPLL clock support
145 * _register_dpll - low level registration of a DPLL clock
149 * Finalizes DPLL registration process. In case a failure (clk-ref or
215 * Initializes a DPLL x 2 clock from device tree data.
272 * of_ti_dpll_setup - Setup function for OMAP DPLL clocks
273 * @node: device node containing the DPLL info
274 * @ops: ops for the DPLL
275 * @ddt: DPLL data template to use
277 * Initializes a DPLL clock from device tree data.
322 * Special case for OMAP2 DPLL, register order is different due to in of_ti_dpll_setup()
399 CLK_OF_DECLARE(ti_omap4_dpll_x2_clock, "ti,omap4-dpll-x2-clock",
408 CLK_OF_DECLARE(ti_am3_dpll_x2_clock, "ti,am3-dpll-x2-clock",
435 CLK_OF_DECLARE(ti_omap3_dpll_clock, "ti,omap3-dpll-clock",
454 CLK_OF_DECLARE(ti_omap3_core_dpll_clock, "ti,omap3-dpll-core-clock",
474 CLK_OF_DECLARE(ti_omap3_per_dpll_clock, "ti,omap3-dpll-per-clock",
496 CLK_OF_DECLARE(ti_omap3_per_jtype_dpll_clock, "ti,omap3-dpll-per-j-type-clock",
516 CLK_OF_DECLARE(ti_omap4_dpll_clock, "ti,omap4-dpll-clock",
537 CLK_OF_DECLARE(of_ti_omap5_mpu_dpll_clock, "ti,omap5-mpu-dpll-clock",
556 CLK_OF_DECLARE(ti_omap4_core_dpll_clock, "ti,omap4-dpll-core-clock",
579 CLK_OF_DECLARE(ti_omap4_m4xen_dpll_clock, "ti,omap4-dpll-m4xen-clock",
600 CLK_OF_DECLARE(ti_omap4_jtype_dpll_clock, "ti,omap4-dpll-j-type-clock",
626 CLK_OF_DECLARE(ti_am3_no_gate_dpll_clock, "ti,am3-dpll-no-gate-clock",
646 CLK_OF_DECLARE(ti_am3_jtype_dpll_clock, "ti,am3-dpll-j-type-clock",
667 "ti,am3-dpll-no-gate-j-type-clock",
692 CLK_OF_DECLARE(ti_am3_dpll_clock, "ti,am3-dpll-clock", of_ti_am3_dpll_setup);
710 CLK_OF_DECLARE(ti_am3_core_dpll_clock, "ti,am3-dpll-core-clock",
725 CLK_OF_DECLARE(ti_omap2_core_dpll_clock, "ti,omap2-dpll-core-clock",