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/Linux-v5.15/drivers/gpu/drm/i915/gt/
Dselftest_lrc.c1 // SPDX-License-Identifier: MIT
24 #define CS_GPR(engine, n) ((engine)->mmio_base + 0x600 + (n) * 4)
30 return __vm_create_scratch_for_read_pinned(&gt->ggtt->vm, PAGE_SIZE); in create_scratch()
52 tasklet_hi_schedule(&engine->sched_engine->tasklet); in wait_for_submit()
63 if (!READ_ONCE(engine->execlists.pending[0]) && is_active(rq)) in wait_for_submit()
67 return -ETIME; in wait_for_submit()
76 i915_ggtt_offset(ce->engine->status_page.vma) + in emit_semaphore_signal()
79 u32 *cs; in emit_semaphore_signal() local
85 cs = intel_ring_begin(rq, 4); in emit_semaphore_signal()
86 if (IS_ERR(cs)) { in emit_semaphore_signal()
[all …]
Dselftest_workarounds.c1 // SPDX-License-Identifier: MIT
41 err = -EIO; in request_add_sync()
54 err = -ETIMEDOUT; in request_add_spin()
68 wa_init_start(&lists->gt_wa_list, "GT_REF", "global"); in reference_lists_init()
69 gt_init_workarounds(gt->i915, &lists->gt_wa_list); in reference_lists_init()
70 wa_init_finish(&lists->gt_wa_list); in reference_lists_init()
73 struct i915_wa_list *wal = &lists->engine[id].wa_list; in reference_lists_init()
75 wa_init_start(wal, "REF", engine->name); in reference_lists_init()
80 &lists->engine[id].ctx_wa_list, in reference_lists_init()
92 intel_wa_list_free(&lists->engine[id].wa_list); in reference_lists_fini()
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Dselftest_engine_pm.c1 // SPDX-License-Identifier: GPL-2.0
23 return *a - *b; in cmp_u64()
32 static u32 *emit_wait(u32 *cs, u32 offset, int op, u32 value) in emit_wait() argument
34 *cs++ = MI_SEMAPHORE_WAIT | in emit_wait()
38 *cs++ = value; in emit_wait()
39 *cs++ = offset; in emit_wait()
40 *cs++ = 0; in emit_wait()
42 return cs; in emit_wait()
45 static u32 *emit_store(u32 *cs, u32 offset, u32 value) in emit_store() argument
47 *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT; in emit_store()
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Dintel_lrc.c1 // SPDX-License-Identifier: MIT
23 #define NOP(x) (BIT(7) | (x)) in set_offsets() argument
26 #define REG(x) (((x) >> 2) | BUILD_BUG_ON_ZERO(x >= 0x200)) in set_offsets() argument
27 #define REG16(x) \ in set_offsets() argument
28 (((x) >> 9) | BIT(7) | BUILD_BUG_ON_ZERO(x >= 0x10000)), \ in set_offsets()
29 (((x) >> 2) & 0x7f) in set_offsets()
32 const u32 base = engine->mmio_base; in set_offsets()
50 if (GRAPHICS_VER(engine->i915) >= 11) in set_offsets()
67 } while (--count); in set_offsets()
73 if (GRAPHICS_VER(engine->i915) >= 11) in set_offsets()
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Dselftest_rps.c1 // SPDX-License-Identifier: MIT
22 #define CPU_LATENCY 0 /* -1 to disable pm_qos, 0 to disable cstates */
33 return -1; in cmp_u64()
45 return -1; in cmp_u32()
64 #define CS_GPR(x) GEN8_RING_CS_GPR(engine->mmio_base, x) in create_spin_counter() argument
68 u32 *base, *cs; in create_spin_counter() local
72 obj = i915_gem_object_create_internal(vm->i915, 64 << 10); in create_spin_counter()
76 end = obj->base.size / sizeof(u32) - 1; in create_spin_counter()
95 cs = base; in create_spin_counter()
97 *cs++ = MI_LOAD_REGISTER_IMM(__NGPR__ * 2); in create_spin_counter()
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Dintel_ring_submission.c1 // SPDX-License-Identifier: MIT
3 * Copyright © 2008-2021 Intel Corporation
22 * set-context and then emitting the batch.
32 if (engine->class == RENDER_CLASS) { in set_hwstam()
33 if (GRAPHICS_VER(engine->i915) >= 6) in set_hwstam()
47 if (GRAPHICS_VER(engine->i915) >= 4) in set_hws_pga()
50 intel_uncore_write(engine->uncore, HWS_PGA, addr); in set_hws_pga()
55 struct drm_i915_gem_object *obj = engine->status_page.vma->obj; in status_page()
58 return sg_page(obj->mm.pages->sgl); in status_page()
75 if (GRAPHICS_VER(engine->i915) == 7) { in set_hwsp()
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Dselftest_timeline.c1 // SPDX-License-Identifier: MIT
3 * Copyright © 2017-2018 Intel Corporation
27 struct drm_i915_gem_object *obj = tl->hwsp_ggtt->obj; in hwsp_page()
30 return sg_page(obj->mm.pages->sgl); in hwsp_page()
37 return (address + offset_in_page(tl->hwsp_offset)) / TIMELINE_SEQNO_BYTES; in hwsp_cacheline()
47 err = i915_gem_object_lock(tl->hwsp_ggtt->obj, &ww); in selftest_tl_pin()
51 if (err == -EDEADLK) { in selftest_tl_pin()
79 tl = xchg(&state->history[idx], tl); in __mock_hwsp_record()
81 radix_tree_delete(&state->cachelines, hwsp_cacheline(tl)); in __mock_hwsp_record()
94 while (count--) { in __mock_hwsp_timeline()
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/Linux-v5.15/drivers/memory/
Dti-aemif.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2010 - 2013 Texas Instruments Incorporated. http://www.ti.com/
8 * Murali Karicheri <m-karicheri2@ti.com>
20 #include <linux/platform_data/ti-aemif.h>
32 #define TA(x) ((x) << TA_SHIFT) argument
33 #define RHOLD(x) ((x) << RHOLD_SHIFT) argument
34 #define RSTROBE(x) ((x) << RSTROBE_SHIFT) argument
35 #define RSETUP(x) ((x) << RSETUP_SHIFT) argument
36 #define WHOLD(x) ((x) << WHOLD_SHIFT) argument
37 #define WSTROBE(x) ((x) << WSTROBE_SHIFT) argument
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Dstm32-fmc2-ebi.c1 // SPDX-License-Identifier: GPL-2.0
18 #define FMC2_BCR(x) ((x) * 0x8 + FMC2_BCR1) argument
19 #define FMC2_BTR(x) ((x) * 0x8 + FMC2_BTR1) argument
22 #define FMC2_BWTR(x) ((x) * 0x8 + FMC2_BWTR1) argument
57 #define FMC2_PCSCNTR_CNTBEN(x) BIT((x) + 16) argument
146 * struct stm32_fmc2_prop - STM32 FMC2 EBI property
170 const struct stm32_fmc2_prop *prop, int cs);
171 u32 (*calculate)(struct stm32_fmc2_ebi *ebi, int cs, u32 setup);
174 int cs, u32 setup);
179 int cs) in stm32_fmc2_ebi_check_mux() argument
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/Linux-v5.15/Documentation/gpu/rfc/
Di915_parallel_execbuf.h1 /* SPDX-License-Identifier: MIT */
9 * struct drm_i915_context_engines_parallel_submit - Configure engine for
30 * Returns -EINVAL if hardware context placement configuration is invalid or if
33 * Returns -ENODEV if extension isn't supported on the platform / submission
36 * .. code-block:: none
39 * CS[X] = generic engine of same class, logical instance X
43 * engines=CS[0],CS[1])
46 * CS[0], CS[1]
49 * CS[X] = generic engine of same class, logical instance X
53 * engines=CS[0],CS[2],CS[1],CS[3])
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/Linux-v5.15/drivers/net/slip/
Dslhc.c21 * - Initial distribution.
28 * - 01-31-90 initial adaptation (from 1.19)
29 * PPP.05 02-15-90 [ks]
30 * PPP.08 05-02-90 [ks] use PPP protocol field to signal compression
31 * PPP.15 09-90 [ks] improve mbuf handling
32 * PPP.16 11-02 [karn] substantially rewritten to use NOS facilities
34 * - Feb 1991 Bill_Simpson@um.cc.umich.edu
39 * - Jul 1994 Dmitry Gorodchanin
41 * - Oct 1994 Dmitry Gorodchanin
43 * - Jan 1995 Bjorn Ekwall
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/Linux-v5.15/include/linux/mfd/syscon/
Datmel-smc.h1 /* SPDX-License-Identifier: GPL-2.0 */
8 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
18 #define ATMEL_SMC_SETUP(cs) (((cs) * 0x10)) argument
19 #define ATMEL_HSMC_SETUP(layout, cs) \ argument
20 ((layout)->timing_regs_offset + ((cs) * 0x14))
21 #define ATMEL_SMC_PULSE(cs) (((cs) * 0x10) + 0x4) argument
22 #define ATMEL_HSMC_PULSE(layout, cs) \ argument
23 ((layout)->timing_regs_offset + ((cs) * 0x14) + 0x4)
24 #define ATMEL_SMC_CYCLE(cs) (((cs) * 0x10) + 0x8) argument
25 #define ATMEL_HSMC_CYCLE(layout, cs) \ argument
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/Linux-v5.15/drivers/scsi/
Dmyrs.c1 // SPDX-License-Identifier: GPL-2.0
5 * This driver supports the newer, SCSI-based firmware interface only.
10 * Copyright 1998-2001 by Leonard N. Zubkoff <lnz@dandelion.com>
91 * myrs_reset_cmd - clears critical fields in struct myrs_cmdblk
95 union myrs_cmd_mbox *mbox = &cmd_blk->mbox; in myrs_reset_cmd()
98 cmd_blk->status = 0; in myrs_reset_cmd()
102 * myrs_qcmd - queues Command for DAC960 V2 Series Controllers.
104 static void myrs_qcmd(struct myrs_hba *cs, struct myrs_cmdblk *cmd_blk) in myrs_qcmd() argument
106 void __iomem *base = cs->io_base; in myrs_qcmd()
107 union myrs_cmd_mbox *mbox = &cmd_blk->mbox; in myrs_qcmd()
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/Linux-v5.15/drivers/gpu/drm/i915/gvt/
Dmmio_context.c2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
165 struct intel_gvt *gvt = engine->i915->gvt; in load_render_mocs()
166 struct intel_uncore *uncore = engine->uncore; in load_render_mocs()
167 u32 cnt = gvt->engine_mmio_list.mocs_mmio_offset_list_cnt; in load_render_mocs()
168 u32 *regs = gvt->engine_mmio_list.mocs_mmio_offset_list; in load_render_mocs()
177 if (!HAS_ENGINE(engine->gt, ring_id)) in load_render_mocs()
201 u32 *cs; in restore_context_mmio_for_inhibit() local
204 struct intel_gvt *gvt = vgpu->gvt; in restore_context_mmio_for_inhibit()
205 int ring_id = req->engine->id; in restore_context_mmio_for_inhibit()
206 int count = gvt->engine_mmio_list.ctx_mmio_count[ring_id]; in restore_context_mmio_for_inhibit()
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/Linux-v5.15/drivers/gpu/drm/i915/gem/selftests/
Di915_gem_client_blt.c1 // SPDX-License-Identifier: MIT
44 const int ver = GRAPHICS_VER(to_i915(batch->base.dev)); in prepare_blit()
47 u32 cmd, *cs; in prepare_blit() local
49 cs = i915_gem_object_pin_map_unlocked(batch, I915_MAP_WC); in prepare_blit()
50 if (IS_ERR(cs)) in prepare_blit()
51 return PTR_ERR(cs); in prepare_blit()
53 *cs++ = MI_LOAD_REGISTER_IMM(1); in prepare_blit()
54 *cs++ = i915_mmio_reg_offset(BCS_SWCTRL); in prepare_blit()
56 if (src->tiling == I915_TILING_Y) in prepare_blit()
58 if (dst->tiling == I915_TILING_Y) in prepare_blit()
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/Linux-v5.15/drivers/spi/
Dspi-fsl-espi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
31 #define ESPI_SPMODEx(x) (ESPI_SPMODE0 + (x) * 4) argument
36 #define SPMODE_TXTHR(x) ((x) << 8) argument
37 #define SPMODE_RXTHR(x) ((x) << 0) argument
39 /* eSPI Controller CS mode register definitions */
44 #define CSMODE_PM(x) ((x) << 24) argument
46 #define CSMODE_LEN(x) ((x) << 16) argument
47 #define CSMODE_BEF(x) ((x) << 12) argument
48 #define CSMODE_AFT(x) ((x) << 8) argument
49 #define CSMODE_CG(x) ((x) << 3) argument
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Dspi-omap2-mcspi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
15 #include <linux/dma-mapping.h>
30 #include <linux/platform_data/spi-omap2-mcspi.h>
47 /* per-channel banks, 0x14 bytes each, first is: */
54 /* per-register bitmasks: */
90 /* We have 2 DMA channels per CS, one for RX and one for TX */
115 struct list_head cs; member
149 writel_relaxed(val, mcspi->base + idx); in mcspi_write_reg()
156 return readl_relaxed(mcspi->base + idx); in mcspi_read_reg()
162 struct omap2_mcspi_cs *cs = spi->controller_state; in mcspi_write_cs_reg() local
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/Linux-v5.15/Documentation/scsi/
DNinjaSCSI.rst1 .. SPDX-License-Identifier: GPL-2.0
4 WorkBiT NinjaSCSI-3/32Bi driver for Linux
10 This is Workbit corp.'s(http://www.workbit.co.jp/) NinjaSCSI-3
17 :pcmcia-cs: 3.1.27
18 :gcc: gcc-2.95.4
19 :PC card: I-O data PCSC-F (NinjaSCSI-3),
20 I-O data CBSC-II in 16 bit mode (NinjaSCSI-32Bi)
21 :SCSI device: I-O data CDPS-PX24 (CD-ROM drive),
22 Media Intelligent MMO-640GT (Optical disk drive)
27 (a) Check your PC card is true "NinjaSCSI-3" card.
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/Linux-v5.15/drivers/clocksource/
Dtimer-sun5i.c6 * Maxime Ripard <maxime.ripard@free-electrons.com>
48 #define to_sun5i_timer(x) \ argument
49 container_of(x, struct sun5i_timer, clk_rate_cb)
56 #define to_sun5i_timer_clksrc(x) \ argument
57 container_of(x, struct sun5i_timer_clksrc, clksrc)
64 #define to_sun5i_timer_clkevt(x) \ argument
65 container_of(x, struct sun5i_timer_clkevt, clkevt)
75 u32 old = readl(ce->timer.base + TIMER_CNTVAL_LO_REG(1)); in sun5i_clkevt_sync()
77 while ((old - readl(ce->timer.base + TIMER_CNTVAL_LO_REG(1))) < TIMER_SYNC_TICKS) in sun5i_clkevt_sync()
83 u32 val = readl(ce->timer.base + TIMER_CTL_REG(timer)); in sun5i_clkevt_time_stop()
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/Linux-v5.15/drivers/media/v4l2-core/
Dv4l2-ctrls-api.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2010-2021 Hans Verkuil <hverkuil-cisco@xs4all.nl>
8 #define pr_fmt(fmt) "v4l2-ctrls: " fmt
13 #include <media/v4l2-ctrls.h>
14 #include <media/v4l2-dev.h>
15 #include <media/v4l2-device.h>
16 #include <media/v4l2-event.h>
17 #include <media/v4l2-ioctl.h>
19 #include "v4l2-ctrls-priv.h"
46 if (ctrl->is_ptr && !ctrl->is_string) in ptr_to_user()
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/Linux-v5.15/arch/powerpc/include/asm/
Dmpc5121.h1 /* SPDX-License-Identifier: GPL-2.0-only */
50 u32 cs_cfg[8]; /* CS config */
51 u32 cs_ctrl; /* CS Control Register */
52 u32 cs_status; /* CS Status Register */
53 u32 burst_ctrl; /* CS Burst Control Register */
54 u32 deadcycle_ctrl; /* CS Deadcycle Control Register */
55 u32 holdcycle_ctrl; /* CS Holdcycle Control Register */
59 int mpc512x_cs_config(unsigned int cs, u32 val);
82 #define MPC512X_SCLPC_CS(x) (((x) & 0x7) << 24) argument
86 #define MPC512X_SCLPC_BPT(x) ((x) & 0x3f) argument
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/Linux-v5.15/drivers/ps3/
Dps3av_cmd.c1 // SPDX-License-Identifier: GPL-2.0-only
28 int cs; member
33 .cs = PS3AV_CMD_VIDEO_CS_RGB_8,
37 .cs = PS3AV_CMD_VIDEO_CS_RGB_10,
41 .cs = PS3AV_CMD_VIDEO_CS_RGB_12,
45 .cs = PS3AV_CMD_VIDEO_CS_YUV444_8,
49 .cs = PS3AV_CMD_VIDEO_CS_YUV444_10,
53 .cs = PS3AV_CMD_VIDEO_CS_YUV444_12,
57 .cs = PS3AV_CMD_VIDEO_CS_YUV422_8,
61 .cs = PS3AV_CMD_VIDEO_CS_YUV422_10,
[all …]
/Linux-v5.15/arch/x86/um/os-Linux/
Dmcontext.c1 // SPDX-License-Identifier: GPL-2.0
10 #define COPY2(X,Y) regs->gp[X] = mc->gregs[REG_##Y] in get_regs_from_mc() argument
11 #define COPY(X) regs->gp[X] = mc->gregs[REG_##X] in get_regs_from_mc() argument
12 #define COPY_SEG(X) regs->gp[X] = mc->gregs[REG_##X] & 0xffff; in get_regs_from_mc() argument
13 #define COPY_SEG_CPL3(X) regs->gp[X] = (mc->gregs[REG_##X] & 0xffff) | 3; in get_regs_from_mc() argument
18 COPY(EIP); COPY_SEG_CPL3(CS); COPY(EFL); COPY_SEG_CPL3(SS); in get_regs_from_mc()
20 #define COPY2(X,Y) regs->gp[X/sizeof(unsigned long)] = mc->gregs[REG_##Y] in get_regs_from_mc()
21 #define COPY(X) regs->gp[X/sizeof(unsigned long)] = mc->gregs[REG_##X] in get_regs_from_mc()
28 COPY2(CS, CSGSFS); in get_regs_from_mc()
29 regs->gp[CS / sizeof(unsigned long)] &= 0xffff; in get_regs_from_mc()
[all …]
/Linux-v5.15/drivers/edac/
Darmada_xp_edac.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <asm/hardware/cache-l2x0.h>
11 #include <asm/hardware/cache-aurora-l2.h>
27 #define SDRAM_ADDR_CTRL_SIZE_HIGH_OFFSET(cs) (20+cs) argument
28 #define SDRAM_ADDR_CTRL_SIZE_HIGH_MASK(cs) (0x1 << SDRAM_ADDR_CTRL_SIZE_HIGH_OFFSET(cs)) argument
29 #define SDRAM_ADDR_CTRL_ADDR_SEL_MASK(cs) BIT(16+cs) argument
30 #define SDRAM_ADDR_CTRL_SIZE_LOW_OFFSET(cs) (cs*4+2) argument
31 #define SDRAM_ADDR_CTRL_SIZE_LOW_MASK(cs) (0x3 << SDRAM_ADDR_CTRL_SIZE_LOW_OFFSET(cs)) argument
32 #define SDRAM_ADDR_CTRL_STRUCT_OFFSET(cs) (cs*4) argument
33 #define SDRAM_ADDR_CTRL_STRUCT_MASK(cs) (0x3 << SDRAM_ADDR_CTRL_STRUCT_OFFSET(cs)) argument
[all …]
/Linux-v5.15/drivers/mtd/spi-nor/controllers/
Daspeed-smc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (c) 2015-2016, IBM Corporation.
15 #include <linux/mtd/spi-nor.h>
21 #define DEVICE_NAME "aspeed-smc"
93 int cs; member
109 void __iomem *ahb_base; /* per-chip windows resource */
189 * +--------+--------+--------+--------+
197 #define SEGMENT_ADDR_REG(controller, cs) \ argument
198 ((controller)->regs + SEGMENT_ADDR_REG0 + (cs) * 4)
235 len -= offset; in aspeed_smc_read_from_ahb()
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