Lines Matching +full:cs +full:- +full:x
1 // SPDX-License-Identifier: MIT
22 #define CPU_LATENCY 0 /* -1 to disable pm_qos, 0 to disable cstates */
33 return -1; in cmp_u64()
45 return -1; in cmp_u32()
64 #define CS_GPR(x) GEN8_RING_CS_GPR(engine->mmio_base, x) in create_spin_counter() argument
68 u32 *base, *cs; in create_spin_counter() local
72 obj = i915_gem_object_create_internal(vm->i915, 64 << 10); in create_spin_counter()
76 end = obj->base.size / sizeof(u32) - 1; in create_spin_counter()
95 cs = base; in create_spin_counter()
97 *cs++ = MI_LOAD_REGISTER_IMM(__NGPR__ * 2); in create_spin_counter()
99 *cs++ = i915_mmio_reg_offset(CS_GPR(i)); in create_spin_counter()
100 *cs++ = 0; in create_spin_counter()
101 *cs++ = i915_mmio_reg_offset(CS_GPR(i)) + 4; in create_spin_counter()
102 *cs++ = 0; in create_spin_counter()
105 *cs++ = MI_LOAD_REGISTER_IMM(1); in create_spin_counter()
106 *cs++ = i915_mmio_reg_offset(CS_GPR(INC)); in create_spin_counter()
107 *cs++ = 1; in create_spin_counter()
109 loop = cs - base; in create_spin_counter()
113 *cs++ = MI_MATH(4); in create_spin_counter()
114 *cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCA, MI_MATH_REG(COUNT)); in create_spin_counter()
115 *cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCB, MI_MATH_REG(INC)); in create_spin_counter()
116 *cs++ = MI_MATH_ADD; in create_spin_counter()
117 *cs++ = MI_MATH_STORE(MI_MATH_REG(COUNT), MI_MATH_REG_ACCU); in create_spin_counter()
120 *cs++ = MI_STORE_REGISTER_MEM_GEN8; in create_spin_counter()
121 *cs++ = i915_mmio_reg_offset(CS_GPR(COUNT)); in create_spin_counter()
122 *cs++ = lower_32_bits(vma->node.start + end * sizeof(*cs)); in create_spin_counter()
123 *cs++ = upper_32_bits(vma->node.start + end * sizeof(*cs)); in create_spin_counter()
127 *cs++ = MI_BATCH_BUFFER_START_GEN8; in create_spin_counter()
128 *cs++ = lower_32_bits(vma->node.start + loop * sizeof(*cs)); in create_spin_counter()
129 *cs++ = upper_32_bits(vma->node.start + loop * sizeof(*cs)); in create_spin_counter()
130 GEM_BUG_ON(cs - base > end); in create_spin_counter()
186 mutex_lock(&rps->lock); in rps_set_check()
189 mutex_unlock(&rps->lock); in rps_set_check()
192 GEM_BUG_ON(rps->last_freq != freq); in rps_set_check()
193 mutex_unlock(&rps->lock); in rps_set_check()
203 pr_info("P_STATE_CAP[%x]: 0x%08x\n", in show_pstate_limits()
208 pr_info("P_STATE_LIMITS[%x]: 0x%08x\n", in show_pstate_limits()
218 struct intel_rps *rps = >->rps; in live_rps_clock_interval()
225 if (!intel_rps_is_enabled(rps) || GRAPHICS_VER(gt->i915) < 6) in live_rps_clock_interval()
229 return -ENOMEM; in live_rps_clock_interval()
232 saved_work = rps->work.func; in live_rps_clock_interval()
233 rps->work.func = dummy_rps_work; in live_rps_clock_interval()
236 intel_rps_disable(>->rps); in live_rps_clock_interval()
251 engine->kernel_context, in live_rps_clock_interval()
263 engine->name); in live_rps_clock_interval()
266 intel_gt_set_wedged(engine->gt); in live_rps_clock_interval()
267 err = -EIO; in live_rps_clock_interval()
271 intel_uncore_forcewake_get(gt->uncore, FORCEWAKE_ALL); in live_rps_clock_interval()
273 intel_uncore_write_fw(gt->uncore, GEN6_RP_CUR_UP_EI, 0); in live_rps_clock_interval()
276 intel_uncore_write_fw(gt->uncore, in live_rps_clock_interval()
278 intel_uncore_write_fw(gt->uncore, in live_rps_clock_interval()
281 intel_uncore_write_fw(gt->uncore, GEN6_RP_CONTROL, in live_rps_clock_interval()
284 if (wait_for(intel_uncore_read_fw(gt->uncore, in live_rps_clock_interval()
289 engine->name); in live_rps_clock_interval()
290 err = -ENODEV; in live_rps_clock_interval()
300 cycles_[i] = -intel_uncore_read_fw(gt->uncore, GEN6_RP_CUR_UP_EI); in live_rps_clock_interval()
305 cycles_[i] += intel_uncore_read_fw(gt->uncore, GEN6_RP_CUR_UP_EI); in live_rps_clock_interval()
317 intel_uncore_write_fw(gt->uncore, GEN6_RP_CONTROL, 0); in live_rps_clock_interval()
318 intel_uncore_forcewake_put(gt->uncore, FORCEWAKE_ALL); in live_rps_clock_interval()
329 engine->name, cycles, time, dt, expected, in live_rps_clock_interval()
330 gt->clock_frequency / 1000); in live_rps_clock_interval()
335 engine->name); in live_rps_clock_interval()
336 err = -EINVAL; in live_rps_clock_interval()
342 engine->name); in live_rps_clock_interval()
343 err = -EINVAL; in live_rps_clock_interval()
347 if (igt_flush_test(gt->i915)) in live_rps_clock_interval()
348 err = -EIO; in live_rps_clock_interval()
353 intel_rps_enable(>->rps); in live_rps_clock_interval()
359 rps->work.func = saved_work; in live_rps_clock_interval()
361 if (err == -ENODEV) /* skipped, don't report a fail */ in live_rps_clock_interval()
370 struct intel_rps *rps = >->rps; in live_rps_control()
387 if (IS_CHERRYVIEW(gt->i915)) /* XXX fragile PCU */ in live_rps_control()
391 return -ENOMEM; in live_rps_control()
394 saved_work = rps->work.func; in live_rps_control()
395 rps->work.func = dummy_rps_work; in live_rps_control()
410 engine->kernel_context, in live_rps_control()
421 engine->name); in live_rps_control()
424 intel_gt_set_wedged(engine->gt); in live_rps_control()
425 err = -EIO; in live_rps_control()
429 if (rps_set_check(rps, rps->min_freq) != rps->min_freq) { in live_rps_control()
430 pr_err("%s: could not set minimum frequency [%x], only %x!\n", in live_rps_control()
431 engine->name, rps->min_freq, read_cagf(rps)); in live_rps_control()
435 err = -EINVAL; in live_rps_control()
439 for (f = rps->min_freq + 1; f < rps->max_freq; f++) { in live_rps_control()
446 if (rps_set_check(rps, rps->min_freq) != rps->min_freq) { in live_rps_control()
447 pr_err("%s: could not restore minimum frequency [%x], only %x!\n", in live_rps_control()
448 engine->name, rps->min_freq, read_cagf(rps)); in live_rps_control()
452 err = -EINVAL; in live_rps_control()
461 min = rps_set_check(rps, rps->min_freq); in live_rps_control()
467 pr_info("%s: range:[%x:%uMHz, %x:%uMHz] limit:[%x:%uMHz], %x:%x response %lluns:%lluns\n", in live_rps_control()
468 engine->name, in live_rps_control()
469 rps->min_freq, intel_gpu_freq(rps, rps->min_freq), in live_rps_control()
470 rps->max_freq, intel_gpu_freq(rps, rps->max_freq), in live_rps_control()
474 if (limit == rps->min_freq) { in live_rps_control()
476 engine->name); in live_rps_control()
478 err = -ENODEV; in live_rps_control()
482 if (igt_flush_test(gt->i915)) { in live_rps_control()
483 err = -EIO; in live_rps_control()
492 rps->work.func = saved_work; in live_rps_control()
507 min_gpu_freq = rps->min_freq; in show_pcu_config()
508 max_gpu_freq = rps->max_freq; in show_pcu_config()
515 wakeref = intel_runtime_pm_get(rps_to_uncore(rps)->rpm); in show_pcu_config()
531 intel_runtime_pm_put(rps_to_uncore(rps)->rpm, wakeref); in show_pcu_config()
541 dc = READ_ONCE(*cntr) - dc; in __measure_frequency()
542 dt = ktime_get() - dt; in __measure_frequency()
549 u64 x[5]; in measure_frequency_at() local
554 x[i] = __measure_frequency(cntr, 2); in measure_frequency_at()
558 sort(x, 5, sizeof(*x), cmp_u64, NULL); in measure_frequency_at()
559 return div_u64(x[1] + 2 * x[2] + x[3], 4); in measure_frequency_at()
568 dc = intel_uncore_read_fw(engine->uncore, CS_GPR(0)); in __measure_cs_frequency()
570 dc = intel_uncore_read_fw(engine->uncore, CS_GPR(0)) - dc; in __measure_cs_frequency()
571 dt = ktime_get() - dt; in __measure_cs_frequency()
580 u64 x[5]; in measure_cs_frequency_at() local
585 x[i] = __measure_cs_frequency(engine, 2); in measure_cs_frequency_at()
589 sort(x, 5, sizeof(*x), cmp_u64, NULL); in measure_cs_frequency_at()
590 return div_u64(x[1] + 2 * x[2] + x[3], 4); in measure_cs_frequency_at()
593 static bool scaled_within(u64 x, u64 y, u32 f_n, u32 f_d) in scaled_within() argument
595 return f_d * x > f_n * y && f_n * x < f_d * y; in scaled_within()
602 struct intel_rps *rps = >->rps; in live_rps_frequency_cs()
617 if (GRAPHICS_VER(gt->i915) < 8) /* for CS simplicity */ in live_rps_frequency_cs()
624 saved_work = rps->work.func; in live_rps_frequency_cs()
625 rps->work.func = dummy_rps_work; in live_rps_frequency_cs()
639 engine->kernel_context->vm, false, in live_rps_frequency_cs()
653 err = i915_request_await_object(rq, vma->obj, false); in live_rps_frequency_cs()
657 err = rq->engine->emit_bb_start(rq, in live_rps_frequency_cs()
658 vma->node.start, in live_rps_frequency_cs()
664 if (wait_for(intel_uncore_read(engine->uncore, CS_GPR(0)), in live_rps_frequency_cs()
667 engine->name); in live_rps_frequency_cs()
671 min.freq = rps->min_freq; in live_rps_frequency_cs()
674 max.freq = rps->max_freq; in live_rps_frequency_cs()
678 engine->name, in live_rps_frequency_cs()
689 pr_err("%s: CS did not scale with frequency! scaled min:%llu, max:%llu\n", in live_rps_frequency_cs()
690 engine->name, in live_rps_frequency_cs()
695 for (f = min.freq + 1; f <= rps->max_freq; f++) { in live_rps_frequency_cs()
703 pr_info("%s: %x:%uMHz: %lluKHz [%d%%]\n", in live_rps_frequency_cs()
704 engine->name, in live_rps_frequency_cs()
712 err = -EINTR; /* ignore error, continue on with test */ in live_rps_frequency_cs()
717 i915_gem_object_flush_map(vma->obj); in live_rps_frequency_cs()
718 i915_gem_object_unpin_map(vma->obj); in live_rps_frequency_cs()
724 if (igt_flush_test(gt->i915)) in live_rps_frequency_cs()
725 err = -EIO; in live_rps_frequency_cs()
731 rps->work.func = saved_work; in live_rps_frequency_cs()
743 struct intel_rps *rps = >->rps; in live_rps_frequency_srm()
758 if (GRAPHICS_VER(gt->i915) < 8) /* for CS simplicity */ in live_rps_frequency_srm()
765 saved_work = rps->work.func; in live_rps_frequency_srm()
766 rps->work.func = dummy_rps_work; in live_rps_frequency_srm()
780 engine->kernel_context->vm, true, in live_rps_frequency_srm()
794 err = i915_request_await_object(rq, vma->obj, false); in live_rps_frequency_srm()
798 err = rq->engine->emit_bb_start(rq, in live_rps_frequency_srm()
799 vma->node.start, in live_rps_frequency_srm()
807 engine->name); in live_rps_frequency_srm()
811 min.freq = rps->min_freq; in live_rps_frequency_srm()
814 max.freq = rps->max_freq; in live_rps_frequency_srm()
818 engine->name, in live_rps_frequency_srm()
829 pr_err("%s: CS did not scale with frequency! scaled min:%llu, max:%llu\n", in live_rps_frequency_srm()
830 engine->name, in live_rps_frequency_srm()
835 for (f = min.freq + 1; f <= rps->max_freq; f++) { in live_rps_frequency_srm()
843 pr_info("%s: %x:%uMHz: %lluKHz [%d%%]\n", in live_rps_frequency_srm()
844 engine->name, in live_rps_frequency_srm()
852 err = -EINTR; /* ignore error, continue on with test */ in live_rps_frequency_srm()
857 i915_gem_object_flush_map(vma->obj); in live_rps_frequency_srm()
858 i915_gem_object_unpin_map(vma->obj); in live_rps_frequency_srm()
864 if (igt_flush_test(gt->i915)) in live_rps_frequency_srm()
865 err = -EIO; in live_rps_frequency_srm()
871 rps->work.func = saved_work; in live_rps_frequency_srm()
886 GEM_BUG_ON(rps->pm_iir); in sleep_for_ei()
897 struct intel_uncore *uncore = engine->uncore; in __rps_up_interrupt()
904 rps_set_check(rps, rps->min_freq); in __rps_up_interrupt()
906 rq = igt_spinner_create_request(spin, engine->kernel_context, MI_NOOP); in __rps_up_interrupt()
915 engine->name); in __rps_up_interrupt()
917 intel_gt_set_wedged(engine->gt); in __rps_up_interrupt()
918 return -EIO; in __rps_up_interrupt()
923 engine->name); in __rps_up_interrupt()
926 return -EINVAL; in __rps_up_interrupt()
929 if (!(rps->pm_events & GEN6_PM_RP_UP_THRESHOLD)) { in __rps_up_interrupt()
931 engine->name); in __rps_up_interrupt()
933 return -EINVAL; in __rps_up_interrupt()
936 if (rps->last_freq != rps->min_freq) { in __rps_up_interrupt()
938 engine->name); in __rps_up_interrupt()
940 return -EINVAL; in __rps_up_interrupt()
944 timeout = intel_gt_pm_interval_to_ns(engine->gt, timeout); in __rps_up_interrupt()
953 if (rps->cur_freq != rps->min_freq) { in __rps_up_interrupt()
955 engine->name, intel_rps_read_actual_frequency(rps)); in __rps_up_interrupt()
956 return -EINVAL; in __rps_up_interrupt()
959 if (!(rps->pm_iir & GEN6_PM_RP_UP_THRESHOLD)) { in __rps_up_interrupt()
960 …err("%s: UP interrupt not recorded for spinner, pm_iir:%x, prev_up:%x, up_threshold:%x, up_ei:%x\n… in __rps_up_interrupt()
961 engine->name, rps->pm_iir, in __rps_up_interrupt()
965 return -EINVAL; in __rps_up_interrupt()
974 struct intel_uncore *uncore = engine->uncore; in __rps_down_interrupt()
977 rps_set_check(rps, rps->max_freq); in __rps_down_interrupt()
979 if (!(rps->pm_events & GEN6_PM_RP_DOWN_THRESHOLD)) { in __rps_down_interrupt()
981 engine->name); in __rps_down_interrupt()
982 return -EINVAL; in __rps_down_interrupt()
985 if (rps->last_freq != rps->max_freq) { in __rps_down_interrupt()
987 engine->name); in __rps_down_interrupt()
988 return -EINVAL; in __rps_down_interrupt()
992 timeout = intel_gt_pm_interval_to_ns(engine->gt, timeout); in __rps_down_interrupt()
997 if (rps->cur_freq != rps->max_freq) { in __rps_down_interrupt()
999 engine->name, in __rps_down_interrupt()
1001 return -EINVAL; in __rps_down_interrupt()
1004 if (!(rps->pm_iir & (GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT))) { in __rps_down_interrupt()
1005 …pt not recorded for idle, pm_iir:%x, prev_down:%x, down_threshold:%x, down_ei:%x [prev_up:%x, up_t… in __rps_down_interrupt()
1006 engine->name, rps->pm_iir, in __rps_down_interrupt()
1013 return -EINVAL; in __rps_down_interrupt()
1022 struct intel_rps *rps = >->rps; in live_rps_interrupt()
1034 if (!intel_rps_has_interrupts(rps) || GRAPHICS_VER(gt->i915) < 6) in live_rps_interrupt()
1038 pm_events = rps->pm_events; in live_rps_interrupt()
1042 return -ENODEV; in live_rps_interrupt()
1046 return -ENOMEM; in live_rps_interrupt()
1049 saved_work = rps->work.func; in live_rps_interrupt()
1050 rps->work.func = dummy_rps_work; in live_rps_interrupt()
1055 intel_gt_pm_wait_for_idle(engine->gt); in live_rps_interrupt()
1066 intel_gt_pm_wait_for_idle(engine->gt); in live_rps_interrupt()
1072 intel_rc6_disable(>->rc6); in live_rps_interrupt()
1076 intel_rc6_enable(>->rc6); in live_rps_interrupt()
1084 if (igt_flush_test(gt->i915)) in live_rps_interrupt()
1085 err = -EIO; in live_rps_interrupt()
1090 rps->work.func = saved_work; in live_rps_interrupt()
1102 dE = librapl_energy_uJ() - dE; in __measure_power()
1103 dt = ktime_get() - dt; in __measure_power()
1110 u64 x[5]; in measure_power_at() local
1115 x[i] = __measure_power(5); in measure_power_at()
1119 sort(x, 5, sizeof(*x), cmp_u64, NULL); in measure_power_at()
1120 return div_u64(x[1] + 2 * x[2] + x[3], 4); in measure_power_at()
1126 struct intel_rps *rps = >->rps; in live_rps_power()
1139 if (!intel_rps_is_enabled(rps) || GRAPHICS_VER(gt->i915) < 6) in live_rps_power()
1142 if (!librapl_supported(gt->i915)) in live_rps_power()
1146 return -ENOMEM; in live_rps_power()
1149 saved_work = rps->work.func; in live_rps_power()
1150 rps->work.func = dummy_rps_work; in live_rps_power()
1165 engine->kernel_context, in live_rps_power()
1177 engine->name); in live_rps_power()
1180 intel_gt_set_wedged(engine->gt); in live_rps_power()
1181 err = -EIO; in live_rps_power()
1185 max.freq = rps->max_freq; in live_rps_power()
1188 min.freq = rps->min_freq; in live_rps_power()
1195 engine->name, in live_rps_power()
1208 engine->name); in live_rps_power()
1209 err = -EINVAL; in live_rps_power()
1213 if (igt_flush_test(gt->i915)) { in live_rps_power()
1214 err = -EIO; in live_rps_power()
1222 rps->work.func = saved_work; in live_rps_power()
1230 struct intel_rps *rps = >->rps; in live_rps_dynamic()
1243 if (!intel_rps_is_enabled(rps) || GRAPHICS_VER(gt->i915) < 6) in live_rps_dynamic()
1247 return -ENOMEM; in live_rps_dynamic()
1266 rps->cur_freq = rps->min_freq; in live_rps_dynamic()
1269 intel_rc6_disable(>->rc6); in live_rps_dynamic()
1270 GEM_BUG_ON(rps->last_freq != rps->min_freq); in live_rps_dynamic()
1273 engine->kernel_context, in live_rps_dynamic()
1283 max.freq = wait_for_freq(rps, rps->max_freq, 500); in live_rps_dynamic()
1289 min.freq = wait_for_freq(rps, rps->min_freq, 2000); in live_rps_dynamic()
1293 engine->name, in live_rps_dynamic()
1300 engine->name); in live_rps_dynamic()
1301 err = -EINVAL; in live_rps_dynamic()
1305 intel_rc6_enable(>->rc6); in live_rps_dynamic()
1308 if (igt_flush_test(gt->i915)) in live_rps_dynamic()
1309 err = -EIO; in live_rps_dynamic()