Lines Matching +full:cs +full:- +full:x
1 // SPDX-License-Identifier: MIT
24 #define CS_GPR(engine, n) ((engine)->mmio_base + 0x600 + (n) * 4)
30 return __vm_create_scratch_for_read_pinned(>->ggtt->vm, PAGE_SIZE); in create_scratch()
52 tasklet_hi_schedule(&engine->sched_engine->tasklet); in wait_for_submit()
63 if (!READ_ONCE(engine->execlists.pending[0]) && is_active(rq)) in wait_for_submit()
67 return -ETIME; in wait_for_submit()
76 i915_ggtt_offset(ce->engine->status_page.vma) + in emit_semaphore_signal()
79 u32 *cs; in emit_semaphore_signal() local
85 cs = intel_ring_begin(rq, 4); in emit_semaphore_signal()
86 if (IS_ERR(cs)) { in emit_semaphore_signal()
88 return PTR_ERR(cs); in emit_semaphore_signal()
91 *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT; in emit_semaphore_signal()
92 *cs++ = offset; in emit_semaphore_signal()
93 *cs++ = 0; in emit_semaphore_signal()
94 *cs++ = 1; in emit_semaphore_signal()
96 intel_ring_advance(rq, cs); in emit_semaphore_signal()
98 rq->sched.attr.priority = I915_PRIORITY_BARRIER; in emit_semaphore_signal()
109 rq = intel_engine_create_kernel_request(ce->engine); in context_flush()
113 fence = i915_active_fence_get(&ce->timeline->last_request); in context_flush()
122 err = -ETIME; in context_flush()
144 return -ENOMEM; in live_lrc_layout()
152 if (!engine->default_state) in live_lrc_layout()
155 hw = shmem_pin_map(engine->default_state); in live_lrc_layout()
163 engine->kernel_context, engine, true); in live_lrc_layout()
175 pr_debug("%s: skipped instruction %x at dword %d\n", in live_lrc_layout()
176 engine->name, lri, dw); in live_lrc_layout()
182 pr_err("%s: Expected LRI command at dword %d, found %08x\n", in live_lrc_layout()
183 engine->name, dw, lri); in live_lrc_layout()
184 err = -EINVAL; in live_lrc_layout()
189 pr_err("%s: LRI command mismatch at dword %d, expected %08x found %08x\n", in live_lrc_layout()
190 engine->name, dw, lri, lrc[dw]); in live_lrc_layout()
191 err = -EINVAL; in live_lrc_layout()
203 pr_err("%s: Different registers found at dword %d, expected %x, found %x\n", in live_lrc_layout()
204 engine->name, dw, offset, lrc[dw]); in live_lrc_layout()
205 err = -EINVAL; in live_lrc_layout()
214 lri -= 2; in live_lrc_layout()
219 pr_info("%s: HW register image:\n", engine->name); in live_lrc_layout()
222 pr_info("%s: SW register image:\n", engine->name); in live_lrc_layout()
226 shmem_unpin_map(engine->default_state, hw); in live_lrc_layout()
243 return -1; in find_offset()
265 i915_mmio_reg_offset(RING_START(engine->mmio_base)), in live_lrc_fixed()
266 CTX_RING_START - 1, in live_lrc_fixed()
270 i915_mmio_reg_offset(RING_CTL(engine->mmio_base)), in live_lrc_fixed()
271 CTX_RING_CTL - 1, in live_lrc_fixed()
275 i915_mmio_reg_offset(RING_HEAD(engine->mmio_base)), in live_lrc_fixed()
276 CTX_RING_HEAD - 1, in live_lrc_fixed()
280 i915_mmio_reg_offset(RING_TAIL(engine->mmio_base)), in live_lrc_fixed()
281 CTX_RING_TAIL - 1, in live_lrc_fixed()
285 i915_mmio_reg_offset(RING_MI_MODE(engine->mmio_base)), in live_lrc_fixed()
290 i915_mmio_reg_offset(RING_BBSTATE(engine->mmio_base)), in live_lrc_fixed()
291 CTX_BB_STATE - 1, in live_lrc_fixed()
295 i915_mmio_reg_offset(RING_BB_PER_CTX_PTR(engine->mmio_base)), in live_lrc_fixed()
300 i915_mmio_reg_offset(RING_INDIRECT_CTX(engine->mmio_base)), in live_lrc_fixed()
305 i915_mmio_reg_offset(RING_INDIRECT_CTX_OFFSET(engine->mmio_base)), in live_lrc_fixed()
310 i915_mmio_reg_offset(RING_CTX_TIMESTAMP(engine->mmio_base)), in live_lrc_fixed()
311 CTX_TIMESTAMP - 1, in live_lrc_fixed()
315 i915_mmio_reg_offset(GEN8_RING_CS_GPR(engine->mmio_base, 0)), in live_lrc_fixed()
320 i915_mmio_reg_offset(RING_CMD_BUF_CCTL(engine->mmio_base)), in live_lrc_fixed()
328 if (!engine->default_state) in live_lrc_fixed()
331 hw = shmem_pin_map(engine->default_state); in live_lrc_fixed()
338 for (t = tbl; t->name; t++) { in live_lrc_fixed()
339 int dw = find_offset(hw, t->reg); in live_lrc_fixed()
341 if (dw != t->offset) { in live_lrc_fixed()
342 pr_err("%s: Offset for %s [0x%x] mismatch, found %x, expected %x\n", in live_lrc_fixed()
343 engine->name, in live_lrc_fixed()
344 t->name, in live_lrc_fixed()
345 t->reg, in live_lrc_fixed()
347 t->offset); in live_lrc_fixed()
348 err = -EINVAL; in live_lrc_fixed()
352 shmem_unpin_map(engine->default_state, hw); in live_lrc_fixed()
370 u32 *cs; in __live_lrc_state() local
380 err = i915_gem_object_lock(scratch->obj, &ww); in __live_lrc_state()
392 cs = intel_ring_begin(rq, 4 * MAX_IDX); in __live_lrc_state()
393 if (IS_ERR(cs)) { in __live_lrc_state()
394 err = PTR_ERR(cs); in __live_lrc_state()
399 *cs++ = MI_STORE_REGISTER_MEM_GEN8 | MI_USE_GGTT; in __live_lrc_state()
400 *cs++ = i915_mmio_reg_offset(RING_START(engine->mmio_base)); in __live_lrc_state()
401 *cs++ = i915_ggtt_offset(scratch) + RING_START_IDX * sizeof(u32); in __live_lrc_state()
402 *cs++ = 0; in __live_lrc_state()
404 expected[RING_START_IDX] = i915_ggtt_offset(ce->ring->vma); in __live_lrc_state()
406 *cs++ = MI_STORE_REGISTER_MEM_GEN8 | MI_USE_GGTT; in __live_lrc_state()
407 *cs++ = i915_mmio_reg_offset(RING_TAIL(engine->mmio_base)); in __live_lrc_state()
408 *cs++ = i915_ggtt_offset(scratch) + RING_TAIL_IDX * sizeof(u32); in __live_lrc_state()
409 *cs++ = 0; in __live_lrc_state()
411 err = i915_request_await_object(rq, scratch->obj, true); in __live_lrc_state()
421 expected[RING_TAIL_IDX] = ce->ring->tail; in __live_lrc_state()
424 err = -ETIME; in __live_lrc_state()
428 cs = i915_gem_object_pin_map(scratch->obj, I915_MAP_WB); in __live_lrc_state()
429 if (IS_ERR(cs)) { in __live_lrc_state()
430 err = PTR_ERR(cs); in __live_lrc_state()
435 if (cs[n] != expected[n]) { in __live_lrc_state()
436 pr_err("%s: Stored register[%d] value[0x%x] did not match expected[0x%x]\n", in __live_lrc_state()
437 engine->name, n, cs[n], expected[n]); in __live_lrc_state()
438 err = -EINVAL; in __live_lrc_state()
443 i915_gem_object_unpin_map(scratch->obj); in __live_lrc_state()
450 if (err == -EDEADLK) { in __live_lrc_state()
483 if (igt_flush_test(gt->i915)) in live_lrc_state()
484 err = -EIO; in live_lrc_state()
493 u32 *cs; in gpr_make_dirty() local
500 cs = intel_ring_begin(rq, 2 * NUM_GPR_DW + 2); in gpr_make_dirty()
501 if (IS_ERR(cs)) { in gpr_make_dirty()
503 return PTR_ERR(cs); in gpr_make_dirty()
506 *cs++ = MI_LOAD_REGISTER_IMM(NUM_GPR_DW); in gpr_make_dirty()
508 *cs++ = CS_GPR(ce->engine, n); in gpr_make_dirty()
509 *cs++ = STACK_MAGIC; in gpr_make_dirty()
511 *cs++ = MI_NOOP; in gpr_make_dirty()
513 intel_ring_advance(rq, cs); in gpr_make_dirty()
515 rq->sched.attr.priority = I915_PRIORITY_BARRIER; in gpr_make_dirty()
525 i915_ggtt_offset(ce->engine->status_page.vma) + in __gpr_read()
528 u32 *cs; in __gpr_read() local
536 cs = intel_ring_begin(rq, 6 + 4 * NUM_GPR_DW); in __gpr_read()
537 if (IS_ERR(cs)) { in __gpr_read()
539 return ERR_CAST(cs); in __gpr_read()
542 *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE; in __gpr_read()
543 *cs++ = MI_NOOP; in __gpr_read()
545 *cs++ = MI_SEMAPHORE_WAIT | in __gpr_read()
549 *cs++ = 0; in __gpr_read()
550 *cs++ = offset; in __gpr_read()
551 *cs++ = 0; in __gpr_read()
554 *cs++ = MI_STORE_REGISTER_MEM_GEN8 | MI_USE_GGTT; in __gpr_read()
555 *cs++ = CS_GPR(ce->engine, n); in __gpr_read()
556 *cs++ = i915_ggtt_offset(scratch) + n * sizeof(u32); in __gpr_read()
557 *cs++ = 0; in __gpr_read()
561 err = i915_request_await_object(rq, scratch->obj, true); in __gpr_read()
580 u32 *slot = memset32(engine->status_page.addr + 1000, 0, 4); in __live_lrc_gpr()
583 u32 *cs; in __live_lrc_gpr() local
587 if (GRAPHICS_VER(engine->i915) < 9 && engine->class != RENDER_CLASS) in __live_lrc_gpr()
590 err = gpr_make_dirty(engine->kernel_context); in __live_lrc_gpr()
609 err = gpr_make_dirty(engine->kernel_context); in __live_lrc_gpr()
613 err = emit_semaphore_signal(engine->kernel_context, slot); in __live_lrc_gpr()
626 err = -ETIME; in __live_lrc_gpr()
630 cs = i915_gem_object_pin_map_unlocked(scratch->obj, I915_MAP_WB); in __live_lrc_gpr()
631 if (IS_ERR(cs)) { in __live_lrc_gpr()
632 err = PTR_ERR(cs); in __live_lrc_gpr()
637 if (cs[n]) { in __live_lrc_gpr()
638 pr_err("%s: GPR[%d].%s was not zero, found 0x%08x!\n", in __live_lrc_gpr()
639 engine->name, in __live_lrc_gpr()
641 cs[n]); in __live_lrc_gpr()
642 err = -EINVAL; in __live_lrc_gpr()
647 i915_gem_object_unpin_map(scratch->obj); in __live_lrc_gpr()
650 memset32(&slot[0], -1, 4); in __live_lrc_gpr()
688 if (igt_flush_test(gt->i915)) in live_lrc_gpr()
689 err = -EIO; in live_lrc_gpr()
702 i915_ggtt_offset(ce->engine->status_page.vma) + in create_timestamp()
705 u32 *cs; in create_timestamp() local
712 cs = intel_ring_begin(rq, 10); in create_timestamp()
713 if (IS_ERR(cs)) { in create_timestamp()
714 err = PTR_ERR(cs); in create_timestamp()
718 *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE; in create_timestamp()
719 *cs++ = MI_NOOP; in create_timestamp()
721 *cs++ = MI_SEMAPHORE_WAIT | in create_timestamp()
725 *cs++ = 0; in create_timestamp()
726 *cs++ = offset; in create_timestamp()
727 *cs++ = 0; in create_timestamp()
729 *cs++ = MI_STORE_REGISTER_MEM_GEN8 | MI_USE_GGTT; in create_timestamp()
730 *cs++ = i915_mmio_reg_offset(RING_CTX_TIMESTAMP(rq->engine->mmio_base)); in create_timestamp()
731 *cs++ = offset + idx * sizeof(u32); in create_timestamp()
732 *cs++ = 0; in create_timestamp()
734 intel_ring_advance(rq, cs); in create_timestamp()
756 return (s32)(end - start) > 0; in timestamp_advanced()
761 u32 *slot = memset32(arg->engine->status_page.addr + 1000, 0, 4); in __lrc_timestamp()
766 arg->ce[0]->lrc_reg_state[CTX_TIMESTAMP] = arg->poison; in __lrc_timestamp()
767 rq = create_timestamp(arg->ce[0], slot, 1); in __lrc_timestamp()
771 err = wait_for_submit(rq->engine, rq, HZ / 2); in __lrc_timestamp()
776 arg->ce[1]->lrc_reg_state[CTX_TIMESTAMP] = 0xdeadbeef; in __lrc_timestamp()
777 err = emit_semaphore_signal(arg->ce[1], slot); in __lrc_timestamp()
786 err = context_flush(arg->ce[0], HZ / 2); in __lrc_timestamp()
790 if (!timestamp_advanced(arg->poison, slot[1])) { in __lrc_timestamp()
791 pr_err("%s(%s): invalid timestamp on restore, context:%x, request:%x\n", in __lrc_timestamp()
792 arg->engine->name, preempt ? "preempt" : "simple", in __lrc_timestamp()
793 arg->poison, slot[1]); in __lrc_timestamp()
794 err = -EINVAL; in __lrc_timestamp()
797 timestamp = READ_ONCE(arg->ce[0]->lrc_reg_state[CTX_TIMESTAMP]); in __lrc_timestamp()
799 pr_err("%s(%s): invalid timestamp on save, request:%x, context:%x\n", in __lrc_timestamp()
800 arg->engine->name, preempt ? "preempt" : "simple", in __lrc_timestamp()
802 err = -EINVAL; in __lrc_timestamp()
806 memset32(slot, -1, 4); in __lrc_timestamp()
877 if (igt_flush_test(gt->i915)) in live_lrc_timestamp()
878 err = -EIO; in live_lrc_timestamp()
893 obj = i915_gem_object_create_internal(vm->i915, size); in create_user_vma()
916 u32 dw, x, *cs, *hw; in store_context() local
919 batch = create_user_vma(ce->vm, SZ_64K); in store_context()
923 cs = i915_gem_object_pin_map_unlocked(batch->obj, I915_MAP_WC); in store_context()
924 if (IS_ERR(cs)) { in store_context()
926 return ERR_CAST(cs); in store_context()
929 defaults = shmem_pin_map(ce->engine->default_state); in store_context()
931 i915_gem_object_unpin_map(batch->obj); in store_context()
933 return ERR_PTR(-ENOMEM); in store_context()
936 x = 0; in store_context()
955 while (len--) { in store_context()
956 *cs++ = MI_STORE_REGISTER_MEM_GEN8; in store_context()
957 *cs++ = hw[dw]; in store_context()
958 *cs++ = lower_32_bits(scratch->node.start + x); in store_context()
959 *cs++ = upper_32_bits(scratch->node.start + x); in store_context()
962 x += 4; in store_context()
967 *cs++ = MI_BATCH_BUFFER_END; in store_context()
969 shmem_unpin_map(ce->engine->default_state, defaults); in store_context()
971 i915_gem_object_flush_map(batch->obj); in store_context()
972 i915_gem_object_unpin_map(batch->obj); in store_context()
984 err = i915_request_await_object(rq, vma->obj, flags); in move_to_active()
1000 u32 *cs; in record_registers() local
1033 cs = intel_ring_begin(rq, 14); in record_registers()
1034 if (IS_ERR(cs)) { in record_registers()
1035 err = PTR_ERR(cs); in record_registers()
1039 *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE; in record_registers()
1040 *cs++ = MI_BATCH_BUFFER_START_GEN8 | BIT(8); in record_registers()
1041 *cs++ = lower_32_bits(b_before->node.start); in record_registers()
1042 *cs++ = upper_32_bits(b_before->node.start); in record_registers()
1044 *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE; in record_registers()
1045 *cs++ = MI_SEMAPHORE_WAIT | in record_registers()
1049 *cs++ = 0; in record_registers()
1050 *cs++ = i915_ggtt_offset(ce->engine->status_page.vma) + in record_registers()
1052 *cs++ = 0; in record_registers()
1053 *cs++ = MI_NOOP; in record_registers()
1055 *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE; in record_registers()
1056 *cs++ = MI_BATCH_BUFFER_START_GEN8 | BIT(8); in record_registers()
1057 *cs++ = lower_32_bits(b_after->node.start); in record_registers()
1058 *cs++ = upper_32_bits(b_after->node.start); in record_registers()
1060 intel_ring_advance(rq, cs); in record_registers()
1080 u32 dw, *cs, *hw; in load_context() local
1083 batch = create_user_vma(ce->vm, SZ_64K); in load_context()
1087 cs = i915_gem_object_pin_map_unlocked(batch->obj, I915_MAP_WC); in load_context()
1088 if (IS_ERR(cs)) { in load_context()
1090 return ERR_CAST(cs); in load_context()
1093 defaults = shmem_pin_map(ce->engine->default_state); in load_context()
1095 i915_gem_object_unpin_map(batch->obj); in load_context()
1097 return ERR_PTR(-ENOMEM); in load_context()
1118 *cs++ = MI_LOAD_REGISTER_IMM(len); in load_context()
1119 while (len--) { in load_context()
1120 *cs++ = hw[dw]; in load_context()
1121 *cs++ = poison; in load_context()
1127 *cs++ = MI_BATCH_BUFFER_END; in load_context()
1129 shmem_unpin_map(ce->engine->default_state, defaults); in load_context()
1131 i915_gem_object_flush_map(batch->obj); in load_context()
1132 i915_gem_object_unpin_map(batch->obj); in load_context()
1141 u32 *cs; in poison_registers() local
1158 cs = intel_ring_begin(rq, 8); in poison_registers()
1159 if (IS_ERR(cs)) { in poison_registers()
1160 err = PTR_ERR(cs); in poison_registers()
1164 *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE; in poison_registers()
1165 *cs++ = MI_BATCH_BUFFER_START_GEN8 | BIT(8); in poison_registers()
1166 *cs++ = lower_32_bits(batch->node.start); in poison_registers()
1167 *cs++ = upper_32_bits(batch->node.start); in poison_registers()
1169 *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT; in poison_registers()
1170 *cs++ = i915_ggtt_offset(ce->engine->status_page.vma) + in poison_registers()
1172 *cs++ = 0; in poison_registers()
1173 *cs++ = 1; in poison_registers()
1175 intel_ring_advance(rq, cs); in poison_registers()
1177 rq->sched.attr.priority = I915_PRIORITY_BARRIER; in poison_registers()
1196 u32 x, dw, *hw, *lrc; in compare_isolation() local
1201 A[0] = i915_gem_object_pin_map_unlocked(ref[0]->obj, I915_MAP_WC); in compare_isolation()
1205 A[1] = i915_gem_object_pin_map_unlocked(ref[1]->obj, I915_MAP_WC); in compare_isolation()
1211 B[0] = i915_gem_object_pin_map_unlocked(result[0]->obj, I915_MAP_WC); in compare_isolation()
1217 B[1] = i915_gem_object_pin_map_unlocked(result[1]->obj, I915_MAP_WC); in compare_isolation()
1223 lrc = i915_gem_object_pin_map_unlocked(ce->state->obj, in compare_isolation()
1224 i915_coherent_map_type(engine->i915, in compare_isolation()
1225 ce->state->obj, in compare_isolation()
1233 defaults = shmem_pin_map(ce->engine->default_state); in compare_isolation()
1235 err = -ENOMEM; in compare_isolation()
1239 x = 0; in compare_isolation()
1258 while (len--) { in compare_isolation()
1259 if (!is_moving(A[0][x], A[1][x]) && in compare_isolation()
1260 (A[0][x] != B[0][x] || A[1][x] != B[1][x])) { in compare_isolation()
1267 …err("%s[%d]: Mismatch for register %4x, default %08x, reference %08x, result (%08x, %08x), poison … in compare_isolation()
1268 engine->name, dw, in compare_isolation()
1270 A[0][x], B[0][x], B[1][x], in compare_isolation()
1272 err = -EINVAL; in compare_isolation()
1276 x++; in compare_isolation()
1281 shmem_unpin_map(ce->engine->default_state, defaults); in compare_isolation()
1283 i915_gem_object_unpin_map(ce->state->obj); in compare_isolation()
1285 i915_gem_object_unpin_map(result[1]->obj); in compare_isolation()
1287 i915_gem_object_unpin_map(result[0]->obj); in compare_isolation()
1289 i915_gem_object_unpin_map(ref[1]->obj); in compare_isolation()
1291 i915_gem_object_unpin_map(ref[0]->obj); in compare_isolation()
1297 u32 *sema = memset32(engine->status_page.addr + 1000, 0, 1); in __lrc_isolation()
1313 ref[0] = create_user_vma(A->vm, SZ_64K); in __lrc_isolation()
1319 ref[1] = create_user_vma(A->vm, SZ_64K); in __lrc_isolation()
1336 err = -ETIME; in __lrc_isolation()
1341 result[0] = create_user_vma(A->vm, SZ_64K); in __lrc_isolation()
1347 result[1] = create_user_vma(A->vm, SZ_64K); in __lrc_isolation()
1361 WRITE_ONCE(*sema, -1); in __lrc_isolation()
1368 err = -ETIME; in __lrc_isolation()
1392 if (engine->class == COPY_ENGINE_CLASS && GRAPHICS_VER(engine->i915) == 9) in skip_isolation()
1395 if (engine->class == RENDER_CLASS && GRAPHICS_VER(engine->i915) == 11) in skip_isolation()
1416 * Our goal is try and verify that per-context state cannot be in live_lrc_isolation()
1417 * tampered with by another non-privileged client. in live_lrc_isolation()
1444 if (igt_flush_test(gt->i915)) { in live_lrc_isolation()
1445 err = -EIO; in live_lrc_isolation()
1466 err = -ETIME; in indirect_ctx_submit_req()
1477 emit_indirect_ctx_bb_canary(const struct intel_context *ce, u32 *cs) in emit_indirect_ctx_bb_canary() argument
1479 *cs++ = MI_STORE_REGISTER_MEM_GEN8 | in emit_indirect_ctx_bb_canary()
1482 *cs++ = i915_mmio_reg_offset(RING_START(0)); in emit_indirect_ctx_bb_canary()
1483 *cs++ = i915_ggtt_offset(ce->state) + in emit_indirect_ctx_bb_canary()
1486 *cs++ = 0; in emit_indirect_ctx_bb_canary()
1488 return cs; in emit_indirect_ctx_bb_canary()
1494 u32 *cs = context_indirect_bb(ce); in indirect_ctx_bb_setup() local
1496 cs[CTX_BB_CANARY_INDEX] = 0xdeadf00d; in indirect_ctx_bb_setup()
1498 setup_indirect_ctx_bb(ce, ce->engine, emit_indirect_ctx_bb_canary); in indirect_ctx_bb_setup()
1503 const u32 * const ctx_bb = (void *)(ce->lrc_reg_state) - in check_ring_start()
1506 if (ctx_bb[CTX_BB_CANARY_INDEX] == ce->lrc_reg_state[CTX_RING_START]) in check_ring_start()
1509 pr_err("ring start mismatch: canary 0x%08x vs state 0x%08x\n", in check_ring_start()
1511 ce->lrc_reg_state[CTX_RING_START]); in check_ring_start()
1525 return -EINVAL; in indirect_ctx_bb_check()
1552 if (!a->wa_bb_page) { in __live_lrc_indirect_ctx_bb()
1553 GEM_BUG_ON(b->wa_bb_page); in __live_lrc_indirect_ctx_bb()
1554 GEM_BUG_ON(GRAPHICS_VER(engine->i915) == 12); in __live_lrc_indirect_ctx_bb()
1598 if (igt_flush_test(gt->i915)) in live_lrc_indirect_ctx_bb()
1599 err = -EIO; in live_lrc_indirect_ctx_bb()
1611 const unsigned int bit = I915_RESET_ENGINE + engine->id; in garbage_reset()
1612 unsigned long *lock = &engine->gt->reset.flags; in garbage_reset()
1616 tasklet_disable(&engine->sched_engine->tasklet); in garbage_reset()
1618 if (!rq->fence.error) in garbage_reset()
1621 tasklet_enable(&engine->sched_engine->tasklet); in garbage_reset()
1638 ce->lrc_reg_state, in garbage()
1639 ce->engine->context_size - in garbage()
1675 err = -ETIME; in __lrc_garbage()
1683 if (!hang->fence.error) { in __lrc_garbage()
1686 engine->name); in __lrc_garbage()
1687 err = -EINVAL; in __lrc_garbage()
1693 engine->name); in __lrc_garbage()
1695 err = -EIO; in __lrc_garbage()
1723 if (!intel_has_reset_engine(engine->gt)) in live_lrc_garbage()
1734 if (igt_flush_test(gt->i915)) in live_lrc_garbage()
1735 err = -EIO; in live_lrc_garbage()
1754 ce->runtime.num_underflow = 0; in __live_pphwsp_runtime()
1755 ce->runtime.max_underflow = 0; in __live_pphwsp_runtime()
1767 if (--loop == 0) in __live_pphwsp_runtime()
1781 pr_err("%s: request not completed!\n", engine->name); in __live_pphwsp_runtime()
1785 igt_flush_test(engine->i915); in __live_pphwsp_runtime()
1788 engine->name, in __live_pphwsp_runtime()
1793 if (ce->runtime.num_underflow) { in __live_pphwsp_runtime()
1795 engine->name, in __live_pphwsp_runtime()
1796 ce->runtime.num_underflow, in __live_pphwsp_runtime()
1797 ce->runtime.max_underflow); in __live_pphwsp_runtime()
1799 err = -EOVERFLOW; in __live_pphwsp_runtime()
1827 if (igt_flush_test(gt->i915)) in live_pphwsp_runtime()
1828 err = -EIO; in live_pphwsp_runtime()
1850 return intel_gt_live_subtests(tests, &i915->gt); in intel_lrc_live_selftests()