| /Linux-v6.1/arch/arm64/boot/dts/mediatek/ |
| D | mt8192.dtsi | 614 <&topckgen CLK_TOP_SPI_SEL>,
639 <&topckgen CLK_TOP_SPI_SEL>,
653 <&topckgen CLK_TOP_SPI_SEL>,
667 <&topckgen CLK_TOP_SPI_SEL>,
681 <&topckgen CLK_TOP_SPI_SEL>,
695 <&topckgen CLK_TOP_SPI_SEL>,
709 <&topckgen CLK_TOP_SPI_SEL>,
723 <&topckgen CLK_TOP_SPI_SEL>,
|
| D | mt2712e.dtsi | 557 <&topckgen CLK_TOP_SPI_SEL>,
636 <&topckgen CLK_TOP_SPI_SEL>,
649 <&topckgen CLK_TOP_SPI_SEL>,
662 <&topckgen CLK_TOP_SPI_SEL>,
675 <&topckgen CLK_TOP_SPI_SEL>,
|
| D | mt8516.dtsi | 392 <&topckgen CLK_TOP_SPI_SEL>,
|
| D | mt8173.dtsi | 763 <&topckgen CLK_TOP_SPI_SEL>,
786 assigned-clocks = <&topckgen CLK_TOP_SPI_SEL>;
|
| /Linux-v6.1/include/dt-bindings/clock/ |
| D | mt7986-clk.h | 51 #define CLK_TOP_SPI_SEL 28 macro
|
| D | mt8135-clk.h | 87 #define CLK_TOP_SPI_SEL 76 macro
|
| D | mt8516-clk.h | 189 #define CLK_TOP_SPI_SEL 157 macro
|
| D | mediatek,mt6795-clk.h | 100 #define CLK_TOP_SPI_SEL 89 macro
|
| D | mt6765-clk.h | 142 #define CLK_TOP_SPI_SEL 107 macro
|
| D | mt8173-clk.h | 102 #define CLK_TOP_SPI_SEL 92 macro
|
| D | mediatek,mt8365-clk.h | 80 #define CLK_TOP_SPI_SEL 70 macro
|
| D | mt2712-clk.h | 139 #define CLK_TOP_SPI_SEL 108 macro
|
| D | mt8192-clk.h | 34 #define CLK_TOP_SPI_SEL 22 macro
|
| /Linux-v6.1/Documentation/devicetree/bindings/spi/ |
| D | mediatek,spi-mt65xx.yaml | 108 <&topckgen CLK_TOP_SPI_SEL>,
|
| /Linux-v6.1/drivers/clk/mediatek/ |
| D | clk-mt7986-topckgen.c | 181 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x000,
|
| D | clk-mt6795-topckgen.c | 467 TOP_MUX_GATE(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x60, 16, 3, 23, 0),
|
| D | clk-mt8135.c | 373 MUX_GATE(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x0150, 16, 3, 23),
|
| D | clk-mt8516.c | 422 MUX(CLK_TOP_SPI_SEL, "spi_sel", spi_parents,
|
| D | clk-mt6765.c | 403 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, CLK_CFG_2,
|
| D | clk-mt8167.c | 612 MUX(CLK_TOP_SPI_SEL, "spi_sel", spi_parents,
|
| D | clk-mt8173.c | 555 MUX_GATE(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x0060, 16, 3, 23),
|
| D | clk-mt8365.c | 439 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x060,
|
| D | clk-mt2712.c | 759 MUX_GATE(CLK_TOP_SPI_SEL, "spi_sel",
|
| D | clk-mt8192.c | 606 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel",
|
