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/Linux-v5.10/drivers/bus/
DKconfig1 # SPDX-License-Identifier: GPL-2.0
37 Driver for the Broadcom Set Top Box System-on-a-chip internal bus
42 bool "Baikal-T1 APB-bus driver"
46 Baikal-T1 AXI-APB bridge is used to access the SoC subsystem CSRs.
47 IO requests are routed to this bus by means of the DW AMBA 3 AXI
48 Interconnect. In case of any APB protocol collisions, slave device
50 reported to the APB terminator (APB Errors Handler Block). This
53 errors counter. The counter and the APB-bus operations timeout can be
57 bool "Baikal-T1 AXI-bus driver"
61 AXI3-bus is the main communication bus connecting all high-speed
[all …]
DMakefile1 # SPDX-License-Identifier: GPL-2.0
7 obj-$(CONFIG_ARM_CCI) += arm-cci.o
8 obj-$(CONFIG_ARM_INTEGRATOR_LM) += arm-integrator-lm.o
9 obj-$(CONFIG_HISILICON_LPC) += hisi_lpc.o
10 obj-$(CONFIG_BRCMSTB_GISB_ARB) += brcmstb_gisb.o
11 obj-$(CONFIG_MOXTET) += moxtet.o
13 # DPAA2 fsl-mc bus
14 obj-$(CONFIG_FSL_MC_BUS) += fsl-mc/
16 obj-$(CONFIG_BT1_APB) += bt1-apb.o
17 obj-$(CONFIG_BT1_AXI) += bt1-axi.o
[all …]
/Linux-v5.10/Documentation/devicetree/bindings/bus/
Dbaikal,bt1-apb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/bus/baikal,bt1-apb.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Baikal-T1 APB-bus
11 - Serge Semin <fancer.lancer@gmail.com>
14 Baikal-T1 CPU or DMAC MMIO requests are handled by the AMBA 3 AXI Interconnect
15 which routes them to the AXI-APB bridge. This interface is a single master
17 addressed APB slave devices. In case of any APB protocol collisions, slave
19 reported to the APB terminator (APB Errors Handler Block).
[all …]
Dnvidia,tegra210-aconnect.txt3 The Tegra ACONNECT bus is an AXI switch which is used to connnect various
5 the APE subsystem go through the ACONNECT via an APB to AXI wrapper.
8 - compatible: Must be "nvidia,tegra210-aconnect".
9 - clocks: Must contain the entries for the APE clock (TEGRA210_CLK_APE),
11 - clock-names: Must contain the names "ape" and "apb2ape" for the corresponding
13 - power-domains: Must contain a phandle that points to the audio powergate
15 - #address-cells: The number of cells used to represent physical base addresses
17 - #size-cells: The number of cells used to represent the size of an address
19 - ranges: Mapping of the aconnect address space to the CPU address space.
21 All devices accessed via the ACONNNECT are described by child-nodes.
[all …]
/Linux-v5.10/drivers/clk/sprd/
Dsc9860-clk.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
16 #include <dt-bindings/clock/sprd,sc9860-clk.h>
25 static CLK_FIXED_FACTOR(fac_4m, "fac-4m", "ext-26m",
27 static CLK_FIXED_FACTOR(fac_2m, "fac-2m", "ext-26m",
29 static CLK_FIXED_FACTOR(fac_1m, "fac-1m", "ext-26m",
31 static CLK_FIXED_FACTOR(fac_250k, "fac-250k", "ext-26m",
33 static CLK_FIXED_FACTOR(fac_rpll0_26m, "rpll0-26m", "ext-26m",
35 static CLK_FIXED_FACTOR(fac_rpll1_26m, "rpll1-26m", "ext-26m",
37 static CLK_FIXED_FACTOR(fac_rco_25m, "rco-25m", "ext-rc0-100m",
[all …]
/Linux-v5.10/arch/arc/plat-axs10x/
Daxs10x.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
12 #include <asm/asm-offsets.h>
32 * intermediate DW APB GPIO blocks (mainly for debouncing) in axs10x_enable_gpio_intc_wire()
34 * --------------------- in axs10x_enable_gpio_intc_wire()
35 * | snps,arc700-intc | in axs10x_enable_gpio_intc_wire()
36 * --------------------- in axs10x_enable_gpio_intc_wire()
38 * ------------------- ------------------- in axs10x_enable_gpio_intc_wire()
39 * | snps,dw-apb-gpio | | snps,dw-apb-gpio | in axs10x_enable_gpio_intc_wire()
40 * ------------------- ------------------- in axs10x_enable_gpio_intc_wire()
[all …]
/Linux-v5.10/Documentation/devicetree/bindings/display/imx/
Dnxp,imx8mq-dcss.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: "http://devicetree.org/schemas/display/imx/nxp,imx8mq-dcss.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - Laurentiu Palcu <laurentiu.palcu@nxp.com>
17 2.2) or MIPI-DSI. The DCSS is intended to support up to 4kp60 displays. HDR10
23 const: nxp,imx8mq-dcss
27 - description: DCSS base address and size, up to IRQ steer start
28 - description: DCSS BLKCTL base address and size
32 - description: Context loader completion and error interrupt
[all …]
/Linux-v5.10/arch/arm/boot/dts/
Dpxa168.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <dt-bindings/clock/marvell,pxa168.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
22 #address-cells = <1>;
23 #size-cells = <1>;
24 compatible = "simple-bus";
25 interrupt-parent = <&intc>;
28 axi@d4200000 { /* AXI */
29 compatible = "mrvl,axi-bus", "simple-bus";
[all …]
Dpxa910.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <dt-bindings/clock/marvell,pxa910.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
22 #address-cells = <1>;
23 #size-cells = <1>;
24 compatible = "simple-bus";
25 interrupt-parent = <&intc>;
28 L2: l2-cache {
29 compatible = "marvell,tauros2-cache";
[all …]
Dsocfpga_arria10.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/reset/altr,rst-mgr-a10.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
14 #address-cells = <1>;
15 #size-cells = <0>;
16 enable-method = "altr,socfpga-a10-smp";
19 compatible = "arm,cortex-a9";
22 next-level-cache = <&L2>;
[all …]
Dmmp2.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <dt-bindings/clock/marvell,mmp2.h>
8 #include <dt-bindings/power/marvell,mmp2.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
24 #address-cells = <1>;
25 #size-cells = <1>;
26 compatible = "simple-bus";
27 interrupt-parent = <&intc>;
30 L2: l2-cache {
[all …]
Dpicoxcell-pc3x2.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 #address-cells = <1>;
9 #size-cells = <1>;
12 #address-cells = <0>;
13 #size-cells = <0>;
16 compatible = "arm,arm1176jz-s";
18 clock-frequency = <400000000>;
19 d-cache-line-size = <32>;
20 d-cache-size = <32768>;
21 i-cache-line-size = <32>;
[all …]
/Linux-v5.10/arch/arm/mach-mmp/
Daddr-map.h1 /* SPDX-License-Identifier: GPL-2.0-only */
9 /* APB - Application Subsystem Peripheral Bus
11 * NOTE: the DMA controller registers are actually on the AXI fabric #1
12 * slave port to AHB/APB bridge, due to its close relationship to those
13 * peripherals on APB, let's count it into the ABP mapping area.
27 /* Static Memory Controller - Chip Select 0 and 1 */
/Linux-v5.10/drivers/dma/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
102 tristate "Analog Devices AXI-DMAC DMA support"
108 Enable support for the Analog Devices AXI-DMAC peripheral. This DMA
128 bool "ST-Ericsson COH901318 DMA support"
132 Enable support for ST-Ericsson COH 901 318 DMA.
151 tristate "SA-11x0 DMA support"
156 Support the DMA engine found on Intel StrongARM SA-1100 and
157 SA-1110 SoCs. This DMA engine can only be used with on-chip
180 tristate "Synopsys DesignWare AXI DMA support"
185 Enable support for Synopsys DesignWare AXI DMA controller.
[all …]
/Linux-v5.10/Documentation/devicetree/bindings/net/
Dmediatek-dwmac.txt9 - compatible: Should be "mediatek,mt2712-gmac" for MT2712 SoC
10 - reg: Address and length of the register set for the device
11 - interrupts: Should contain the MAC interrupts
12 - interrupt-names: Should contain a list of interrupt names corresponding to
15 - clocks: Must contain a phandle for each entry in clock-names.
16 - clock-names: The name of the clock listed in the clocks property. These are
17 "axi", "apb", "mac_main", "ptp_ref", "rmii_internal" for MT2712 SoC.
18 - mac-address: See ethernet.txt in the same directory
19 - phy-mode: See ethernet.txt in the same directory
20 - mediatek,pericfg: A phandle to the syscon node that control ethernet
[all …]
Dsnps,dwc-qos-ethernet.txt13 - compatible: One of:
14 - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10"
15 Represents the IP core when integrated into the Axis ARTPEC-6 SoC.
16 - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10"
18 - "snps,dwc-qos-ethernet-4.10"
20 "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10". It is supported to be
22 - reg: Address and length of the register set for the device
23 - clocks: Phandle and clock specifiers for each entry in clock-names, in the
24 same order. See ../clock/clock-bindings.txt.
25 - clock-names: May contain any/all of the following depending on the IP
[all …]
/Linux-v5.10/Documentation/devicetree/bindings/pci/
Drockchip-pcie-host.txt1 * Rockchip AXI PCIe Root Port Bridge DT description
4 - #address-cells: Address representation for root ports, set to <3>
5 - #size-cells: Size representation for root ports, set to <2>
6 - #interrupt-cells: specifies the number of cells needed to encode an
8 - compatible: Should contain "rockchip,rk3399-pcie"
9 - reg: Two register ranges as listed in the reg-names property
10 - reg-names: Must include the following names
11 - "axi-base"
12 - "apb-base"
13 - clocks: Must contain an entry for each entry in clock-names.
[all …]
Drockchip-pcie-ep.txt1 * Rockchip AXI PCIe Endpoint Controller DT description
4 - compatible: Should contain "rockchip,rk3399-pcie-ep"
5 - reg: Two register ranges as listed in the reg-names property
6 - reg-names: Must include the following names
7 - "apb-base"
8 - "mem-base"
9 - clocks: Must contain an entry for each entry in clock-names.
10 See ../clocks/clock-bindings.txt for details.
11 - clock-names: Must include the following entries:
12 - "aclk"
[all …]
/Linux-v5.10/Documentation/devicetree/bindings/clock/
Dbaikal,bt1-ccu-div.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/clock/baikal,bt1-ccu-div.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Baikal-T1 Clock Control Unit Dividers
11 - Serge Semin <fancer.lancer@gmail.com>
14 Clocks Control Unit is the core of Baikal-T1 SoC System Controller
18 IP-blocks or to groups of blocks (clock domains). The transformation is done
19 by means of an embedded into CCU PLLs and gateable/non-gateable dividers. The
22 registers. Baikal-T1 CCU is logically divided into the next components:
[all …]
Dbaikal,bt1-ccu-pll.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/clock/baikal,bt1-ccu-pll.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Baikal-T1 Clock Control Unit PLL
11 - Serge Semin <fancer.lancer@gmail.com>
14 Clocks Control Unit is the core of Baikal-T1 SoC System Controller
18 IP-blocks or to groups of blocks (clock domains). The transformation is done
19 by means of PLLs and gateable/non-gateable dividers embedded into the CCU.
23 2) PLLs clocks generators (PLLs) - described in this binding file.
[all …]
/Linux-v5.10/arch/arc/plat-hsdk/
Dplatform.c1 // SPDX-License-Identifier: GPL-2.0-only
34 * DW APB GPIO blocks (mainly for debouncing) in hsdk_enable_gpio_intc_wire()
36 * --------------------- in hsdk_enable_gpio_intc_wire()
37 * | snps,archs-intc | in hsdk_enable_gpio_intc_wire()
38 * --------------------- in hsdk_enable_gpio_intc_wire()
40 * ---------------------- in hsdk_enable_gpio_intc_wire()
41 * | snps,archs-idu-intc | in hsdk_enable_gpio_intc_wire()
42 * ---------------------- in hsdk_enable_gpio_intc_wire()
46 * ------------------- in hsdk_enable_gpio_intc_wire()
47 * | snps,dw-apb-intc | in hsdk_enable_gpio_intc_wire()
[all …]
/Linux-v5.10/arch/arc/boot/dts/
Dhsdk.dts1 // SPDX-License-Identifier: GPL-2.0-only
9 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/reset/snps,hsdk-reset.h>
18 #address-cells = <2>;
19 #size-cells = <2>;
22 … "earlycon=uart8250,mmio32,0xf0005000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1";
30 #address-cells = <1>;
31 #size-cells = <0>;
62 input_clk: input-clk {
[all …]
/Linux-v5.10/include/dt-bindings/clock/
Dmarvell,pxa168.h1 /* SPDX-License-Identifier: GPL-2.0 */
26 /* apb periphrals */
48 /* axi periphrals */
Dmarvell,pxa910.h1 /* SPDX-License-Identifier: GPL-2.0 */
26 /* apb periphrals */
46 /* axi periphrals */
Dmarvell,pxa1928.h1 /* SPDX-License-Identifier: GPL-2.0 */
9 /* apb peripherals */
42 /* axi peripherals */

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