1 // SPDX-License-Identifier: GPL-2.0-only
5  * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
12 #include <asm/asm-offsets.h>
32 	 * intermediate DW APB GPIO blocks (mainly for debouncing)  in axs10x_enable_gpio_intc_wire()
34 	 *         ---------------------  in axs10x_enable_gpio_intc_wire()
35 	 *        |  snps,arc700-intc |  in axs10x_enable_gpio_intc_wire()
36 	 *        ---------------------  in axs10x_enable_gpio_intc_wire()
38 	 * -------------------   -------------------  in axs10x_enable_gpio_intc_wire()
39 	 * | snps,dw-apb-gpio |  | snps,dw-apb-gpio |  in axs10x_enable_gpio_intc_wire()
40 	 * -------------------   -------------------  in axs10x_enable_gpio_intc_wire()
44 	 * ------------------------  in axs10x_enable_gpio_intc_wire()
45 	 * | snps,dw-apb-intc (MB)|  in axs10x_enable_gpio_intc_wire()
46 	 * ------------------------  in axs10x_enable_gpio_intc_wire()
50 	 * Current implementation of "irq-dw-apb-ictl" driver doesn't work well  in axs10x_enable_gpio_intc_wire()
52 	 * not yet instantiated. See discussion here -  in axs10x_enable_gpio_intc_wire()
56 	 * DT hardware topology - connect MB intc directly to cpu intc  in axs10x_enable_gpio_intc_wire()
88 	pr_info("AXS: %s FPGA Date: %u-%u-%u\n", str, board.d, board.m,  in axs10x_print_board_ver()
99 		mb_rev = 3;	/* HT-3 (rev3.0) */  in axs10x_early_init()
101 		mb_rev = 2;	/* HT-2 (rev2.0) */  in axs10x_early_init()
122  * Each AXI master has a 4GB memory map specified as 16 apertures of 256MB, each
125  * e.g. ARC cpu AXI Master's aperture 8 (0x8000_0000) is mapped to aperture 0
128  * Access from cpu to MB controllers such as GMAC is setup using AXI Tunnel:
131  * (0xE000_0000) of CPU Card AXI Tunnel slave (slave #3) which is mapped to
132  * MB AXI Tunnel Master, which also has a mem map setup
134  * In the reverse direction, MB AXI Masters (e.g. GMAC) mem map is setup
135  * to map to MB AXI Tunnel slave which connects to CPU Card AXI Tunnel Master
149 /* MB AXI Target slaves */
156 /* MB AXI masters */
183  * memmap for CPU Card AXI Tunnel Master (for access by MB controllers)
184  * GMAC (MB) -> MB AXI Tunnel slave -> CPU Card AXI Tunnel Master -> DDR
206  * memmap for MB AXI Masters
207  * Same mem map for all perip controllers as well as MB AXI Tunnel Master
261 	/* AXI tunnel memory map (incoming traffic from MB into CPU Card */  in axs101_early_init()
320 					"assigned-clock-rates", NULL);  in axs103_early_init()
321 		freq = be32_to_cpu(*(u32 *)(prop->data));  in axs103_early_init()
323 		/* Patching .dtb in-place with new core clock value */  in axs103_early_init()
327 					    "assigned-clock-rates", &freq, sizeof(freq));  in axs103_early_init()
332 	/* Memory maps already config in pre-bootloader */  in axs103_early_init()
344 	/* connect ICTL - Main Board with GPIO line */  in axs103_early_init()
380  * For the VDK OS-kit, to get the offset to pid and command fields