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/Linux-v5.15/drivers/mtd/nand/raw/
Dnand_ids.c29 {"TC58NVG0S3E 1G 3.3V 8-bit",
31 SZ_2K, SZ_128, SZ_128K, 0, 8, 64, NAND_ECC_INFO(1, SZ_512), },
32 {"TC58NVG2S0F 4G 3.3V 8-bit",
34 SZ_4K, SZ_512, SZ_256K, 0, 8, 224, NAND_ECC_INFO(4, SZ_512) },
35 {"TC58NVG2S0H 4G 3.3V 8-bit",
37 SZ_4K, SZ_512, SZ_256K, 0, 8, 256, NAND_ECC_INFO(8, SZ_512) },
38 {"TC58NVG3S0F 8G 3.3V 8-bit",
40 SZ_4K, SZ_1K, SZ_256K, 0, 8, 232, NAND_ECC_INFO(4, SZ_512) },
41 {"TC58NVG5D2 32G 3.3V 8-bit",
43 SZ_8K, SZ_4K, SZ_1M, 0, 8, 640, NAND_ECC_INFO(40, SZ_1K) },
[all …]
/Linux-v5.15/include/soc/mscc/
Docelot_dev.h11 #define DEV_CLOCK_CFG_MAC_TX_RST BIT(7)
12 #define DEV_CLOCK_CFG_MAC_RX_RST BIT(6)
13 #define DEV_CLOCK_CFG_PCS_TX_RST BIT(5)
14 #define DEV_CLOCK_CFG_PCS_RX_RST BIT(4)
15 #define DEV_CLOCK_CFG_PORT_RST BIT(3)
16 #define DEV_CLOCK_CFG_PHY_RST BIT(2)
20 #define DEV_PORT_MISC_FWD_ERROR_ENA BIT(4)
21 #define DEV_PORT_MISC_FWD_PAUSE_ENA BIT(3)
22 #define DEV_PORT_MISC_FWD_CTRL_ENA BIT(2)
23 #define DEV_PORT_MISC_DEV_LOOP_ENA BIT(1)
[all …]
Docelot_hsio.h85 #define HSIO_PLL5G_CFG0_ENA_ROT BIT(31)
86 #define HSIO_PLL5G_CFG0_ENA_LANE BIT(30)
87 #define HSIO_PLL5G_CFG0_ENA_CLKTREE BIT(29)
88 #define HSIO_PLL5G_CFG0_DIV4 BIT(28)
89 #define HSIO_PLL5G_CFG0_ENA_LOCK_FINE BIT(27)
99 #define HSIO_PLL5G_CFG0_ENA_VCO_CONTRH BIT(15)
100 #define HSIO_PLL5G_CFG0_ENA_CP1 BIT(14)
101 #define HSIO_PLL5G_CFG0_ENA_VCO_BUF BIT(13)
102 #define HSIO_PLL5G_CFG0_ENA_BIAS BIT(12)
109 #define HSIO_PLL5G_CFG1_ENA_DIRECT BIT(18)
[all …]
Docelot_ana.h11 #define ANA_ANAGEFIL_B_DOM_EN BIT(22)
12 #define ANA_ANAGEFIL_B_DOM_VAL BIT(21)
13 #define ANA_ANAGEFIL_AGE_LOCKED BIT(20)
14 #define ANA_ANAGEFIL_PID_EN BIT(19)
18 #define ANA_ANAGEFIL_VID_EN BIT(13)
27 #define ANA_STORMLIMIT_CFG_STORM_UNIT BIT(2)
31 #define ANA_AUTOAGE_AGE_FAST BIT(21)
35 #define ANA_AUTOAGE_AUTOAGE_LOCKED BIT(0)
37 #define ANA_MACTOPTIONS_REDUCED_TABLE BIT(1)
38 #define ANA_MACTOPTIONS_SHADOW BIT(0)
[all …]
/Linux-v5.15/drivers/net/wireless/mediatek/mt76/
Dmt76x02_regs.h15 #define MT_CMB_CTRL_XTAL_RDY BIT(22)
16 #define MT_CMB_CTRL_PLL_LD BIT(23)
21 #define MT_EFUSE_CTRL_LDO_OFF_TIME GENMASK(13, 8)
24 #define MT_EFUSE_CTRL_KICK BIT(30)
25 #define MT_EFUSE_CTRL_SEL BIT(31)
31 #define MT_COEXCFG0_COEX_EN BIT(0)
34 #define MT_WLAN_FUN_CTRL_WLAN_EN BIT(0)
35 #define MT_WLAN_FUN_CTRL_WLAN_CLK_EN BIT(1)
36 #define MT_WLAN_FUN_CTRL_WLAN_RESET_RF BIT(2)
43 #define MT_WLAN_FUN_CTRL_WLAN_RESET BIT(3) /* MT76x0 */
[all …]
/Linux-v5.15/drivers/gpu/drm/vc4/
Dvc4_regs.h26 ('3' << 8) | \
37 # define V3D_IDENT1_QUPS_MASK VC4_MASK(11, 8)
38 # define V3D_IDENT1_QUPS_SHIFT 8
47 # define V3D_L2CACTL_L2CCLR BIT(2)
48 # define V3D_L2CACTL_L2CDIS BIT(1)
49 # define V3D_L2CACTL_L2CENA BIT(0)
56 # define V3D_SLCACTL_UCC_MASK VC4_MASK(11, 8)
57 # define V3D_SLCACTL_UCC_SHIFT 8
64 # define V3D_INT_SPILLUSE BIT(3)
65 # define V3D_INT_OUTOMEM BIT(2)
[all …]
/Linux-v5.15/drivers/net/fddi/skfp/h/
Dskfbi.h40 #define B0_RAP 0x0000 /* 8 bit register address port */
42 #define B0_CTRL 0x0004 /* 8 bit control register */
43 #define B0_DAS 0x0005 /* 8 Bit control register (DAS) */
44 #define B0_LED 0x0006 /* 8 Bit LED register */
45 #define B0_TST_CTRL 0x0007 /* 8 bit test control register */
46 #define B0_ISRC 0x0008 /* 32 bit Interrupt source register */
47 #define B0_IMSK 0x000c /* 32 bit Interrupt mask register */
52 #define B0_ST1U 0x0010 /* read upper 16-bit of status reg 1 */
53 #define B0_ST1L 0x0014 /* read lower 16-bit of status reg 1 */
54 #define B0_ST2U 0x0018 /* read upper 16-bit of status reg 2 */
[all …]
/Linux-v5.15/drivers/net/ethernet/intel/ice/
Dice_hw_autogen.h19 #define PF_FW_ARQLEN_ARQVFE_M BIT(28)
20 #define PF_FW_ARQLEN_ARQOVFL_M BIT(29)
21 #define PF_FW_ARQLEN_ARQCRIT_M BIT(30)
22 #define PF_FW_ARQLEN_ARQENABLE_M BIT(31)
30 #define PF_FW_ATQLEN_ATQVFE_M BIT(28)
31 #define PF_FW_ATQLEN_ATQOVFL_M BIT(29)
32 #define PF_FW_ATQLEN_ATQCRIT_M BIT(30)
35 #define PF_FW_ATQLEN_ATQENABLE_M BIT(31)
43 #define PF_MBX_ARQLEN_ARQCRIT_M BIT(30)
44 #define PF_MBX_ARQLEN_ARQENABLE_M BIT(31)
[all …]
/Linux-v5.15/drivers/net/wireless/mediatek/mt7601u/
Dregs.h18 #define MT_CMB_CTRL_XTAL_RDY BIT(22)
19 #define MT_CMB_CTRL_PLL_LD BIT(23)
24 #define MT_EFUSE_CTRL_LDO_OFF_TIME GENMASK(13, 8)
27 #define MT_EFUSE_CTRL_KICK BIT(30)
28 #define MT_EFUSE_CTRL_SEL BIT(31)
34 #define MT_COEXCFG0_COEX_EN BIT(0)
37 #define MT_WLAN_FUN_CTRL_WLAN_EN BIT(0)
38 #define MT_WLAN_FUN_CTRL_WLAN_CLK_EN BIT(1)
39 #define MT_WLAN_FUN_CTRL_WLAN_RESET_RF BIT(2)
41 #define MT_WLAN_FUN_CTRL_WLAN_RESET BIT(3) /* MT76x0 */
[all …]
/Linux-v5.15/drivers/net/wireless/mediatek/mt76/mt7603/
Dregs.h28 #define MT_INT_RX_DONE(_n) BIT(_n)
31 #define MT_INT_TX_DONE(_n) BIT((_n) + 4)
33 #define MT_INT_RX_COHERENT BIT(20)
34 #define MT_INT_TX_COHERENT BIT(21)
35 #define MT_INT_MAC_IRQ3 BIT(27)
37 #define MT_INT_MCU_CMD BIT(30)
40 #define MT_WPDMA_GLO_CFG_TX_DMA_EN BIT(0)
41 #define MT_WPDMA_GLO_CFG_TX_DMA_BUSY BIT(1)
42 #define MT_WPDMA_GLO_CFG_RX_DMA_EN BIT(2)
43 #define MT_WPDMA_GLO_CFG_RX_DMA_BUSY BIT(3)
[all …]
Dmac.h10 #define MT_RXD0_NORMAL_IP_SUM BIT(23)
11 #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24)
12 #define MT_RXD0_NORMAL_GROUP_1 BIT(25)
13 #define MT_RXD0_NORMAL_GROUP_2 BIT(26)
14 #define MT_RXD0_NORMAL_GROUP_3 BIT(27)
15 #define MT_RXD0_NORMAL_GROUP_4 BIT(28)
29 #define MT_RXD1_NORMAL_HDR_TRANS BIT(23)
30 #define MT_RXD1_NORMAL_HDR_OFFSET BIT(22)
32 #define MT_RXD1_NORMAL_CH_FREQ GENMASK(15, 8)
34 #define MT_RXD1_NORMAL_BEACON_UC BIT(5)
[all …]
/Linux-v5.15/drivers/gpu/drm/v3d/
Dv3d_regs.h30 # define V3D_HUB_IDENT1_WITH_MSO BIT(19)
31 # define V3D_HUB_IDENT1_WITH_TSY BIT(18)
32 # define V3D_HUB_IDENT1_WITH_TFU BIT(17)
33 # define V3D_HUB_IDENT1_WITH_L3C BIT(16)
36 # define V3D_HUB_IDENT1_NCORES_MASK V3D_MASK(11, 8)
37 # define V3D_HUB_IDENT1_NCORES_SHIFT 8
44 # define V3D_HUB_IDENT2_WITH_MMU BIT(8)
49 # define V3D_HUB_IDENT3_IPREV_MASK V3D_MASK(15, 8)
50 # define V3D_HUB_IDENT3_IPREV_SHIFT 8
60 # define V3D_HUB_INT_MMU_WRV BIT(5)
[all …]
/Linux-v5.15/drivers/net/ethernet/marvell/
Dskge.h131 /* B0_CTST 16 bit Control/Status register */
138 CS_BUS_SLOT_SZ = 1<<8, /* Slot Size 0/1 = 32/64 bit slot */
142 CS_STOP_MAST = 1<<4, /* Command Bit to stop the master */
148 /* B0_LED 8 Bit LED register */
149 /* Bit 7.. 2: reserved */
153 /* B0_POWER_CTRL 8 Bit Power Control reg (YUKON only) */
164 /* B2_IRQM_MSK 32 bit IRQ Moderation Mask */
168 /* Bit 30: reserved */
195 IS_XA1_B = 1<<8, /* Q_XA1 End of Buffer */
215 /* B2_IRQM_HWE_MSK 32 bit IRQ Moderation HW Error Mask */
[all …]
/Linux-v5.15/drivers/media/platform/vsp1/
Dvsp1_regs.h18 #define VI6_CMD_UPDHDR BIT(4)
19 #define VI6_CMD_STRCMD BIT(0)
22 #define VI6_CLK_DCSWT_CSTPW_MASK (0xff << 8)
23 #define VI6_CLK_DCSWT_CSTPW_SHIFT 8
28 #define VI6_SRESET_SRTS(n) BIT(n)
31 #define VI6_STATUS_FLD_STD(n) BIT((n) + 28)
32 #define VI6_STATUS_SYS_ACT(n) BIT((n) + 8)
35 #define VI6_WFP_IRQ_ENB_DFEE BIT(1)
36 #define VI6_WFP_IRQ_ENB_FREE BIT(0)
39 #define VI6_WFP_IRQ_STA_DFE BIT(1)
[all …]
/Linux-v5.15/drivers/media/cec/platform/tegra/
Dtegra_cec.h37 #define TEGRA_CEC_HWCTRL_RX_SNOOP BIT(15)
38 #define TEGRA_CEC_HWCTRL_RX_NAK_MODE BIT(16)
39 #define TEGRA_CEC_HWCTRL_TX_NAK_MODE BIT(24)
40 #define TEGRA_CEC_HWCTRL_FAST_SIM_MODE BIT(30)
41 #define TEGRA_CEC_HWCTRL_TX_RX_MODE BIT(31)
43 #define TEGRA_CEC_INPUT_FILTER_MODE BIT(31)
47 #define TEGRA_CEC_TX_REG_EOM BIT(8)
48 #define TEGRA_CEC_TX_REG_BCAST BIT(12)
49 #define TEGRA_CEC_TX_REG_START_BIT BIT(16)
50 #define TEGRA_CEC_TX_REG_RETRY BIT(17)
[all …]
/Linux-v5.15/drivers/soc/mediatek/
Dmt8192-pm-domains.h16 .sta_mask = BIT(21),
18 .sram_pdn_bits = GENMASK(8, 8),
51 .sta_mask = BIT(2),
53 .sram_pdn_bits = GENMASK(8, 8),
58 .sta_mask = BIT(3),
60 .sram_pdn_bits = GENMASK(8, 8),
83 .sta_mask = BIT(4),
85 .sram_pdn_bits = GENMASK(8, 8),
90 .sta_mask = BIT(5),
92 .sram_pdn_bits = GENMASK(8, 8),
[all …]
/Linux-v5.15/drivers/gpio/
Dgpio-ws16c48.c36 * @io_state: bit I/O state (whether bit is set to input or output)
56 const unsigned port = offset / 8; in ws16c48_gpio_get_direction()
57 const unsigned mask = BIT(offset % 8); in ws16c48_gpio_get_direction()
68 const unsigned port = offset / 8; in ws16c48_gpio_direction_input()
69 const unsigned mask = BIT(offset % 8); in ws16c48_gpio_direction_input()
87 const unsigned port = offset / 8; in ws16c48_gpio_direction_output()
88 const unsigned mask = BIT(offset % 8); in ws16c48_gpio_direction_output()
108 const unsigned port = offset / 8; in ws16c48_gpio_get()
109 const unsigned mask = BIT(offset % 8); in ws16c48_gpio_get()
141 port_addr = ws16c48gpio->base + offset / 8; in ws16c48_gpio_get_multiple()
[all …]
/Linux-v5.15/drivers/staging/media/sunxi/cedrus/
Dcedrus_regs.h38 #define VE_MODE_PIC_WIDTH_IS_4096 BIT(22)
39 #define VE_MODE_PIC_WIDTH_MORE_2048 BIT(21)
96 #define VE_DEC_MPEG_MP12HDR_F_CODE_SHIFT(x, y) (24 - 4 * (y) - 8 * (x))
103 SHIFT_AND_MASK_BITS(s, 9, 8)
105 ((v) ? BIT(7) : 0)
107 ((v) ? BIT(6) : 0)
109 ((v) ? BIT(5) : 0)
111 ((v) ? BIT(4) : 0)
113 ((v) ? BIT(3) : 0)
115 ((v) ? BIT(2) : 0)
[all …]
/Linux-v5.15/drivers/net/dsa/
Dqca8k.h35 #define QCA8K_MASK_CTRL_DEVICE_ID_MASK GENMASK(15, 8)
36 #define QCA8K_MASK_CTRL_DEVICE_ID(x) ((x) >> 8)
40 #define QCA8K_PORT_PAD_RGMII_EN BIT(26)
43 #define QCA8K_PORT_PAD_RGMII_TX_DELAY_EN BIT(25)
44 #define QCA8K_PORT_PAD_RGMII_RX_DELAY_EN BIT(24)
46 #define QCA8K_PORT_PAD_SGMII_EN BIT(7)
48 #define QCA8K_PWS_SERDES_AEN_DIS BIT(7)
50 #define QCA8K_MODULE_EN_MIB BIT(0)
52 #define QCA8K_MIB_FLUSH BIT(24)
53 #define QCA8K_MIB_CPU_KEEP BIT(20)
[all …]
/Linux-v5.15/drivers/mmc/host/
Dtoshsd.h24 #define SD_PCICFG_EXTGATECLK3 0xf9 /* Bit 1: double buffer/single buffer */
28 #define SD_PCICFG_CLKMODE_DIV_DISABLE BIT(0)
74 #define SD_TRANSCTL_SET BIT(8)
76 #define SD_CARDCLK_DIV_DISABLE BIT(15)
77 #define SD_CARDCLK_ENABLE_CLOCK BIT(8)
78 #define SD_CARDCLK_CLK_DIV_512 BIT(7)
79 #define SD_CARDCLK_CLK_DIV_256 BIT(6)
80 #define SD_CARDCLK_CLK_DIV_128 BIT(5)
81 #define SD_CARDCLK_CLK_DIV_64 BIT(4)
82 #define SD_CARDCLK_CLK_DIV_32 BIT(3)
[all …]
/Linux-v5.15/Documentation/gpu/
Dafbc.rst42 * Component 0: R(8)
43 * Component 1: G(8)
44 * Component 2: B(8)
45 * Component 3: A(8)
49 * Component 0: R(8)
50 * Component 1: G(8)
51 * Component 2: B(8)
55 * Component 0: Y(8)
56 * Component 1: Cb(8, 2x1 subsampled)
57 * Component 2: Cr(8, 2x1 subsampled)
[all …]
/Linux-v5.15/drivers/net/ethernet/stmicro/stmmac/
Ddwxgmac2.h28 #define XGMAC_CONFIG_JD BIT(16)
29 #define XGMAC_CONFIG_TE BIT(0)
32 #define XGMAC_CONFIG_ARPEN BIT(31)
38 #define XGMAC_CONFIG_S2KP BIT(11)
39 #define XGMAC_CONFIG_LM BIT(10)
40 #define XGMAC_CONFIG_IPC BIT(9)
41 #define XGMAC_CONFIG_JE BIT(8)
42 #define XGMAC_CONFIG_WD BIT(7)
43 #define XGMAC_CONFIG_GPSLCE BIT(6)
44 #define XGMAC_CONFIG_CST BIT(2)
[all …]
/Linux-v5.15/drivers/power/supply/
Dbd99954-charger.h482 [F_PREV_CHGSTM_STATE] = REG_FIELD(CHGSTM_STATUS, 8, 14),
486 [F_BATTEMP] = REG_FIELD(CHGOP_STATUS, 8, 10),
490 [F_THERMWDT_VAL] = REG_FIELD(WDT_STATUS, 8, 15),
513 [F_SDP_CHG_TRIG] = REG_FIELD(CHGOP_SET1, 8, 8),
520 [F_BATT_LEARN] = REG_FIELD(CHGOP_SET2, 8, 8),
530 [F_WDT_FST] = REG_FIELD(CHGWDT_SET, 8, 15),
532 [F_WDT_IBAT_SHORT] = REG_FIELD(BATTWDT_SET, 8, 15),
551 [F_PROCHOT_IDCHG_DG_SET] = REG_FIELD(PROCHOT_CTRL_SET, 8, 9),
558 [F_PMON_INSEL] = REG_FIELD(PMON_IOUT_CTRL_SET, 8, 8),
567 [F_VCC_ADCRTRY] = REG_FIELD(VCC_UCD_SET, 8, 8),
[all …]
/Linux-v5.15/drivers/net/dsa/b53/
Db53_regs.h63 /* Port Control Register (8 bit) */
65 #define PORT_CTRL_RX_DISABLE BIT(0)
66 #define PORT_CTRL_TX_DISABLE BIT(1)
67 #define PORT_CTRL_RX_BCST_EN BIT(2) /* Broadcast RX (P8 only) */
68 #define PORT_CTRL_RX_MCST_EN BIT(3) /* Multicast RX (P8 only) */
69 #define PORT_CTRL_RX_UCST_EN BIT(4) /* Unicast RX (P8 only) */
79 /* SMP Control Register (8 bit) */
82 /* Switch Mode Control Register (8 bit) */
84 #define SM_SW_FWD_MODE BIT(0) /* 1 = Managed Mode */
85 #define SM_SW_FWD_EN BIT(1) /* Forwarding Enable */
[all …]
/Linux-v5.15/drivers/net/wireless/mediatek/mt76/mt7615/
Dmac.h15 #define MT_RXD0_NORMAL_IP_SUM BIT(23)
16 #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24)
17 #define MT_RXD0_NORMAL_GROUP_1 BIT(25)
18 #define MT_RXD0_NORMAL_GROUP_2 BIT(26)
19 #define MT_RXD0_NORMAL_GROUP_3 BIT(27)
20 #define MT_RXD0_NORMAL_GROUP_4 BIT(28)
37 #define MT_RXD1_MID_AMSDU_FRAME BIT(1)
38 #define MT_RXD1_LAST_AMSDU_FRAME BIT(0)
39 #define MT_RXD1_NORMAL_HDR_TRANS BIT(23)
40 #define MT_RXD1_NORMAL_HDR_OFFSET BIT(22)
[all …]

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