Lines Matching +full:8 +full:bit
63 /* Port Control Register (8 bit) */
65 #define PORT_CTRL_RX_DISABLE BIT(0)
66 #define PORT_CTRL_TX_DISABLE BIT(1)
67 #define PORT_CTRL_RX_BCST_EN BIT(2) /* Broadcast RX (P8 only) */
68 #define PORT_CTRL_RX_MCST_EN BIT(3) /* Multicast RX (P8 only) */
69 #define PORT_CTRL_RX_UCST_EN BIT(4) /* Unicast RX (P8 only) */
79 /* SMP Control Register (8 bit) */
82 /* Switch Mode Control Register (8 bit) */
84 #define SM_SW_FWD_MODE BIT(0) /* 1 = Managed Mode */
85 #define SM_SW_FWD_EN BIT(1) /* Forwarding Enable */
87 /* IMP Port state override register (8 bit) */
89 #define PORT_OVERRIDE_LINK BIT(0)
90 #define PORT_OVERRIDE_FULL_DUPLEX BIT(1) /* 0 = Half Duplex */
95 #define PORT_OVERRIDE_RV_MII_25 BIT(4) /* BCM5325 only */
96 #define PORT_OVERRIDE_RX_FLOW BIT(4)
97 #define PORT_OVERRIDE_TX_FLOW BIT(5)
98 #define PORT_OVERRIDE_SPEED_2000M BIT(6) /* BCM5301X only, requires setting 1000M */
99 #define PORT_OVERRIDE_EN BIT(7) /* Use the register contents */
104 /* IP Multicast control (8 bit) */
106 #define B53_IPMC_FWD_EN BIT(1)
107 #define B53_UC_FWD_EN BIT(6)
108 #define B53_MC_FWD_EN BIT(7)
110 /* Switch control (8 bit) */
112 #define B53_MII_DUMB_FWDG_EN BIT(6)
114 /* (16 bit) */
121 * Override Ports 0-7 State on devices with xMII interfaces (8 bit)
123 * For port 8 still use B53_PORT_OVERRIDE_CTRL
128 #define GMII_PO_LINK BIT(0)
129 #define GMII_PO_FULL_DUPLEX BIT(1) /* 0 = Half Duplex */
134 #define GMII_PO_RX_FLOW BIT(4)
135 #define GMII_PO_TX_FLOW BIT(5)
136 #define GMII_PO_EN BIT(6) /* Use the register contents */
137 #define GMII_PO_SPEED_2000M BIT(7) /* BCM5301X only, requires setting 1000M */
140 #define RGMII_CTRL_ENABLE_GMII BIT(7)
141 #define RGMII_CTRL_TIMING_SEL BIT(2)
142 #define RGMII_CTRL_DLL_RXC BIT(1)
143 #define RGMII_CTRL_DLL_TXC BIT(0)
147 /* Software reset register (8 bit) */
149 #define SW_RST BIT(7)
150 #define EN_CH_RST BIT(6)
151 #define EN_SW_RST BIT(4)
153 /* Fast Aging Control register (8 bit) */
155 #define FAST_AGE_STATIC BIT(0)
156 #define FAST_AGE_DYNAMIC BIT(1)
157 #define FAST_AGE_PORT BIT(2)
158 #define FAST_AGE_VLAN BIT(3)
159 #define FAST_AGE_STP BIT(4)
160 #define FAST_AGE_MC BIT(5)
161 #define FAST_AGE_DONE BIT(7)
163 /* Fast Aging Port Control register (8 bit) */
166 /* Fast Aging VID Control register (16 bit) */
173 /* Link Status Summary Register (16bit) */
176 /* Link Status Change Register (16 bit) */
179 /* Port Speed Summary Register (16 bit for FE, 32 bit for GE) */
187 /* Duplex Status Summary (16 bit) */
195 /* Strap Value (48 bit) */
197 #define SV_GMII_CTRL_115 BIT(27)
203 /* Global Management Config Register (8 bit) */
213 /* Broadcom Header control register (8 bit) */
215 #define BRCM_HDR_P8_EN BIT(0) /* Enable tagging on port 8 */
216 #define BRCM_HDR_P5_EN BIT(1) /* Enable tagging on port 5 */
217 #define BRCM_HDR_P7_EN BIT(2) /* Enable tagging on port 7 */
219 /* Mirror capture control register (16 bit) */
222 #define BLK_NOT_MIR BIT(14)
223 #define MIRROR_EN BIT(15)
225 /* Ingress mirror control register (16 bit) */
228 #define DIV_EN BIT(13)
235 /* Ingress mirror divider register (16 bit) */
239 /* Ingress mirror MAC address register (48 bit) */
242 /* Egress mirror control register (16 bit) */
245 /* Egress mirror divider register (16 bit) */
248 /* Egress mirror MAC address register (48 bit) */
251 /* Device ID register (8 or 32 bit) */
254 /* Revision ID register (8 bit) */
257 /* Broadcom header RX control (16 bit) */
260 /* Broadcom header TX control (16 bit) */
267 /* VLAN Table Access Register (8 bit) */
274 #define VTA_START_CMD BIT(7)
276 /* VLAN Table Index Register (16 bit) */
281 /* VLAN Table Entry Register (32 bit) */
293 /* ARL Table Read/Write Register (8 bit) */
295 #define ARLTBL_RW BIT(0)
296 #define ARLTBL_IVL_SVL_SELECT BIT(6)
297 #define ARLTBL_START_DONE BIT(7)
299 /* MAC Address Index Register (48 bit) */
302 /* VLAN ID Index Register (16 bit) */
305 /* ARL Table MAC/VID Entry N Registers (64 bit)
316 #define ARLTBL_AGE_25 BIT(61)
317 #define ARLTBL_STATIC_25 BIT(62)
318 #define ARLTBL_VALID_25 BIT(63)
320 /* ARL Table Data Entry N Registers (32 bit) */
324 #define ARLTBL_AGE BIT(14)
325 #define ARLTBL_STATIC BIT(15)
326 #define ARLTBL_VALID BIT(16)
331 /* ARL Search Control Register (8 bit) */
334 #define ARL_SRCH_VLID BIT(0)
335 #define ARL_SRCH_STDN BIT(7)
337 /* ARL Search Address Register (16 bit) */
343 /* ARL Search MAC/VID Result (64 bit) */
351 /* ARL Search Data Result (32 bit) */
361 /* Port VLAN mask (16 bit) IMP port is always 8, also on 5325 & co */
364 /* Join all VLANs register (16 bit) */
371 /* Global QoS Control (8 bit) */
374 /* Enable 802.1Q for individual Ports (16 bit) */
381 /* VLAN Control 0 (8 bit) */
392 #define VC0_RESERVED_1 BIT(1)
393 #define VC0_DROP_VID_MISS BIT(4)
394 #define VC0_VID_HASH_VID BIT(5)
395 #define VC0_VID_CHK_EN BIT(6) /* Use VID,DA or VID,SA */
396 #define VC0_VLAN_EN BIT(7) /* 802.1Q VLAN Enabled */
398 /* VLAN Control 1 (8 bit) */
400 #define VC1_RX_MCST_TAG_EN BIT(1)
401 #define VC1_RX_MCST_FWD_EN BIT(2)
402 #define VC1_RX_MCST_UNTAG_EN BIT(3)
404 /* VLAN Control 2 (8 bit) */
407 /* VLAN Control 3 (8 bit when BCM5325, 16 bit else) */
410 #define VC3_MAXSIZE_1532 BIT(6) /* 5325 only */
411 #define VC3_HIGH_8BIT_EN BIT(7) /* 5325 only */
413 /* VLAN Control 4 (8 bit) */
424 /* VLAN Control 5 (8 bit) */
428 #define VC5_VID_FFF_EN BIT(2)
429 #define VC5_DROP_VTABLE_MISS BIT(3)
431 /* VLAN Control 6 (8 bit) */
435 /* VLAN Table Access Register (16 bit) */
441 #define VTA_VID_HIGH_S_65 8
444 #define VTA_RW_STATE BIT(12)
446 #define VTA_RW_STATE_WR BIT(12)
447 #define VTA_RW_OP_EN BIT(13)
449 /* VLAN Read/Write Registers for (16/32 bit) */
460 #define VA_VALID_25 BIT(20)
461 #define VA_VALID_25_R4 BIT(24)
462 #define VA_VALID_65 BIT(14)
464 /* VLAN Port Default Tag (16 bit) */
471 /* Jumbo Enable Port Mask (bit i == port i enabled) (32 bit) */
474 #define JPM_10_100_JUMBO_EN BIT(24) /* GigE always enabled */
476 /* Good Frame Max Size without 802.1Q TAG (16 bit) */
486 /* EEE Enable control register (16 bit) */
489 /* EEE LPI assert status register (16 bit) */
492 /* EEE LPI indicate status register (16 bit) */
495 /* EEE Receiving idle symbols status register (16 bit) */
498 /* EEE Pipeline timer register (32 bit) */
501 /* EEE Sleep timer Gig register (32 bit) */
504 /* EEE Sleep timer FE register (32 bit) */
507 /* EEE Minimum LP timer Gig register (32 bit) */
510 /* EEE Minimum LP timer FE register (32 bit) */
513 /* EEE Wake timer Gig register (16 bit) */
516 /* EEE Wake timer FE register (16 bit) */
524 /* CFP Control Register with ports map (8 bit) */