| /Linux-v6.1/tools/testing/selftests/vm/ |
| D | mremap_dontunmap.c | 43 // Try a simple operation for to "test" for kernel support this prevents
100 unsigned long num_pages = 5; in mremap_dontunmap_simple()
107 memset(source_mapping, 'a', num_pages * page_size); in mremap_dontunmap_simple()
116 // the dest_mapping contains a's. in mremap_dontunmap_simple()
118 (dest_mapping, num_pages * page_size, 'a') != 0, in mremap_dontunmap_simple()
130 // This test validates that MREMAP_DONTUNMAP on a shared mapping works as expected.
133 unsigned long num_pages = 5; in mremap_dontunmap_simple_shmem()
148 memset(source_mapping, 'a', num_pages * page_size); in mremap_dontunmap_simple_shmem()
164 // the dest_mapping contains a's. in mremap_dontunmap_simple_shmem()
166 (dest_mapping, num_pages * page_size, 'a') != 0, in mremap_dontunmap_simple_shmem()
[all …]
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| /Linux-v6.1/arch/alpha/lib/ |
| D | ev6-memset.S | 23 * A future enhancement might be to put in a byte store loop for really
25 * a win in the kernel would depend upon the contextual usage.
41 .align 5
48 * undertake a major re-write to interleave the constant materialization
64 inswl $17,4,$5 # U : 0000chch00000000
69 or $2,$5,$2 # E : chchchch00000000
70 bic $1,7,$1 # E : fit within a single quadword?
79 * Target address is misaligned, and won't fit within a quadword
82 bis $16,$16,$5 # E : Save the address
92 stq_u $1,0($5) # L : Store result
[all …]
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| /Linux-v6.1/tools/perf/pmu-events/arch/x86/sapphirerapids/ |
| D | frontend.json | 9 …to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Le…
32 …a Uop-cache that holds translations of previously fetched instructions that were decoded by the le…
40 "Counter": "0,1,2,3,4,5,6,7",
46 "PEBScounters": "0,1,2,3,4,5,6,7",
53 "BriefDescription": "Retired Instructions who experienced a critical DSB miss.",
55 "Counter": "0,1,2,3,4,5,6,7",
61 "PEBScounters": "0,1,2,3,4,5,6,7",
62 …erienced a critical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical m…
70 "Counter": "0,1,2,3,4,5,6,7",
76 "PEBScounters": "0,1,2,3,4,5,6,7",
[all …]
|
| D | pipeline.json | 19 "Counter": "0,1,2,3,4,5,6,7",
23 "PEBScounters": "0,1,2,3,4,5,6,7",
31 "Counter": "0,1,2,3,4,5,6,7",
35 "PEBScounters": "0,1,2,3,4,5,6,7",
44 "Counter": "0,1,2,3,4,5,6,7",
48 "PEBScounters": "0,1,2,3,4,5,6,7",
56 "Counter": "0,1,2,3,4,5,6,7",
59 "PEBScounters": "0,1,2,3,4,5,6,7",
67 "Counter": "0,1,2,3,4,5,6,7",
71 "PEBScounters": "0,1,2,3,4,5,6,7",
[all …]
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| /Linux-v6.1/tools/perf/pmu-events/arch/x86/icelakex/ |
| D | frontend.json | 3 … number when the front end is resteered, mainly when the BPU cannot provide a correct prediction a…
9 …the front-end is resteered when it finds a branch instruction in a fetch line. This occurs for the…
23 …"PublicDescription": "Counts the number of Decode Stream Buffer (DSB a.k.a. Uop Cache)-to-MITE spe…
35 …a Uop-cache that holds translations of previously fetched instructions that were decoded by the le…
43 "Counter": "0,1,2,3,4,5,6,7",
49 "PEBScounters": "0,1,2,3,4,5,6,7",
56 "BriefDescription": "Retired Instructions who experienced a critical DSB miss.",
58 "Counter": "0,1,2,3,4,5,6,7",
64 "PEBScounters": "0,1,2,3,4,5,6,7",
65 …erienced a critical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical m…
[all …]
|
| D | pipeline.json | 5 "Counter": "0,1,2,3,4,5,6,7",
9 "PEBScounters": "0,1,2,3,4,5,6,7",
16 … "BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.",
18 "Counter": "0,1,2,3,4,5,6,7",
21 "PEBScounters": "0,1,2,3,4,5,6,7",
22 …"PublicDescription": "Counts the number of occurrences where a microcode assist is invoked by hard…
30 "Counter": "0,1,2,3,4,5,6,7",
34 "PEBScounters": "0,1,2,3,4,5,6,7",
41 "Counter": "0,1,2,3,4,5,6,7",
45 "PEBScounters": "0,1,2,3,4,5,6,7",
[all …]
|
| /Linux-v6.1/tools/perf/pmu-events/arch/x86/icelake/ |
| D | frontend.json | 3 … number when the front end is resteered, mainly when the BPU cannot provide a correct prediction a…
9 …the front-end is resteered when it finds a branch instruction in a fetch line. This occurs for the…
23 …"PublicDescription": "Counts the number of Decode Stream Buffer (DSB a.k.a. Uop Cache)-to-MITE spe…
35 …a Uop-cache that holds translations of previously fetched instructions that were decoded by the le…
43 "Counter": "0,1,2,3,4,5,6,7",
49 "PEBScounters": "0,1,2,3,4,5,6,7",
56 "BriefDescription": "Retired Instructions who experienced a critical DSB miss.",
58 "Counter": "0,1,2,3,4,5,6,7",
64 "PEBScounters": "0,1,2,3,4,5,6,7",
65 …erienced a critical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical m…
[all …]
|
| D | pipeline.json | 5 "Counter": "0,1,2,3,4,5,6,7",
9 "PEBScounters": "0,1,2,3,4,5,6,7",
16 … "BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.",
18 "Counter": "0,1,2,3,4,5,6,7",
21 "PEBScounters": "0,1,2,3,4,5,6,7",
22 …"PublicDescription": "Counts the number of occurrences where a microcode assist is invoked by hard…
30 "Counter": "0,1,2,3,4,5,6,7",
34 "PEBScounters": "0,1,2,3,4,5,6,7",
41 "Counter": "0,1,2,3,4,5,6,7",
45 "PEBScounters": "0,1,2,3,4,5,6,7",
[all …]
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| D | memory.json | 29 "Counter": "0,1,2,3,4,5,6,7",
32 "PEBScounters": "0,1,2,3,4,5,6,7",
40 "Counter": "0,1,2,3,4,5,6,7",
43 "PEBScounters": "0,1,2,3,4,5,6,7",
51 "Counter": "0,1,2,3,4,5,6,7",
54 "PEBScounters": "0,1,2,3,4,5,6,7",
62 "Counter": "0,1,2,3,4,5,6,7",
65 "PEBScounters": "0,1,2,3,4,5,6,7",
73 "Counter": "0,1,2,3,4,5,6,7",
76 "PEBScounters": "0,1,2,3,4,5,6,7",
[all …]
|
| /Linux-v6.1/tools/perf/pmu-events/arch/x86/tigerlake/ |
| D | frontend.json | 3 … number when the front end is resteered, mainly when the BPU cannot provide a correct prediction a…
9 …the front-end is resteered when it finds a branch instruction in a fetch line. This occurs for the…
22 …"PublicDescription": "Counts the number of Decode Stream Buffer (DSB a.k.a. Uop Cache)-to-MITE spe…
33 …a Uop-cache that holds translations of previously fetched instructions that were decoded by the le…
40 "Counter": "0,1,2,3,4,5,6,7",
46 "PEBScounters": "0,1,2,3,4,5,6,7",
53 "BriefDescription": "Retired Instructions who experienced a critical DSB miss.",
55 "Counter": "0,1,2,3,4,5,6,7",
61 "PEBScounters": "0,1,2,3,4,5,6,7",
62 …erienced a critical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical m…
[all …]
|
| D | pipeline.json | 5 "Counter": "0,1,2,3,4,5,6,7",
9 "PEBScounters": "0,1,2,3,4,5,6,7",
15 … "BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.",
17 "Counter": "0,1,2,3,4,5,6,7",
20 "PEBScounters": "0,1,2,3,4,5,6,7",
21 …"PublicDescription": "Counts the number of occurrences where a microcode assist is invoked by hard…
28 "Counter": "0,1,2,3,4,5,6,7",
32 "PEBScounters": "0,1,2,3,4,5,6,7",
39 "Counter": "0,1,2,3,4,5,6,7",
43 "PEBScounters": "0,1,2,3,4,5,6,7",
[all …]
|
| D | memory.json | 16 "Counter": "0,1,2,3,4,5,6,7",
19 "PEBScounters": "0,1,2,3,4,5,6,7",
20 …ected dye to memory ordering. Memory Ordering Machine Clears may apply when a memory read may not …
27 "Counter": "0,1,2,3,4,5,6,7",
34 "PEBScounters": "0,1,2,3,4,5,6,7",
43 "Counter": "0,1,2,3,4,5,6,7",
50 "PEBScounters": "0,1,2,3,4,5,6,7",
59 "Counter": "0,1,2,3,4,5,6,7",
66 "PEBScounters": "0,1,2,3,4,5,6,7",
75 "Counter": "0,1,2,3,4,5,6,7",
[all …]
|
| /Linux-v6.1/tools/perf/pmu-events/arch/x86/skylake/ |
| D | virtual-memory.json | 5 "CounterHTOff": "0,1,2,3,4,5,6,7",
8 …"PublicDescription": "Counts demand data loads that caused a page walk of any page size (4K/2M/4M/…
15 "CounterHTOff": "0,1,2,3,4,5,6,7",
23 …"BriefDescription": "Cycles when at least one PMH is busy with a page walk for a load. EPT page wa…
25 "CounterHTOff": "0,1,2,3,4,5,6,7",
29 …n": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a load.",
34 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size…
36 "CounterHTOff": "0,1,2,3,4,5,6,7",
39 …s it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
44 "BriefDescription": "Page walk completed due to a demand data load to a 1G page",
[all …]
|
| /Linux-v6.1/tools/perf/pmu-events/arch/x86/cascadelakex/ |
| D | virtual-memory.json | 5 "CounterHTOff": "0,1,2,3,4,5,6,7",
8 …"PublicDescription": "Counts demand data loads that caused a page walk of any page size (4K/2M/4M/…
15 "CounterHTOff": "0,1,2,3,4,5,6,7",
23 …"BriefDescription": "Cycles when at least one PMH is busy with a page walk for a load. EPT page wa…
25 "CounterHTOff": "0,1,2,3,4,5,6,7",
29 …n": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a load.",
34 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size…
36 "CounterHTOff": "0,1,2,3,4,5,6,7",
39 …s it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
44 "BriefDescription": "Page walk completed due to a demand data load to a 1G page",
[all …]
|
| /Linux-v6.1/tools/perf/pmu-events/arch/x86/skylakex/ |
| D | virtual-memory.json | 5 "CounterHTOff": "0,1,2,3,4,5,6,7",
8 …"PublicDescription": "Counts demand data loads that caused a page walk of any page size (4K/2M/4M/…
15 "CounterHTOff": "0,1,2,3,4,5,6,7",
23 …"BriefDescription": "Cycles when at least one PMH is busy with a page walk for a load. EPT page wa…
25 "CounterHTOff": "0,1,2,3,4,5,6,7",
29 …n": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a load.",
34 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size…
36 "CounterHTOff": "0,1,2,3,4,5,6,7",
39 …s it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
44 "BriefDescription": "Page walk completed due to a demand data load to a 1G page",
[all …]
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| D | pipeline.json | 5 "CounterHTOff": "0,1,2,3,4,5,6,7",
15 "CounterHTOff": "0,1,2,3,4,5,6,7",
30 …"PublicDescription": "This is a precise version of BR_INST_RETIRED.ALL_BRANCHES that counts all (m…
37 "CounterHTOff": "0,1,2,3,4,5,6,7",
49 "CounterHTOff": "0,1,2,3,4,5,6,7",
60 "CounterHTOff": "0,1,2,3,4,5,6,7",
72 "CounterHTOff": "0,1,2,3,4,5,6,7",
84 "CounterHTOff": "0,1,2,3,4,5,6,7",
96 "CounterHTOff": "0,1,2,3,4,5,6,7",
108 "CounterHTOff": "0,1,2,3,4,5,6,7",
[all …]
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| /Linux-v6.1/Documentation/input/devices/ |
| D | elantech.rst | 22 5. Hardware version 2
57 combine a status packet with multiple head or motion packets. Hardware version
58 4 allows tracking up to 5 fingers.
60 Some Hardware version 3 and version 4 also have a trackpoint which uses a
67 Note that a mouse button is also associated with either the touchpad or the
68 trackpoint when a trackpoint is available. Disabling the Touchpad in xorg
101 Currently a value of "1" will turn on some basic debugging and a value of
107 generate quite a lot of data!
118 calculating a parity bit for the last 3 bytes of each packet. The driver
175 By echoing a hexadecimal value to a register it contents can be altered.
[all …]
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| /Linux-v6.1/tools/perf/pmu-events/arch/x86/alderlake/ |
| D | frontend.json | 5 "Counter": "0,1,2,3,4,5",
8 "PEBScounters": "0,1,2,3,4,5",
15 …": "Counts the number of requests to the instruction cache for one or more bytes of a cache line.",
17 "Counter": "0,1,2,3,4,5",
20 "PEBScounters": "0,1,2,3,4,5",
29 "Counter": "0,1,2,3,4,5",
32 "PEBScounters": "0,1,2,3,4,5",
77 "Counter": "0,1,2,3,4,5,6,7",
83 "PEBScounters": "0,1,2,3,4,5,6,7",
90 "BriefDescription": "Retired Instructions who experienced a critical DSB miss.",
[all …]
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| /Linux-v6.1/tools/perf/pmu-events/arch/x86/broadwell/ |
| D | virtual-memory.json | 5 "CounterHTOff": "0,1,2,3,4,5,6,7",
16 "CounterHTOff": "0,1,2,3,4,5,6,7",
25 "CounterHTOff": "0,1,2,3,4,5,6,7",
34 "CounterHTOff": "0,1,2,3,4,5,6,7",
41 …: "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that compl…
43 "CounterHTOff": "0,1,2,3,4,5,6,7",
51 "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (1G)",
53 "CounterHTOff": "0,1,2,3,4,5,6,7",
57 …misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end …
62 …: "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that compl…
[all …]
|
| /Linux-v6.1/tools/perf/pmu-events/arch/x86/broadwellde/ |
| D | virtual-memory.json | 5 "CounterHTOff": "0,1,2,3,4,5,6,7",
16 "CounterHTOff": "0,1,2,3,4,5,6,7",
25 "CounterHTOff": "0,1,2,3,4,5,6,7",
34 "CounterHTOff": "0,1,2,3,4,5,6,7",
41 …: "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that compl…
43 "CounterHTOff": "0,1,2,3,4,5,6,7",
51 "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (1G)",
53 "CounterHTOff": "0,1,2,3,4,5,6,7",
57 …misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end …
62 …: "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that compl…
[all …]
|
| /Linux-v6.1/tools/perf/pmu-events/arch/x86/broadwellx/ |
| D | virtual-memory.json | 5 "CounterHTOff": "0,1,2,3,4,5,6,7",
16 "CounterHTOff": "0,1,2,3,4,5,6,7",
25 "CounterHTOff": "0,1,2,3,4,5,6,7",
34 "CounterHTOff": "0,1,2,3,4,5,6,7",
41 …: "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that compl…
43 "CounterHTOff": "0,1,2,3,4,5,6,7",
51 "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (1G)",
53 "CounterHTOff": "0,1,2,3,4,5,6,7",
57 …misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end …
62 …: "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that compl…
[all …]
|
| /Linux-v6.1/Documentation/admin-guide/perf/ |
| D | hisi-pmu.rst | 27 Each L3C, HHA and DDRC is registered as a separate PMU with perf. The PMU
38 The driver also provides a "cpumask" sysfs attribute, which shows the CPU core
53 $# perf stat -a -e hisi_sccl3_l3c0/rd_hit_cpipe/ sleep 5
54 $# perf stat -a -e hisi_sccl3_l3c0/config=0x02/ sleep 5
59 (a) L3C PMU supports filtering by core/thread within the cluster which can be
60 specified as a bitmap::
62 $# perf stat -a -e hisi_sccl3_l3c0/config=0x02,tt_core=0x3/ sleep 5
72 $# perf stat -a -e hisi_sccl3_l3c0/config=0x02,tt_req=0x4/ sleep 5
76 (c) Datasrc allows the user to check where the data comes from. It is 5 bits.
78 5'b00001: comes from L3C in this die;
[all …]
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| /Linux-v6.1/drivers/net/ipa/ |
| D | ipa_reg.h | 20 * Device Tree. Each register has a specified offset within that space,
22 * has a unique identifer, taken from the ipa_reg_id enumerated type.
25 * Certain "parameterized" register types are duplicated for a number of
29 * ID multiplied and a "stride" value for the register. Similarly, some
31 * this case, the stride is multiplied by a member of the gsi_ee_id
36 * (for parameterized registers) a non-zero stride value. Not all versions
37 * of IPA define all registers. The offset for a register is returned by
42 * such a register has a unique identifier (from an enumerated type).
43 * The position and width of the fields in a register are defined by
46 * argument. To encode a value to be represented in a register field,
[all …]
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| /Linux-v6.1/arch/powerpc/crypto/ |
| D | aes-tab-4k.S | 10 * crypto/aes_generic.c and are designed to be simply accessed by a combination
11 * of rlwimi/lwz instructions with a minimum of table registers (usually only
19 * This is a quite good tradeoff for low power devices (e.g. routers) without
25 #define R(a, b, c, d) \ argument
26 0x##a##b##c##d, 0x##d##a##b##c, 0x##c##d##a##b, 0x##b##c##d##a
40 .long R(4d, ab, ab, e6), R(ec, 76, 76, 9a)
46 .long R(5f, a2, a2, fd), R(45, af, af, ea)
48 .long R(e4, 72, 72, 96), R(9b, c0, c0, 5b)
50 .long R(3d, 93, 93, ae), R(4c, 26, 26, 6a)
51 .long R(6c, 36, 36, 5a), R(7e, 3f, 3f, 41)
[all …]
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| /Linux-v6.1/arch/s390/lib/ |
| D | uaccess.c | 42 .oac2.a = 1, in raw_copy_from_user_key()
58 " jnh 5f\n" in raw_copy_from_user_key()
61 " j 5f\n" in raw_copy_from_user_key()
63 "5:\n" in raw_copy_from_user_key()
64 EX_TABLE(0b,2b) EX_TABLE(3b,5b) EX_TABLE(6b,2b) EX_TABLE(7b,5b) in raw_copy_from_user_key()
65 : "+a" (size), "+a" (from), "+a" (to), "+a" (tmp1), "=a" (tmp2) in raw_copy_from_user_key()
102 .oac1.a = 1, in raw_copy_to_user_key()
118 " jnh 5f\n" in raw_copy_to_user_key()
121 " j 5f\n" in raw_copy_to_user_key()
123 "5:\n" in raw_copy_to_user_key()
[all …]
|
