Lines Matching +full:5 +full:a
20 * Device Tree. Each register has a specified offset within that space,
22 * has a unique identifer, taken from the ipa_reg_id enumerated type.
25 * Certain "parameterized" register types are duplicated for a number of
29 * ID multiplied and a "stride" value for the register. Similarly, some
31 * this case, the stride is multiplied by a member of the gsi_ee_id
36 * (for parameterized registers) a non-zero stride value. Not all versions
37 * of IPA define all registers. The offset for a register is returned by
42 * such a register has a unique identifier (from an enumerated type).
43 * The position and width of the fields in a register are defined by
46 * argument. To encode a value to be represented in a register field,
48 * a value encoded in a register field, the field ID is passed to
50 * can be used to either encode the bit value, or to generate a mask
65 IPA_BCR, /* Not IPA v4.5+ */
68 COUNTER_CFG, /* Not IPA v4.5+ */
69 IPA_TX_CFG, /* IPA v3.5+ */
70 FLAVOR_0, /* IPA v3.5+ */
71 IDLE_INDICATION_CFG, /* IPA v3.5+ */
72 QTIME_TIMESTAMP_CFG, /* IPA v4.5+ */
73 TIMERS_XO_CLK_DIV_CFG, /* IPA v4.5+ */
74 TIMERS_PULSE_GRAN_CFG, /* IPA v4.5+ */
77 SRC_RSRC_GRP_45_RSRC_TYPE, /* Not IPA v3.5+, IPA v4.5 */
78 SRC_RSRC_GRP_67_RSRC_TYPE, /* Not IPA v3.5+ */
81 DST_RSRC_GRP_45_RSRC_TYPE, /* Not IPA v3.5+, IPA v4.5 */
82 DST_RSRC_GRP_67_RSRC_TYPE, /* Not IPA v3.5+ */
166 IPA_DCMP_FAST_CLK_EN, /* Not IPA v4.5+ */
185 FULL_FLUSH_WAIT_RS_CLOSURE_EN, /* IPA v4.5+ */
207 CLKON_DCMP, /* IPA v4.5+ */
208 NTF_TX_CMDQS, /* IPA v3.5+ */
209 CLKON_TX_0, /* IPA v3.5+ */
210 CLKON_TX_1, /* IPA v3.5+ */
220 DPL_FIFO, /* IPA v4.5+ */
269 BCR_DUAL_TX = 0x5, /* IPA v3.5+ */
270 BCR_ENABLE_FILTER_DATA_CACHE = 0x6, /* IPA v3.5+ */
271 BCR_NOTIF_PRIORITY_OVER_ZLT = 0x7, /* IPA v3.5+ */
272 BCR_FILTER_PREFETCH_EN = 0x8, /* IPA v3.5+ */
273 BCR_ROUTER_PREFETCH_EN = 0x9, /* IPA v3.5+ */
283 EOT_COAL_GRANULARITY, /* Not v3.5+ */
298 DUAL_TX_ENABLE, /* v4.5+ */
299 SSPND_PA_NO_START_STATE, /* v4,2+, not v4.5 */
375 IPA_CS_OFFLOAD_UL /* TX */ = 0x1, /* Not IPA v4.5+ */
376 IPA_CS_OFFLOAD_DL /* RX */ = 0x2, /* Not IPA v4.5+ */
377 IPA_CS_OFFLOAD_INLINE /* TX and RX */ = 0x1, /* IPA v4.5+ */
402 HDR_METADATA_REG_VALID, /* Not v4.5+ */
403 HDR_LEN_MSB, /* v4.5+ */
404 HDR_OFST_METADATA_MSB, /* v4.5+ */
415 HDR_TOTAL_LEN_OR_PAD_OFFSET_MSB, /* v4.5+ */
416 HDR_OFST_PKT_SIZE_MSB, /* v4.5+ */
417 HDR_ADDITIONAL_CONST_LEN_MSB, /* v4.5+ */
423 DCPH_ENABLE, /* v4.5+ */
428 HDR_FTCH_DISABLE, /* v4.5+ */
478 TIMER_BASE_VALUE, /* Not v4.5+ */
480 TIMER_LIMIT, /* v4.5+ */
481 TIMER_GRAN_SEL, /* v4.5+ */
502 SEQ_REP_TYPE, /* Not v4.5+ */
516 * passes a packet takes through the IPA pipeline. The last pass through can
551 STATUS_LOCATION, /* Not v4.5+ */
616 /* The next bit is not present for IPA v3.5+ */
638 /* The next bit is not present for IPA v4.5+ */
643 /* The next bit is present for IPA v4.5+ */
664 /* Return the field mask for a field in a register */
673 /* Return the mask for a single-bit field in a register */
683 /* Encode a value into the given field of a register */
699 /* Given a register value, decode (extract) the value in the given field */