Lines Matching +full:5 +full:a

5         "Counter": "0,1,2,3,4,5",
8         "PEBScounters": "0,1,2,3,4,5",
15 …": "Counts the number of requests to the instruction cache for one or more bytes of a cache line.",
17         "Counter": "0,1,2,3,4,5",
20         "PEBScounters": "0,1,2,3,4,5",
29         "Counter": "0,1,2,3,4,5",
32         "PEBScounters": "0,1,2,3,4,5",
77         "Counter": "0,1,2,3,4,5,6,7",
83         "PEBScounters": "0,1,2,3,4,5,6,7",
90         "BriefDescription": "Retired Instructions who experienced a critical DSB miss.",
92         "Counter": "0,1,2,3,4,5,6,7",
98         "PEBScounters": "0,1,2,3,4,5,6,7",
107         "Counter": "0,1,2,3,4,5,6,7",
113         "PEBScounters": "0,1,2,3,4,5,6,7",
122         "Counter": "0,1,2,3,4,5,6,7",
128         "PEBScounters": "0,1,2,3,4,5,6,7",
137         "Counter": "0,1,2,3,4,5,6,7",
143         "PEBScounters": "0,1,2,3,4,5,6,7",
152         "Counter": "0,1,2,3,4,5,6,7",
158         "PEBScounters": "0,1,2,3,4,5,6,7",
165 …nterval where the front-end delivered no uops for a period of 128 cycles which was not interrupted…
167         "Counter": "0,1,2,3,4,5,6,7",
173         "PEBScounters": "0,1,2,3,4,5,6,7",
180 …nterval where the front-end delivered no uops for a period of 16 cycles which was not interrupted …
182         "Counter": "0,1,2,3,4,5,6,7",
188         "PEBScounters": "0,1,2,3,4,5,6,7",
197         "Counter": "0,1,2,3,4,5,6,7",
203         "PEBScounters": "0,1,2,3,4,5,6,7",
210 …nterval where the front-end delivered no uops for a period of 256 cycles which was not interrupted…
212         "Counter": "0,1,2,3,4,5,6,7",
218         "PEBScounters": "0,1,2,3,4,5,6,7",
225 …where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not interrupted …
227         "Counter": "0,1,2,3,4,5,6,7",
233         "PEBScounters": "0,1,2,3,4,5,6,7",
240 …nterval where the front-end delivered no uops for a period of 32 cycles which was not interrupted …
242         "Counter": "0,1,2,3,4,5,6,7",
248         "PEBScounters": "0,1,2,3,4,5,6,7",
255 …interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted …
257         "Counter": "0,1,2,3,4,5,6,7",
263         "PEBScounters": "0,1,2,3,4,5,6,7",
270 …nterval where the front-end delivered no uops for a period of 512 cycles which was not interrupted…
272         "Counter": "0,1,2,3,4,5,6,7",
278         "PEBScounters": "0,1,2,3,4,5,6,7",
285 …nterval where the front-end delivered no uops for a period of 64 cycles which was not interrupted …
287         "Counter": "0,1,2,3,4,5,6,7",
293         "PEBScounters": "0,1,2,3,4,5,6,7",
300 …interval where the front-end delivered no uops for a period of 8 cycles which was not interrupted …
302         "Counter": "0,1,2,3,4,5,6,7",
308         "PEBScounters": "0,1,2,3,4,5,6,7",
317         "Counter": "0,1,2,3,4,5,6,7",
323         "PEBScounters": "0,1,2,3,4,5,6,7",
332         "Counter": "0,1,2,3,4,5,6,7",
338         "PEBScounters": "0,1,2,3,4,5,6,7",
347         "Counter": "0,1,2,3,4,5,6,7",
353         "PEBScounters": "0,1,2,3,4,5,6,7",
360 …      "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache miss.",
372 …  "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss.",
501         "Counter": "0,1,2,3,4,5,6,7",
504         "PEBScounters": "0,1,2,3,4,5,6,7",
513         "Counter": "0,1,2,3,4,5,6,7",
517         "PEBScounters": "0,1,2,3,4,5,6,7",
526         "Counter": "0,1,2,3,4,5,6,7",
531         "PEBScounters": "0,1,2,3,4,5,6,7",