Lines Matching +full:5 +full:a
9 …to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Le…
32 …a Uop-cache that holds translations of previously fetched instructions that were decoded by the le…
40 "Counter": "0,1,2,3,4,5,6,7",
46 "PEBScounters": "0,1,2,3,4,5,6,7",
53 "BriefDescription": "Retired Instructions who experienced a critical DSB miss.",
55 "Counter": "0,1,2,3,4,5,6,7",
61 "PEBScounters": "0,1,2,3,4,5,6,7",
62 …erienced a critical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical m…
70 "Counter": "0,1,2,3,4,5,6,7",
76 "PEBScounters": "0,1,2,3,4,5,6,7",
85 "Counter": "0,1,2,3,4,5,6,7",
91 "PEBScounters": "0,1,2,3,4,5,6,7",
100 "Counter": "0,1,2,3,4,5,6,7",
106 "PEBScounters": "0,1,2,3,4,5,6,7",
115 "Counter": "0,1,2,3,4,5,6,7",
121 "PEBScounters": "0,1,2,3,4,5,6,7",
122 …rval where the front-end delivered no uops for a period of at least 1 cycle which was not interrup…
128 …nterval where the front-end delivered no uops for a period of 128 cycles which was not interrupted…
130 "Counter": "0,1,2,3,4,5,6,7",
136 "PEBScounters": "0,1,2,3,4,5,6,7",
137 …nterval where the front-end delivered no uops for a period of 128 cycles which was not interrupted…
143 …nterval where the front-end delivered no uops for a period of 16 cycles which was not interrupted …
145 "Counter": "0,1,2,3,4,5,6,7",
151 "PEBScounters": "0,1,2,3,4,5,6,7",
152 …ion": "Counts retired instructions that are delivered to the back-end after a front-end stall of a…
160 "Counter": "0,1,2,3,4,5,6,7",
166 "PEBScounters": "0,1,2,3,4,5,6,7",
167 …val where the front-end delivered no uops for a period of at least 2 cycles which was not interrup…
173 …nterval where the front-end delivered no uops for a period of 256 cycles which was not interrupted…
175 "Counter": "0,1,2,3,4,5,6,7",
181 "PEBScounters": "0,1,2,3,4,5,6,7",
182 …nterval where the front-end delivered no uops for a period of 256 cycles which was not interrupted…
188 …where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not interrupted …
190 "Counter": "0,1,2,3,4,5,6,7",
196 "PEBScounters": "0,1,2,3,4,5,6,7",
197 … the back-end after the front-end had at least 1 bubble-slot for a period of 2 cycles. A bubble-sl…
203 …nterval where the front-end delivered no uops for a period of 32 cycles which was not interrupted …
205 "Counter": "0,1,2,3,4,5,6,7",
211 "PEBScounters": "0,1,2,3,4,5,6,7",
212 …ion": "Counts retired instructions that are delivered to the back-end after a front-end stall of a…
218 …interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted …
220 "Counter": "0,1,2,3,4,5,6,7",
226 "PEBScounters": "0,1,2,3,4,5,6,7",
227 …interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted …
233 …nterval where the front-end delivered no uops for a period of 512 cycles which was not interrupted…
235 "Counter": "0,1,2,3,4,5,6,7",
241 "PEBScounters": "0,1,2,3,4,5,6,7",
242 …nterval where the front-end delivered no uops for a period of 512 cycles which was not interrupted…
248 …nterval where the front-end delivered no uops for a period of 64 cycles which was not interrupted …
250 "Counter": "0,1,2,3,4,5,6,7",
256 "PEBScounters": "0,1,2,3,4,5,6,7",
257 …nterval where the front-end delivered no uops for a period of 64 cycles which was not interrupted …
263 …interval where the front-end delivered no uops for a period of 8 cycles which was not interrupted …
265 "Counter": "0,1,2,3,4,5,6,7",
271 "PEBScounters": "0,1,2,3,4,5,6,7",
272 …ion": "Counts retired instructions that are delivered to the back-end after a front-end stall of a…
280 "Counter": "0,1,2,3,4,5,6,7",
286 "PEBScounters": "0,1,2,3,4,5,6,7",
294 "Counter": "0,1,2,3,4,5,6,7",
300 "PEBScounters": "0,1,2,3,4,5,6,7",
309 "Counter": "0,1,2,3,4,5,6,7",
315 "PEBScounters": "0,1,2,3,4,5,6,7",
321 … "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache miss.",
327 …tion": "Counts cycles where a code line fetch is stalled due to an L1 instruction cache miss. The …
333 … "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss.",
339 …"PublicDescription": "Counts cycles where a code fetch is stalled due to L1 instruction cache tag …
462 "Counter": "0,1,2,3,4,5,6,7",
465 "PEBScounters": "0,1,2,3,4,5,6,7",
466 …ipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle.",
474 "Counter": "0,1,2,3,4,5,6,7",
478 "PEBScounters": "0,1,2,3,4,5,6,7",
479 …ipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle.",
487 "Counter": "0,1,2,3,4,5,6,7",
492 "PEBScounters": "0,1,2,3,4,5,6,7",
493 …ipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle.",