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/Linux-v6.1/drivers/gpu/drm/amd/include/asic_reg/smu/
Dsmu_7_1_3_sh_mask.h27 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
28 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
29 #define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
30 #define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
31 #define GCK_MCLK_FUSES__StartupMClkDid_MASK 0x7f
32 #define GCK_MCLK_FUSES__StartupMClkDid__SHIFT 0x0
33 #define GCK_MCLK_FUSES__MClkADCA_MASK 0x780
34 #define GCK_MCLK_FUSES__MClkADCA__SHIFT 0x7
35 #define GCK_MCLK_FUSES__MClkDDCA_MASK 0x1800
36 #define GCK_MCLK_FUSES__MClkDDCA__SHIFT 0xb
[all …]
Dsmu_7_1_0_sh_mask.h27 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
28 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
29 #define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
30 #define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
31 #define CG_DCLK_CNTL__DCLK_DIVIDER_MASK 0x7f
32 #define CG_DCLK_CNTL__DCLK_DIVIDER__SHIFT 0x0
33 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK 0x100
34 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT 0x8
35 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG_MASK 0x200
36 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG__SHIFT 0x9
[all …]
Dsmu_7_1_2_sh_mask.h27 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
28 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
29 #define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
30 #define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
31 #define CG_DCLK_CNTL__DCLK_DIVIDER_MASK 0x7f
32 #define CG_DCLK_CNTL__DCLK_DIVIDER__SHIFT 0x0
33 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK 0x100
34 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT 0x8
35 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG_MASK 0x200
36 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG__SHIFT 0x9
[all …]
Dsmu_7_1_1_sh_mask.h27 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
28 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
29 #define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
30 #define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
31 #define CG_DCLK_CNTL__DCLK_DIVIDER_MASK 0x7f
32 #define CG_DCLK_CNTL__DCLK_DIVIDER__SHIFT 0x0
33 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK 0x100
34 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT 0x8
35 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG_MASK 0x200
36 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG__SHIFT 0x9
[all …]
Dsmu_7_0_1_sh_mask.h27 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
28 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
29 #define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
30 #define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
31 #define CG_DCLK_CNTL__DCLK_DIVIDER_MASK 0x7f
32 #define CG_DCLK_CNTL__DCLK_DIVIDER__SHIFT 0x0
33 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK 0x100
34 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT 0x8
35 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG_MASK 0x200
36 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG__SHIFT 0x9
[all …]
/Linux-v6.1/drivers/mtd/nand/raw/
Dpasemi_nand.c25 #define LBICTRL_LPCCTL_NR 0x00004000
36 while (len > 0x800) { in pasemi_read_buf()
37 memcpy_fromio(buf, chip->legacy.IO_ADDR_R, 0x800); in pasemi_read_buf()
38 buf += 0x800; in pasemi_read_buf()
39 len -= 0x800; in pasemi_read_buf()
47 while (len > 0x800) { in pasemi_write_buf()
48 memcpy_toio(chip->legacy.IO_ADDR_R, buf, 0x800); in pasemi_write_buf()
49 buf += 0x800; in pasemi_write_buf()
50 len -= 0x800; in pasemi_write_buf()
82 return 0; in pasemi_attach_chip()
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Dcs553x_nand.c11 * mtd-id for command line partitioning is cs553x_nand_cs[0-3]
12 * where 0-3 reflects the chip select for NAND.
29 #define MSR_DIVIL_GLD_CAP 0x51400000 /* DIVIL capabilitiies */
30 #define CAP_CS5535 0x2df000ULL
31 #define CAP_CS5536 0x5df500ULL
34 #define MSR_NANDF_DATA 0x5140001b /* NAND Flash Data Timing MSR */
35 #define MSR_NANDF_CTL 0x5140001c /* NAND Flash Control Timing */
36 #define MSR_NANDF_RSVD 0x5140001d /* Reserved */
39 #define MSR_DIVIL_LBAR_FLSH0 0x51400010 /* Flash Chip Select 0 */
40 #define MSR_DIVIL_LBAR_FLSH1 0x51400011 /* Flash Chip Select 1 */
[all …]
/Linux-v6.1/drivers/gpu/drm/nouveau/
Dnouveau_reg.h3 #define NV04_PFB_BOOT_0 0x00100000
4 # define NV04_PFB_BOOT_0_RAM_AMOUNT 0x00000003
5 # define NV04_PFB_BOOT_0_RAM_AMOUNT_32MB 0x00000000
6 # define NV04_PFB_BOOT_0_RAM_AMOUNT_4MB 0x00000001
7 # define NV04_PFB_BOOT_0_RAM_AMOUNT_8MB 0x00000002
8 # define NV04_PFB_BOOT_0_RAM_AMOUNT_16MB 0x00000003
9 # define NV04_PFB_BOOT_0_RAM_WIDTH_128 0x00000004
10 # define NV04_PFB_BOOT_0_RAM_TYPE 0x00000028
11 # define NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_8MBIT 0x00000000
12 # define NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_16MBIT 0x00000008
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/media/
Dmediatek,vcodec-decoder.yaml119 reg = <0x16000000 0x100>, /*VDEC_SYS*/
120 <0x16020000 0x1000>, /*VDEC_MISC*/
121 <0x16021000 0x800>, /*VDEC_LD*/
122 <0x16021800 0x800>, /*VDEC_TOP*/
123 <0x16022000 0x1000>, /*VDEC_CM*/
124 <0x16023000 0x1000>, /*VDEC_AD*/
125 <0x16024000 0x1000>, /*VDEC_AV*/
126 <0x16025000 0x1000>, /*VDEC_PP*/
127 <0x16026800 0x800>, /*VP8_VD*/
128 <0x16027000 0x800>, /*VP6_VD*/
[all …]
/Linux-v6.1/arch/sh/include/cpu-sh4a/cpu/
Ddma.h9 #define DMTE0_IRQ evt2irq(0x800)
10 #define DMTE4_IRQ evt2irq(0xb80)
11 #define DMAE0_IRQ evt2irq(0xbc0) /* DMA Error IRQ*/
12 #define SH_DMAC_BASE0 0xFE008020
14 #define DMTE0_IRQ evt2irq(0x800)
15 #define DMTE4_IRQ evt2irq(0xb80)
16 #define DMAE0_IRQ evt2irq(0xbc0) /* DMA Error IRQ*/
17 #define SH_DMAC_BASE0 0xFE008020
19 #define DMTE0_IRQ evt2irq(0x640)
20 #define DMTE4_IRQ evt2irq(0x780)
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/Linux-v6.1/arch/riscv/kernel/
Dmodule.c38 return 0; in apply_r_riscv_32_rela()
44 return 0; in apply_r_riscv_64_rela()
51 u32 imm12 = (offset & 0x1000) << (31 - 12); in apply_r_riscv_branch_rela()
52 u32 imm11 = (offset & 0x800) >> (11 - 7); in apply_r_riscv_branch_rela()
53 u32 imm10_5 = (offset & 0x7e0) << (30 - 10); in apply_r_riscv_branch_rela()
54 u32 imm4_1 = (offset & 0x1e) << (11 - 4); in apply_r_riscv_branch_rela()
56 *location = (*location & 0x1fff07f) | imm12 | imm11 | imm10_5 | imm4_1; in apply_r_riscv_branch_rela()
57 return 0; in apply_r_riscv_branch_rela()
64 u32 imm20 = (offset & 0x100000) << (31 - 20); in apply_r_riscv_jal_rela()
65 u32 imm19_12 = (offset & 0xff000); in apply_r_riscv_jal_rela()
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/hsi/
Domap-ssi.txt37 0 and 1 (in this order).
55 reg = <0x48058000 0x1000>,
56 <0x48059000 0x1000>;
77 reg = <0x4805a000 0x800>,
78 <0x4805a800 0x800>;
92 reg = <0x4805b000 0x800>,
93 <0x4805b800 0x800>;
/Linux-v6.1/arch/arm/boot/dts/
Dsam9x60.dtsi37 #size-cells = <0>;
39 cpu@0 {
42 reg = <0>;
48 reg = <0x20000000 0x10000000>;
54 #clock-cells = <0>;
59 #clock-cells = <0>;
65 reg = <0x00300000 0x100000>;
68 ranges = <0 0x00300000 0x100000>;
79 #size-cells = <0>;
81 reg = <0x00500000 0x100000
[all …]
/Linux-v6.1/drivers/phy/freescale/
Dphy-fsl-lynx-28g.c14 #define LYNX_28G_PCC8 0x10a0
15 #define LYNX_28G_PCC8_SGMII 0x1
16 #define LYNX_28G_PCC8_SGMII_DIS 0x0
18 #define LYNX_28G_PCCC 0x10b0
19 #define LYNX_28G_PCCC_10GBASER 0x9
20 #define LYNX_28G_PCCC_USXGMII 0x1
21 #define LYNX_28G_PCCC_SXGMII_DIS 0x0
26 #define LYNX_28G_PLLnRSTCTL(pll) (0x400 + (pll) * 0x100 + 0x0)
30 #define LYNX_28G_PLLnCR0(pll) (0x400 + (pll) * 0x100 + 0x4)
32 #define LYNX_28G_PLLnCR0_REFCLK_SEL_100MHZ 0x0
[all …]
/Linux-v6.1/arch/m68k/mac/
Dmacboing.c23 static __u8 mac_asc_wave_tab[ 0x800 ];
26 * Alan's original sine table; needs interpolating to 0x800
27 * (hint: interpolate or hardwire [0 -> Pi/2[, it's symmetric)
30 0, 39, 75, 103, 121, 127, 121, 103, 75, 39,
31 0, -39, -75, -103, -121, -127, -121, -103, -75, -39
37 static volatile __u8* mac_asc_regs = ( void* )0x50F14000;
44 static unsigned long mac_bell_phase; /* 0..2*Pi -> 0..0x800 (wavetable size) */
74 * mac_asc_regs[ 0x800 ] & 0xF0 != 0 in mac_init_asc()
84 mac_asc_regs = ( void* )0x50010000; in mac_init_asc()
147 for ( i = 0; i < 0x400; i++ ) in mac_init_asc()
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/Linux-v6.1/Documentation/devicetree/bindings/net/
Dlitex,liteeth.yaml56 minimum: 0x800
57 default: 0x800
78 reg = <0x8021000 0x100>,
79 <0x8020800 0x100>,
80 <0x8030000 0x2000>;
84 litex,slot-size = <0x800>;
85 interrupts = <0x11 0x1>;
90 #size-cells = <0>;
92 eth_phy: ethernet-phy@0 {
93 reg = <0>;
/Linux-v6.1/drivers/gpu/drm/nouveau/nvkm/subdev/privring/
Dgk20a.c29 nvkm_mask(device, 0x137250, 0x3f, 0); in gk20a_privring_init_privring_ring()
31 nvkm_mask(device, 0x000200, 0x20, 0); in gk20a_privring_init_privring_ring()
33 nvkm_mask(device, 0x000200, 0x20, 0x20); in gk20a_privring_init_privring_ring()
35 nvkm_wr32(device, 0x12004c, 0x4); in gk20a_privring_init_privring_ring()
36 nvkm_wr32(device, 0x122204, 0x2); in gk20a_privring_init_privring_ring()
37 nvkm_rd32(device, 0x122204); in gk20a_privring_init_privring_ring()
43 nvkm_wr32(device, 0x122354, 0x800); in gk20a_privring_init_privring_ring()
44 nvkm_wr32(device, 0x128328, 0x800); in gk20a_privring_init_privring_ring()
45 nvkm_wr32(device, 0x124320, 0x800); in gk20a_privring_init_privring_ring()
52 u32 status0 = nvkm_rd32(device, 0x120058); in gk20a_privring_intr()
[all …]
/Linux-v6.1/arch/mips/include/asm/mach-ralink/
Drt3883.h13 #define RT3883_SDRAM_BASE 0x00000000
14 #define RT3883_SYSC_BASE 0x10000000
15 #define RT3883_TIMER_BASE 0x10000100
16 #define RT3883_INTC_BASE 0x10000200
17 #define RT3883_MEMC_BASE 0x10000300
18 #define RT3883_UART0_BASE 0x10000500
19 #define RT3883_PIO_BASE 0x10000600
20 #define RT3883_FSCC_BASE 0x10000700
21 #define RT3883_NANDC_BASE 0x10000810
22 #define RT3883_I2C_BASE 0x10000900
[all …]
/Linux-v6.1/drivers/staging/r8188eu/include/
DHal8188EPhyReg.h8 /* BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF */
10 /* 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00 */
11 /* 3. RF register 0x00-2E */
18 /* 1. Page1(0x100) */
20 #define rPMAC_Reset 0x100
21 #define rPMAC_TxStart 0x104
22 #define rPMAC_TxLegacySIG 0x108
23 #define rPMAC_TxHTSIG1 0x10c
24 #define rPMAC_TxHTSIG2 0x110
25 #define rPMAC_PHYDebug 0x114
[all …]
/Linux-v6.1/drivers/gpu/drm/nouveau/nvkm/engine/disp/
Dgf119.c40 const u32 hoff = 0x800 * head; in gf119_sor_hda_device_entry()
42 nvkm_mask(device, 0x616548 + hoff, 0x00000070, head << 4); in gf119_sor_hda_device_entry()
49 const u32 soff = 0x030 * ior->id + (head * 0x04); in gf119_sor_hda_eld()
52 for (i = 0; i < size; i++) in gf119_sor_hda_eld()
53 nvkm_wr32(device, 0x10ec00 + soff, (i << 8) | data[i]); in gf119_sor_hda_eld()
54 for (; i < 0x60; i++) in gf119_sor_hda_eld()
55 nvkm_wr32(device, 0x10ec00 + soff, (i << 8)); in gf119_sor_hda_eld()
56 nvkm_mask(device, 0x10ec10 + soff, 0x80000002, 0x80000002); in gf119_sor_hda_eld()
63 const u32 soff = 0x030 * ior->id + (head * 0x04); in gf119_sor_hda_hpd()
64 u32 data = 0x80000000; in gf119_sor_hda_hpd()
[all …]
/Linux-v6.1/drivers/net/arcnet/
Darc-rimi.c73 dev->dev_addr[0], dev->mem_start, dev->irq); in arcrimi_probe()
76 if (dev->mem_start <= 0 || dev->irq <= 0) { in arcrimi_probe()
81 if (dev->dev_addr[0] == 0) { in arcrimi_probe()
112 res = 0; in check_mirror()
139 if (request_irq(dev->irq, arcnet_interrupt, 0, "arcnet (RIM I)", dev)) { in arcrimi_found()
159 check_mirror(shmem - MIRROR_SIZE, MIRROR_SIZE) == 0 && in arcrimi_found()
214 dev->dev_addr[0], in arcrimi_found()
223 return 0; in arcrimi_found()
244 void __iomem *ioaddr = lp->mem_start + 0x800; in arcrimi_reset()
250 arcnet_writeb(TESTvalue, ioaddr, -0x800); /* fake reset */ in arcrimi_reset()
[all …]
/Linux-v6.1/arch/powerpc/boot/dts/
Dmpc7448hpc2.dts29 #size-cells =<0>;
31 PowerPC,7448@0 {
33 reg = <0x0>;
36 d-cache-size = <0x8000>; // L1, 32K bytes
37 i-cache-size = <0x8000>; // L1, 32K bytes
38 timebase-frequency = <0>; // 33 MHz, from uboot
39 clock-frequency = <0>; // From U-Boot
40 bus-frequency = <0>; // From U-Boot
46 reg = <0x0 0x20000000 // DDR2 512M at 0
54 ranges = <0x0 0xc0000000 0x10000>;
[all …]
/Linux-v6.1/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_7_2_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_COLOR_CONTROL__DEGAMMA_ENABLE_MASK 0x8
36 #define CB_COLOR_CONTROL__DEGAMMA_ENABLE__SHIFT 0x3
[all …]
/Linux-v6.1/drivers/video/fbdev/aty/
Datyfb.h114 #define DONT_USE_SPLL 0x1
115 #define DONT_USE_XDLL 0x2
116 #define USE_CPUCLK 0x4
117 #define POWERDOWN_PLL 0x8
199 #define M64F_RESET_3D 0x00000001
200 #define M64F_MAGIC_FIFO 0x00000002
201 #define M64F_GTB_DSP 0x00000004
202 #define M64F_FIFO_32 0x00000008
203 #define M64F_SDRAM_MAGIC_PLL 0x00000010
204 #define M64F_MAGIC_POSTDIV 0x00000020
[all …]
/Linux-v6.1/drivers/gpu/drm/msm/adreno/
Da6xx_gpu_state.h13 0x8000, 0x8006, 0x8010, 0x8092, 0x8094, 0x809d, 0x80a0, 0x80a6,
14 0x80af, 0x80f1, 0x8100, 0x8107, 0x8109, 0x8109, 0x8110, 0x8110,
15 0x8400, 0x840b,
19 0x8800, 0x8806, 0x8809, 0x8811, 0x8818, 0x881e, 0x8820, 0x8865,
20 0x8870, 0x8879, 0x8880, 0x8889, 0x8890, 0x8891, 0x8898, 0x8898,
21 0x88c0, 0x88c1, 0x88d0, 0x88e3, 0x8900, 0x890c, 0x890f, 0x891a,
22 0x8c00, 0x8c01, 0x8c08, 0x8c10, 0x8c17, 0x8c1f, 0x8c26, 0x8c33,
26 0x88f0, 0x88f3, 0x890d, 0x890e, 0x8927, 0x8928, 0x8bf0, 0x8bf1,
27 0x8c02, 0x8c07, 0x8c11, 0x8c16, 0x8c20, 0x8c25,
31 0x9200, 0x9216, 0x9218, 0x9236, 0x9300, 0x9306,
[all …]

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