14 #define LYNX_28G_PCC8				0x10a0
15 #define LYNX_28G_PCC8_SGMII			0x1
16 #define LYNX_28G_PCC8_SGMII_DIS			0x0
18 #define LYNX_28G_PCCC				0x10b0
19 #define LYNX_28G_PCCC_10GBASER			0x9
20 #define LYNX_28G_PCCC_USXGMII			0x1
21 #define LYNX_28G_PCCC_SXGMII_DIS		0x0
26 #define LYNX_28G_PLLnRSTCTL(pll)		(0x400 + (pll) * 0x100 + 0x0)
30 #define LYNX_28G_PLLnCR0(pll)			(0x400 + (pll) * 0x100 + 0x4)
32 #define LYNX_28G_PLLnCR0_REFCLK_SEL_100MHZ	0x0
33 #define LYNX_28G_PLLnCR0_REFCLK_SEL_125MHZ	0x10000
34 #define LYNX_28G_PLLnCR0_REFCLK_SEL_156MHZ	0x20000
35 #define LYNX_28G_PLLnCR0_REFCLK_SEL_150MHZ	0x30000
36 #define LYNX_28G_PLLnCR0_REFCLK_SEL_161MHZ	0x40000
38 #define LYNX_28G_PLLnCR1(pll)			(0x400 + (pll) * 0x100 + 0x8)
40 #define LYNX_28G_PLLnCR1_FRATE_5G_10GVCO	0x0
41 #define LYNX_28G_PLLnCR1_FRATE_5G_25GVCO	0x10000000
42 #define LYNX_28G_PLLnCR1_FRATE_10G_20GVCO	0x6000000
46 #define LYNX_28G_LNaGCR0(lane)			(0x800 + (lane) * 0x100 + 0x0)
48 #define LYNX_28G_LNaGCR0_PROTO_SEL_SGMII	0x8
49 #define LYNX_28G_LNaGCR0_PROTO_SEL_XFI		0x50
50 #define LYNX_28G_LNaGCR0_IF_WIDTH_MSK		GENMASK(2, 0)
51 #define LYNX_28G_LNaGCR0_IF_WIDTH_10_BIT	0x0
52 #define LYNX_28G_LNaGCR0_IF_WIDTH_20_BIT	0x2
55 #define LYNX_28G_LNaTRSTCTL(lane)		(0x800 + (lane) * 0x100 + 0x20)
61 #define LYNX_28G_LNaTGCR0(lane)			(0x800 + (lane) * 0x100 + 0x24)
62 #define LYNX_28G_LNaTGCR0_USE_PLLF		0x0
65 #define LYNX_28G_LNaTGCR0_N_RATE_FULL		0x0
66 #define LYNX_28G_LNaTGCR0_N_RATE_HALF		0x1000000
67 #define LYNX_28G_LNaTGCR0_N_RATE_QUARTER	0x2000000
70 #define LYNX_28G_LNaTECR0(lane)			(0x800 + (lane) * 0x100 + 0x30)
73 #define LYNX_28G_LNaRRSTCTL(lane)		(0x800 + (lane) * 0x100 + 0x40)
80 #define LYNX_28G_LNaRGCR0(lane)			(0x800 + (lane) * 0x100 + 0x44)
81 #define LYNX_28G_LNaRGCR0_USE_PLLF		0x0
85 #define LYNX_28G_LNaRGCR0_N_RATE_FULL		0x0
86 #define LYNX_28G_LNaRGCR0_N_RATE_HALF		0x1000000
87 #define LYNX_28G_LNaRGCR0_N_RATE_QUARTER	0x2000000
90 #define LYNX_28G_LNaRGCR1(lane)			(0x800 + (lane) * 0x100 + 0x48)
92 #define LYNX_28G_LNaRECR0(lane)			(0x800 + (lane) * 0x100 + 0x50)
93 #define LYNX_28G_LNaRECR1(lane)			(0x800 + (lane) * 0x100 + 0x54)
94 #define LYNX_28G_LNaRECR2(lane)			(0x800 + (lane) * 0x100 + 0x58)
96 #define LYNX_28G_LNaRSCCR0(lane)		(0x800 + (lane) * 0x100 + 0x74)
98 #define LYNX_28G_LNaPSS(lane)			(0x1000 + (lane) * 0x4)
100 #define LYNX_28G_LNaPSS_TYPE_SGMII		0x4
101 #define LYNX_28G_LNaPSS_TYPE_XFI		0x28
103 #define LYNX_28G_SGMIIaCR1(lane)		(0x1804 + (lane) * 0x10)
105 #define LYNX_28G_SGMIIaCR1_SGPCS_DIS		0x0
159 	for (i = 0; i < LYNX_28G_NUM_PLL; i++) {  in lynx_28g_supports_interface()
176 	for (i = 0; i < LYNX_28G_NUM_PLL; i++) {  in lynx_28g_pll_get()
225 	if (pll->id == 0) {  in lynx_28g_lane_set_pll()
244 			     GENMASK(3, 0) << lane_offset);  in lynx_28g_cleanup_lane()
250 			     GENMASK(3, 0) << lane_offset);  in lynx_28g_cleanup_lane()
268 		     GENMASK(3, 0) << lane_offset);  in lynx_28g_lane_set_sgmii()
285 	iowrite32(0x00808006, priv->base + LYNX_28G_LNaTECR0(lane->id));  in lynx_28g_lane_set_sgmii()
286 	iowrite32(0x04310000, priv->base + LYNX_28G_LNaRGCR1(lane->id));  in lynx_28g_lane_set_sgmii()
287 	iowrite32(0x9f800000, priv->base + LYNX_28G_LNaRECR0(lane->id));  in lynx_28g_lane_set_sgmii()
288 	iowrite32(0x001f0000, priv->base + LYNX_28G_LNaRECR1(lane->id));  in lynx_28g_lane_set_sgmii()
289 	iowrite32(0x00000000, priv->base + LYNX_28G_LNaRECR2(lane->id));  in lynx_28g_lane_set_sgmii()
290 	iowrite32(0x00000000, priv->base + LYNX_28G_LNaRSCCR0(lane->id));  in lynx_28g_lane_set_sgmii()
304 		     GENMASK(3, 0) << lane_offset);  in lynx_28g_lane_set_10gbaser()
321 	iowrite32(0x10808307, priv->base + LYNX_28G_LNaTECR0(lane->id));  in lynx_28g_lane_set_10gbaser()
322 	iowrite32(0x10000000, priv->base + LYNX_28G_LNaRGCR1(lane->id));  in lynx_28g_lane_set_10gbaser()
323 	iowrite32(0x00000000, priv->base + LYNX_28G_LNaRECR0(lane->id));  in lynx_28g_lane_set_10gbaser()
324 	iowrite32(0x001f0000, priv->base + LYNX_28G_LNaRECR1(lane->id));  in lynx_28g_lane_set_10gbaser()
325 	iowrite32(0x81000020, priv->base + LYNX_28G_LNaRECR2(lane->id));  in lynx_28g_lane_set_10gbaser()
326 	iowrite32(0x00002000, priv->base + LYNX_28G_LNaRSCCR0(lane->id));  in lynx_28g_lane_set_10gbaser()
335 		return 0;  in lynx_28g_power_off()
350 	return 0;  in lynx_28g_power_off()
359 		return 0;  in lynx_28g_power_on()
374 	return 0;  in lynx_28g_power_on()
382 	int err = 0;  in lynx_28g_set_mode()
434 	return 0;  in lynx_28g_validate()
451 	return 0;  in lynx_28g_init()
468 	for (i = 0; i < LYNX_28G_NUM_PLL; i++) {  in lynx_28g_pll_read_configuration()
507 	for (i = 0; i < LYNX_28G_NUM_LANE; i++) {  in lynx_28g_cdr_lock_check()
550 	int idx = args->args[0];  in lynx_28g_xlate()
570 	priv->base = devm_platform_ioremap_resource(pdev, 0);  in lynx_28g_probe()
576 	for (i = 0; i < LYNX_28G_NUM_LANE; i++) {  in lynx_28g_probe()
580 		memset(lane, 0, sizeof(*lane));  in lynx_28g_probe()