Lines Matching +full:0 +full:x800
37 #size-cells = <0>;
39 cpu@0 {
42 reg = <0>;
48 reg = <0x20000000 0x10000000>;
54 #clock-cells = <0>;
59 #clock-cells = <0>;
65 reg = <0x00300000 0x100000>;
68 ranges = <0 0x00300000 0x100000>;
79 #size-cells = <0>;
81 reg = <0x00500000 0x100000
82 0xf803c000 0x400>;
93 reg = <0x00600000 0x100000>;
102 reg = <0x00700000 0x100000>;
117 reg = <0x10000000 0x60000000>;
118 ranges = <0x0 0x0 0x10000000 0x10000000
119 0x1 0x0 0x20000000 0x10000000
120 0x2 0x0 0x30000000 0x10000000
121 0x3 0x0 0x40000000 0x10000000
122 0x4 0x0 0x50000000 0x10000000
123 0x5 0x0 0x60000000 0x10000000>;
139 reg = <0x80000000 0x300>;
140 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
150 reg = <0x90000000 0x300>;
151 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>;
167 reg = <0xf0000000 0x200>;
171 ranges = <0x0 0xf0000000 0x800>;
177 reg = <0xf0004000 0x200>;
181 ranges = <0x0 0xf0004000 0x800>;
187 reg = <0xf0008000 0x1000>;
188 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
196 reg = <0xf0010000 0x4000>;
199 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
202 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
212 reg = <0xf0014000 0x100>, <0x70000000 0x10000000>;
216 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
219 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
226 #size-cells = <0>;
232 reg = <0xf001c000 0x100>;
235 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
238 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
248 reg = <0xf0020000 0x200>;
252 ranges = <0x0 0xf0020000 0x800>;
258 reg = <0xf0024000 0x200>;
262 ranges = <0x0 0xf0024000 0x800>;
268 reg = <0xf0028000 0x100>;
276 reg = <0xf002c000 0x100>;
277 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 0>;
279 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
288 reg = <0xf0030000 0x100>;
289 interrupts = <38 IRQ_TYPE_LEVEL_HIGH 0>;
295 reg = <0xf0034000 0x100>;
296 interrupts = <39 IRQ_TYPE_LEVEL_HIGH 0>;
298 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
301 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
310 reg = <0xf0038000 0x100>;
311 interrupts = <40 IRQ_TYPE_LEVEL_HIGH 0>;
313 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
316 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
325 reg = <0xf003c000 0x100>;
328 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
338 reg = <0xf8000000 0x300>;
347 reg = <0xf8004000 0x300>;
357 #size-cells = <0>;
358 reg = <0xf8008000 0x100>;
359 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
360 clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&clk32k 0>;
367 #size-cells = <0>;
368 reg = <0xf800c000 0x100>;
369 interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>;
370 clocks = <&pmc PMC_TYPE_PERIPHERAL 45>, <&clk32k 0>;
376 reg = <0xf8010000 0x200>;
380 ranges = <0x0 0xf8010000 0x800>;
386 reg = <0xf8014000 0x200>;
390 ranges = <0x0 0xf8014000 0x800>;
396 reg = <0xf8018000 0x200>;
400 ranges = <0x0 0xf8018000 0x800>;
406 reg = <0xf801c000 0x200>;
410 ranges = <0x0 0xf801c000 0x800>;
416 reg = <0xf8020000 0x200>;
420 ranges = <0x0 0xf8020000 0x800>;
426 reg = <0xf8024000 0x200>;
430 ranges = <0x0 0xf8024000 0x800>;
436 reg = <0xf8028000 0x200>;
440 ranges = <0x0 0xf8028000 0x800>;
446 reg = <0xf802c000 0x1000>;
455 reg = <0xf8030000 0x1000>;
464 reg = <0xf8034000 0x300>;
473 reg = <0xf8038000 0x4000>;
474 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 0>;
484 #size-cells = <0>;
486 port@0 {
488 #size-cells = <0>;
489 reg = <0>;
501 reg = <0xf8040000 0x200>;
505 ranges = <0x0 0xf8040000 0x800>;
511 reg = <0xf8044000 0x200>;
515 ranges = <0x0 0xf8044000 0x800>;
521 reg = <0xf8048000 0x100>;
528 #size-cells = <0>;
534 reg = <0xf804c000 0x100>;
538 dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(40))>;
550 reg = <0xf8050000 0x100>;
555 reg = <0xffffde00 0x200>;
560 reg = <0xffffe000 0x300>,
561 <0xffffe600 0x100>;
566 reg = <0xffffe800 0x200>;
573 reg = <0xffffea00 0x100>;
580 reg = <0xfffff100 0x100>;
586 reg = <0xfffff200 0x200>;
590 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
593 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
605 ranges = <0xfffff400 0xfffff400 0x800>;
610 0xffffffff 0xffe03fff 0xef00019d /* pioA */
611 0x03ffffff 0x02fc7e7f 0x00780000 /* pioB */
612 0xffffffff 0xffffffff 0xf83fffff /* pioC */
613 0x003fffff 0x003f8000 0x00000000 /* pioD */
618 reg = <0xfffff400 0x200>;
629 reg = <0xfffff600 0x200>;
641 reg = <0xfffff800 0x200>;
652 reg = <0xfffffa00 0x200>;
665 reg = <0xfffffc00 0x200>;
668 clocks = <&clk32k 1>, <&clk32k 0>, <&main_xtal>;
674 reg = <0xfffffe00 0x10>;
675 clocks = <&clk32k 0>;
680 reg = <0xfffffe10 0x10>;
681 clocks = <&clk32k 0>;
683 #size-cells = <0>;
691 reg = <0xfffffe20 0x20>;
693 clocks = <&clk32k 0>;
698 reg = <0xfffffe40 0x10>;
705 reg = <0xfffffe50 0x4>;
712 reg = <0xfffffe60 0x10>;
717 reg = <0xfffffea8 0x100>;
719 clocks = <&clk32k 0>;
724 reg = <0xffffff80 0x24>;
726 clocks = <&clk32k 0>;