Lines Matching +full:0 +full:x800
40 const u32 hoff = 0x800 * head; in gf119_sor_hda_device_entry()
42 nvkm_mask(device, 0x616548 + hoff, 0x00000070, head << 4); in gf119_sor_hda_device_entry()
49 const u32 soff = 0x030 * ior->id + (head * 0x04); in gf119_sor_hda_eld()
52 for (i = 0; i < size; i++) in gf119_sor_hda_eld()
53 nvkm_wr32(device, 0x10ec00 + soff, (i << 8) | data[i]); in gf119_sor_hda_eld()
54 for (; i < 0x60; i++) in gf119_sor_hda_eld()
55 nvkm_wr32(device, 0x10ec00 + soff, (i << 8)); in gf119_sor_hda_eld()
56 nvkm_mask(device, 0x10ec10 + soff, 0x80000002, 0x80000002); in gf119_sor_hda_eld()
63 const u32 soff = 0x030 * ior->id + (head * 0x04); in gf119_sor_hda_hpd()
64 u32 data = 0x80000000; in gf119_sor_hda_hpd()
65 u32 mask = 0x80000001; in gf119_sor_hda_hpd()
69 data |= 0x00000001; in gf119_sor_hda_hpd()
71 mask |= 0x00000002; in gf119_sor_hda_hpd()
74 nvkm_mask(device, 0x10ec10 + soff, mask, data); in gf119_sor_hda_hpd()
88 const u32 hoff = head * 0x800; in gf119_sor_dp_watermark()
90 nvkm_mask(device, 0x616610 + hoff, 0x0800003f, 0x08000000 | watermark); in gf119_sor_dp_watermark()
97 const u32 hoff = head * 0x800; in gf119_sor_dp_audio_sym()
99 nvkm_mask(device, 0x616620 + hoff, 0x0000ffff, h); in gf119_sor_dp_audio_sym()
100 nvkm_mask(device, 0x616624 + hoff, 0x00ffffff, v); in gf119_sor_dp_audio_sym()
107 const u32 hoff = 0x800 * head; in gf119_sor_dp_audio()
108 const u32 data = 0x80000000 | (0x00000001 * enable); in gf119_sor_dp_audio()
109 const u32 mask = 0x8000000d; in gf119_sor_dp_audio()
111 nvkm_mask(device, 0x616618 + hoff, mask, data); in gf119_sor_dp_audio()
113 if (!(nvkm_rd32(device, 0x616618 + hoff) & 0x80000000)) in gf119_sor_dp_audio()
122 const u32 hoff = head * 0x800; in gf119_sor_dp_vcpi()
124 nvkm_mask(device, 0x616588 + hoff, 0x00003f3f, (slot_nr << 8) | slot); in gf119_sor_dp_vcpi()
125 nvkm_mask(device, 0x61658c + hoff, 0xffffffff, (aligned << 16) | pbn); in gf119_sor_dp_vcpi()
136 data[0] = nvkm_rd32(device, 0x61c118 + loff) & ~(0x000000ff << shift); in gf119_sor_dp_drive()
137 data[1] = nvkm_rd32(device, 0x61c120 + loff) & ~(0x000000ff << shift); in gf119_sor_dp_drive()
138 data[2] = nvkm_rd32(device, 0x61c130 + loff); in gf119_sor_dp_drive()
139 if ((data[2] & 0x0000ff00) < (pu << 8) || ln == 0) in gf119_sor_dp_drive()
140 data[2] = (data[2] & ~0x0000ff00) | (pu << 8); in gf119_sor_dp_drive()
142 nvkm_wr32(device, 0x61c118 + loff, data[0] | (dc << shift)); in gf119_sor_dp_drive()
143 nvkm_wr32(device, 0x61c120 + loff, data[1] | (pe << shift)); in gf119_sor_dp_drive()
144 nvkm_wr32(device, 0x61c130 + loff, data[2]); in gf119_sor_dp_drive()
146 data[3] = nvkm_rd32(device, 0x61c13c + loff) & ~(0x000000ff << shift); in gf119_sor_dp_drive()
147 nvkm_wr32(device, 0x61c13c + loff, data[3] | (pc << shift)); in gf119_sor_dp_drive()
158 case 0: data = 0x10101010; break; in gf119_sor_dp_pattern()
159 case 1: data = 0x01010101; break; in gf119_sor_dp_pattern()
160 case 2: data = 0x02020202; break; in gf119_sor_dp_pattern()
161 case 3: data = 0x03030303; break; in gf119_sor_dp_pattern()
167 nvkm_mask(device, 0x61c110 + soff, 0x1f1f1f1f, data); in gf119_sor_dp_pattern()
176 u32 dpctrl = 0x00000000; in gf119_sor_dp_links()
177 u32 clksor = 0x00000000; in gf119_sor_dp_links()
182 dpctrl |= 0x40000000; in gf119_sor_dp_links()
184 dpctrl |= 0x00004000; in gf119_sor_dp_links()
186 nvkm_mask(device, 0x612300 + soff, 0x007c0000, clksor); in gf119_sor_dp_links()
187 nvkm_mask(device, 0x61c10c + loff, 0x401f4000, dpctrl); in gf119_sor_dp_links()
188 return 0; in gf119_sor_dp_links()
193 .lanes = { 2, 1, 0, 3 },
209 const u32 ctrl = 0x40000000 * enable | in gf119_sor_hdmi_ctrl()
212 const u32 hoff = head * 0x800; in gf119_sor_hdmi_ctrl()
219 if (!(ctrl & 0x40000000)) { in gf119_sor_hdmi_ctrl()
220 nvkm_mask(device, 0x616798 + hoff, 0x40000000, 0x00000000); in gf119_sor_hdmi_ctrl()
221 nvkm_mask(device, 0x616730 + hoff, 0x00000001, 0x00000000); in gf119_sor_hdmi_ctrl()
222 nvkm_mask(device, 0x6167a4 + hoff, 0x00000001, 0x00000000); in gf119_sor_hdmi_ctrl()
223 nvkm_mask(device, 0x616714 + hoff, 0x00000001, 0x00000000); in gf119_sor_hdmi_ctrl()
228 nvkm_mask(device, 0x616714 + hoff, 0x00000001, 0x00000000); in gf119_sor_hdmi_ctrl()
230 nvkm_wr32(device, 0x61671c + hoff, avi_infoframe.header); in gf119_sor_hdmi_ctrl()
231 nvkm_wr32(device, 0x616720 + hoff, avi_infoframe.subpack0_low); in gf119_sor_hdmi_ctrl()
232 nvkm_wr32(device, 0x616724 + hoff, avi_infoframe.subpack0_high); in gf119_sor_hdmi_ctrl()
233 nvkm_wr32(device, 0x616728 + hoff, avi_infoframe.subpack1_low); in gf119_sor_hdmi_ctrl()
234 nvkm_wr32(device, 0x61672c + hoff, avi_infoframe.subpack1_high); in gf119_sor_hdmi_ctrl()
235 nvkm_mask(device, 0x616714 + hoff, 0x00000001, 0x00000001); in gf119_sor_hdmi_ctrl()
239 nvkm_mask(device, 0x616730 + hoff, 0x00010001, 0x00010000); in gf119_sor_hdmi_ctrl()
246 nvkm_wr32(device, 0x616738 + hoff, vendor_infoframe.header); in gf119_sor_hdmi_ctrl()
247 nvkm_wr32(device, 0x61673c + hoff, vendor_infoframe.subpack0_low); in gf119_sor_hdmi_ctrl()
248 nvkm_wr32(device, 0x616740 + hoff, vendor_infoframe.subpack0_high); in gf119_sor_hdmi_ctrl()
250 nvkm_mask(device, 0x616730 + hoff, 0x00000001, 0x00000001); in gf119_sor_hdmi_ctrl()
254 nvkm_mask(device, 0x6167a4 + hoff, 0x00000001, 0x00000000); in gf119_sor_hdmi_ctrl()
255 nvkm_wr32(device, 0x6167ac + hoff, 0x00000010); in gf119_sor_hdmi_ctrl()
256 nvkm_mask(device, 0x6167a4 + hoff, 0x00000001, 0x00000001); in gf119_sor_hdmi_ctrl()
259 nvkm_mask(device, 0x616798 + hoff, 0x401f007f, ctrl); in gf119_sor_hdmi_ctrl()
271 const u32 speed = sor->tmds.high_speed ? 0x14 : 0x0a; in gf119_sor_clock()
272 nvkm_mask(device, 0x612300 + soff, 0x007c0000, speed << 18); in gf119_sor_clock()
277 nvkm_mask(device, 0x612300 + soff, 0x00000707, (div2 << 8) | div1); in gf119_sor_clock()
284 const u32 coff = (state == &sor->asy) * 0x20000 + sor->id * 0x20; in gf119_sor_state()
285 u32 ctrl = nvkm_rd32(device, 0x640200 + coff); in gf119_sor_state()
287 state->proto_evo = (ctrl & 0x00000f00) >> 8; in gf119_sor_state()
289 case 0: state->proto = LVDS; state->link = 1; break; in gf119_sor_state()
300 state->head = ctrl & 0x0000000f; in gf119_sor_state()
325 *pmask = (nvkm_rd32(device, 0x612004) & 0x0000ff00) >> 8; in gf119_sor_cnt()
334 nvkm_mask(device, 0x612280 + doff, 0x07070707, 0x00000000); in gf119_dac_clock()
341 const u32 coff = (state == &dac->asy) * 0x20000 + dac->id * 0x20; in gf119_dac_state()
342 u32 ctrl = nvkm_rd32(device, 0x640180 + coff); in gf119_dac_state()
344 state->proto_evo = (ctrl & 0x00000f00) >> 8; in gf119_dac_state()
346 case 0: state->proto = CRT; break; in gf119_dac_state()
352 state->head = ctrl & 0x0000000f; in gf119_dac_state()
373 *pmask = (nvkm_rd32(device, 0x612004) & 0x000000f0) >> 4; in gf119_dac_cnt()
381 const u32 hoff = head->id * 0x800; in gf119_head_vblank_put()
382 nvkm_mask(device, 0x6100c0 + hoff, 0x00000001, 0x00000000); in gf119_head_vblank_put()
389 const u32 hoff = head->id * 0x800; in gf119_head_vblank_get()
390 nvkm_mask(device, 0x6100c0 + hoff, 0x00000001, 0x00000001); in gf119_head_vblank_get()
397 nvkm_mask(device, 0x612200 + (head->id * 0x800), 0x0000000f, div); in gf119_head_rgclk()
404 const u32 hoff = (state == &head->asy) * 0x20000 + head->id * 0x300; in gf119_head_state()
407 data = nvkm_rd32(device, 0x640414 + hoff); in gf119_head_state()
408 state->vtotal = (data & 0xffff0000) >> 16; in gf119_head_state()
409 state->htotal = (data & 0x0000ffff); in gf119_head_state()
410 data = nvkm_rd32(device, 0x640418 + hoff); in gf119_head_state()
411 state->vsynce = (data & 0xffff0000) >> 16; in gf119_head_state()
412 state->hsynce = (data & 0x0000ffff); in gf119_head_state()
413 data = nvkm_rd32(device, 0x64041c + hoff); in gf119_head_state()
414 state->vblanke = (data & 0xffff0000) >> 16; in gf119_head_state()
415 state->hblanke = (data & 0x0000ffff); in gf119_head_state()
416 data = nvkm_rd32(device, 0x640420 + hoff); in gf119_head_state()
417 state->vblanks = (data & 0xffff0000) >> 16; in gf119_head_state()
418 state->hblanks = (data & 0x0000ffff); in gf119_head_state()
419 state->hz = nvkm_rd32(device, 0x640450 + hoff); in gf119_head_state()
421 data = nvkm_rd32(device, 0x640404 + hoff); in gf119_head_state()
422 switch ((data & 0x000003c0) >> 6) { in gf119_head_state()
426 case 0: state->or.depth = 18; break; /*XXX: "default" */ in gf119_head_state()
453 *pmask = nvkm_rd32(device, 0x612004) & 0x0000000f; in gf119_head_cnt()
454 return nvkm_rd32(device, 0x022448); in gf119_head_cnt()
462 nvkm_mask(device, 0x610090, 0x00000001 << index, 0x00000000 << index); in gf119_disp_chan_uevent_fini()
463 nvkm_wr32(device, 0x61008c, 0x00000001 << index); in gf119_disp_chan_uevent_fini()
471 nvkm_wr32(device, 0x61008c, 0x00000001 << index); in gf119_disp_chan_uevent_init()
472 nvkm_mask(device, 0x610090, 0x00000001 << index, 0x00000001 << index); in gf119_disp_chan_uevent_init()
485 const u32 mask = 0x00000001 << chan->chid.user; in gf119_disp_chan_intr()
487 nvkm_mask(device, 0x610090, mask, 0x00000000); in gf119_disp_chan_intr()
488 nvkm_mask(device, 0x6100a0, mask, 0x00000000); in gf119_disp_chan_intr()
490 nvkm_mask(device, 0x6100a0, mask, mask); in gf119_disp_chan_intr()
503 nvkm_mask(device, 0x610490 + (ctrl * 0x10), 0x00000001, 0x00000000); in gf119_disp_pioc_fini()
505 if (!(nvkm_rd32(device, 0x610490 + (ctrl * 0x10)) & 0x00030000)) in gf119_disp_pioc_fini()
507 ) < 0) { in gf119_disp_pioc_fini()
509 nvkm_rd32(device, 0x610490 + (ctrl * 0x10))); in gf119_disp_pioc_fini()
523 nvkm_wr32(device, 0x610490 + (ctrl * 0x10), 0x00000001); in gf119_disp_pioc_init()
525 u32 tmp = nvkm_rd32(device, 0x610490 + (ctrl * 0x10)); in gf119_disp_pioc_init()
526 if ((tmp & 0x00030000) == 0x00010000) in gf119_disp_pioc_init()
528 ) < 0) { in gf119_disp_pioc_init()
530 nvkm_rd32(device, 0x610490 + (ctrl * 0x10))); in gf119_disp_pioc_init()
534 return 0; in gf119_disp_pioc_init()
549 chan->chid.user << 27 | 0x00000001); in gf119_disp_dmac_bind()
561 nvkm_mask(device, 0x610490 + (ctrl * 0x0010), 0x00001010, 0x00001000); in gf119_disp_dmac_fini()
562 nvkm_mask(device, 0x610490 + (ctrl * 0x0010), 0x00000003, 0x00000000); in gf119_disp_dmac_fini()
564 if (!(nvkm_rd32(device, 0x610490 + (ctrl * 0x10)) & 0x001e0000)) in gf119_disp_dmac_fini()
566 ) < 0) { in gf119_disp_dmac_fini()
568 nvkm_rd32(device, 0x610490 + (ctrl * 0x10))); in gf119_disp_dmac_fini()
571 chan->suspend_put = nvkm_rd32(device, 0x640000 + (ctrl * 0x1000)); in gf119_disp_dmac_fini()
583 nvkm_wr32(device, 0x610494 + (ctrl * 0x0010), chan->push); in gf119_disp_dmac_init()
584 nvkm_wr32(device, 0x610498 + (ctrl * 0x0010), 0x00010000); in gf119_disp_dmac_init()
585 nvkm_wr32(device, 0x61049c + (ctrl * 0x0010), 0x00000001); in gf119_disp_dmac_init()
586 nvkm_mask(device, 0x610490 + (ctrl * 0x0010), 0x00000010, 0x00000010); in gf119_disp_dmac_init()
587 nvkm_wr32(device, 0x640000 + (ctrl * 0x1000), chan->suspend_put); in gf119_disp_dmac_init()
588 nvkm_wr32(device, 0x610490 + (ctrl * 0x0010), 0x00000013); in gf119_disp_dmac_init()
592 if (!(nvkm_rd32(device, 0x610490 + (ctrl * 0x10)) & 0x80000000)) in gf119_disp_dmac_init()
594 ) < 0) { in gf119_disp_dmac_init()
596 nvkm_rd32(device, 0x610490 + (ctrl * 0x10))); in gf119_disp_dmac_init()
600 return 0; in gf119_disp_dmac_init()
629 .mthd = 0x0000,
631 { 0x0080, 0x665080 },
632 { 0x0084, 0x665084 },
633 { 0x0088, 0x665088 },
634 { 0x008c, 0x66508c },
635 { 0x0090, 0x665090 },
636 { 0x0094, 0x665094 },
637 { 0x00a0, 0x6650a0 },
638 { 0x00a4, 0x6650a4 },
639 { 0x00b0, 0x6650b0 },
640 { 0x00b4, 0x6650b4 },
641 { 0x00b8, 0x6650b8 },
642 { 0x00c0, 0x6650c0 },
643 { 0x00e0, 0x6650e0 },
644 { 0x00e4, 0x6650e4 },
645 { 0x00e8, 0x6650e8 },
646 { 0x0100, 0x665100 },
647 { 0x0104, 0x665104 },
648 { 0x0108, 0x665108 },
649 { 0x010c, 0x66510c },
650 { 0x0110, 0x665110 },
651 { 0x0118, 0x665118 },
652 { 0x011c, 0x66511c },
653 { 0x0120, 0x665120 },
654 { 0x0124, 0x665124 },
655 { 0x0130, 0x665130 },
656 { 0x0134, 0x665134 },
657 { 0x0138, 0x665138 },
658 { 0x013c, 0x66513c },
659 { 0x0140, 0x665140 },
660 { 0x0144, 0x665144 },
661 { 0x0148, 0x665148 },
662 { 0x014c, 0x66514c },
663 { 0x0150, 0x665150 },
664 { 0x0154, 0x665154 },
665 { 0x0158, 0x665158 },
666 { 0x015c, 0x66515c },
667 { 0x0160, 0x665160 },
668 { 0x0164, 0x665164 },
669 { 0x0168, 0x665168 },
670 { 0x016c, 0x66516c },
671 { 0x0400, 0x665400 },
672 { 0x0408, 0x665408 },
673 { 0x040c, 0x66540c },
674 { 0x0410, 0x665410 },
682 .addr = 0x001000,
683 .prev = -0x020000,
700 .mthd = 0x0000,
701 .addr = 0x000000,
703 { 0x0080, 0x661080 },
704 { 0x0084, 0x661084 },
705 { 0x0088, 0x661088 },
706 { 0x008c, 0x66108c },
707 { 0x0090, 0x661090 },
708 { 0x0094, 0x661094 },
709 { 0x00a0, 0x6610a0 },
710 { 0x00a4, 0x6610a4 },
711 { 0x00c0, 0x6610c0 },
712 { 0x00c4, 0x6610c4 },
713 { 0x00c8, 0x6610c8 },
714 { 0x00cc, 0x6610cc },
715 { 0x00e0, 0x6610e0 },
716 { 0x00e4, 0x6610e4 },
717 { 0x00e8, 0x6610e8 },
718 { 0x00ec, 0x6610ec },
719 { 0x00fc, 0x6610fc },
720 { 0x0100, 0x661100 },
721 { 0x0104, 0x661104 },
722 { 0x0108, 0x661108 },
723 { 0x010c, 0x66110c },
724 { 0x0110, 0x661110 },
725 { 0x0114, 0x661114 },
726 { 0x0118, 0x661118 },
727 { 0x011c, 0x66111c },
728 { 0x0130, 0x661130 },
729 { 0x0134, 0x661134 },
730 { 0x0138, 0x661138 },
731 { 0x013c, 0x66113c },
732 { 0x0140, 0x661140 },
733 { 0x0144, 0x661144 },
734 { 0x0148, 0x661148 },
735 { 0x014c, 0x66114c },
736 { 0x0150, 0x661150 },
737 { 0x0154, 0x661154 },
738 { 0x0158, 0x661158 },
739 { 0x015c, 0x66115c },
740 { 0x0160, 0x661160 },
741 { 0x0164, 0x661164 },
742 { 0x0168, 0x661168 },
743 { 0x016c, 0x66116c },
750 .mthd = 0x0020,
751 .addr = 0x000020,
753 { 0x0400, 0x661400 },
754 { 0x0404, 0x661404 },
755 { 0x0408, 0x661408 },
756 { 0x040c, 0x66140c },
757 { 0x0410, 0x661410 },
765 .addr = 0x001000,
766 .prev = -0x020000,
784 .mthd = 0x0000,
785 .addr = 0x000000,
787 { 0x0080, 0x660080 },
788 { 0x0084, 0x660084 },
789 { 0x0088, 0x660088 },
790 { 0x008c, 0x000000 },
797 .mthd = 0x0020,
798 .addr = 0x000020,
800 { 0x0180, 0x660180 },
801 { 0x0184, 0x660184 },
802 { 0x0188, 0x660188 },
803 { 0x0190, 0x660190 },
810 .mthd = 0x0020,
811 .addr = 0x000020,
813 { 0x0200, 0x660200 },
814 { 0x0204, 0x660204 },
815 { 0x0208, 0x660208 },
816 { 0x0210, 0x660210 },
823 .mthd = 0x0020,
824 .addr = 0x000020,
826 { 0x0300, 0x660300 },
827 { 0x0304, 0x660304 },
828 { 0x0308, 0x660308 },
829 { 0x0310, 0x660310 },
836 .mthd = 0x0300,
837 .addr = 0x000300,
839 { 0x0400, 0x660400 },
840 { 0x0404, 0x660404 },
841 { 0x0408, 0x660408 },
842 { 0x040c, 0x66040c },
843 { 0x0410, 0x660410 },
844 { 0x0414, 0x660414 },
845 { 0x0418, 0x660418 },
846 { 0x041c, 0x66041c },
847 { 0x0420, 0x660420 },
848 { 0x0424, 0x660424 },
849 { 0x0428, 0x660428 },
850 { 0x042c, 0x66042c },
851 { 0x0430, 0x660430 },
852 { 0x0434, 0x660434 },
853 { 0x0438, 0x660438 },
854 { 0x0440, 0x660440 },
855 { 0x0444, 0x660444 },
856 { 0x0448, 0x660448 },
857 { 0x044c, 0x66044c },
858 { 0x0450, 0x660450 },
859 { 0x0454, 0x660454 },
860 { 0x0458, 0x660458 },
861 { 0x045c, 0x66045c },
862 { 0x0460, 0x660460 },
863 { 0x0468, 0x660468 },
864 { 0x046c, 0x66046c },
865 { 0x0470, 0x660470 },
866 { 0x0474, 0x660474 },
867 { 0x0480, 0x660480 },
868 { 0x0484, 0x660484 },
869 { 0x048c, 0x66048c },
870 { 0x0490, 0x660490 },
871 { 0x0494, 0x660494 },
872 { 0x0498, 0x660498 },
873 { 0x04b0, 0x6604b0 },
874 { 0x04b8, 0x6604b8 },
875 { 0x04bc, 0x6604bc },
876 { 0x04c0, 0x6604c0 },
877 { 0x04c4, 0x6604c4 },
878 { 0x04c8, 0x6604c8 },
879 { 0x04d0, 0x6604d0 },
880 { 0x04d4, 0x6604d4 },
881 { 0x04e0, 0x6604e0 },
882 { 0x04e4, 0x6604e4 },
883 { 0x04e8, 0x6604e8 },
884 { 0x04ec, 0x6604ec },
885 { 0x04f0, 0x6604f0 },
886 { 0x04f4, 0x6604f4 },
887 { 0x04f8, 0x6604f8 },
888 { 0x04fc, 0x6604fc },
889 { 0x0500, 0x660500 },
890 { 0x0504, 0x660504 },
891 { 0x0508, 0x660508 },
892 { 0x050c, 0x66050c },
893 { 0x0510, 0x660510 },
894 { 0x0514, 0x660514 },
895 { 0x0518, 0x660518 },
896 { 0x051c, 0x66051c },
897 { 0x052c, 0x66052c },
898 { 0x0530, 0x660530 },
899 { 0x054c, 0x66054c },
900 { 0x0550, 0x660550 },
901 { 0x0554, 0x660554 },
902 { 0x0558, 0x660558 },
903 { 0x055c, 0x66055c },
911 .addr = 0x000000,
912 .prev = -0x020000,
930 nvkm_mask(device, 0x610490, 0x00000010, 0x00000000); in gf119_disp_core_fini()
931 nvkm_mask(device, 0x610490, 0x00000003, 0x00000000); in gf119_disp_core_fini()
933 if (!(nvkm_rd32(device, 0x610490) & 0x001e0000)) in gf119_disp_core_fini()
935 ) < 0) { in gf119_disp_core_fini()
937 nvkm_rd32(device, 0x610490)); in gf119_disp_core_fini()
940 chan->suspend_put = nvkm_rd32(device, 0x640000); in gf119_disp_core_fini()
950 nvkm_wr32(device, 0x610494, chan->push); in gf119_disp_core_init()
951 nvkm_wr32(device, 0x610498, 0x00010000); in gf119_disp_core_init()
952 nvkm_wr32(device, 0x61049c, 0x00000001); in gf119_disp_core_init()
953 nvkm_mask(device, 0x610490, 0x00000010, 0x00000010); in gf119_disp_core_init()
954 nvkm_wr32(device, 0x640000, chan->suspend_put); in gf119_disp_core_init()
955 nvkm_wr32(device, 0x610490, 0x01000013); in gf119_disp_core_init()
959 if (!(nvkm_rd32(device, 0x610490) & 0x80000000)) in gf119_disp_core_init()
961 ) < 0) { in gf119_disp_core_init()
963 nvkm_rd32(device, 0x610490)); in gf119_disp_core_init()
967 return 0; in gf119_disp_core_init()
983 .ctrl = 0,
984 .user = 0,
1001 mask[head->id] = nvkm_rd32(device, 0x6101d4 + (head->id * 0x800)); in gf119_disp_super()
1005 if (disp->super.pending & 0x00000001) { in gf119_disp_super()
1006 nv50_disp_chan_mthd(disp->chan[0], NV_DBG_DEBUG); in gf119_disp_super()
1009 if (!(mask[head->id] & 0x00001000)) in gf119_disp_super()
1014 if (disp->super.pending & 0x00000002) { in gf119_disp_super()
1016 if (!(mask[head->id] & 0x00001000)) in gf119_disp_super()
1022 if (!(mask[head->id] & 0x00010000)) in gf119_disp_super()
1027 if (!(mask[head->id] & 0x00001000)) in gf119_disp_super()
1032 if (disp->super.pending & 0x00000004) { in gf119_disp_super()
1034 if (!(mask[head->id] & 0x00001000)) in gf119_disp_super()
1041 nvkm_wr32(device, 0x6101d4 + (head->id * 0x800), 0x00000000); in gf119_disp_super()
1043 nvkm_wr32(device, 0x6101d0, 0x80000000); in gf119_disp_super()
1052 u32 stat = nvkm_rd32(device, 0x6101f0 + (chid * 12)); in gf119_disp_intr_error()
1053 u32 type = (stat & 0x00007000) >> 12; in gf119_disp_intr_error()
1054 u32 mthd = (stat & 0x00000ffc); in gf119_disp_intr_error()
1055 u32 data = nvkm_rd32(device, 0x6101f4 + (chid * 12)); in gf119_disp_intr_error()
1056 u32 code = nvkm_rd32(device, 0x6101f8 + (chid * 12)); in gf119_disp_intr_error()
1067 case 0x0080: in gf119_disp_intr_error()
1075 nvkm_wr32(device, 0x61009c, (1 << chid)); in gf119_disp_intr_error()
1076 nvkm_wr32(device, 0x6101f0 + (chid * 12), 0x90000000); in gf119_disp_intr_error()
1085 u32 intr = nvkm_rd32(device, 0x610088); in gf119_disp_intr()
1087 if (intr & 0x00000001) { in gf119_disp_intr()
1088 u32 stat = nvkm_rd32(device, 0x61008c); in gf119_disp_intr()
1092 nvkm_wr32(device, 0x61008c, 1 << chid); in gf119_disp_intr()
1094 intr &= ~0x00000001; in gf119_disp_intr()
1097 if (intr & 0x00000002) { in gf119_disp_intr()
1098 u32 stat = nvkm_rd32(device, 0x61009c); in gf119_disp_intr()
1100 if (chid >= 0) in gf119_disp_intr()
1102 intr &= ~0x00000002; in gf119_disp_intr()
1105 if (intr & 0x00100000) { in gf119_disp_intr()
1106 u32 stat = nvkm_rd32(device, 0x6100ac); in gf119_disp_intr()
1107 if (stat & 0x00000007) { in gf119_disp_intr()
1108 disp->super.pending = (stat & 0x00000007); in gf119_disp_intr()
1110 nvkm_wr32(device, 0x6100ac, disp->super.pending); in gf119_disp_intr()
1111 stat &= ~0x00000007; in gf119_disp_intr()
1116 nvkm_wr32(device, 0x6100ac, stat); in gf119_disp_intr()
1119 intr &= ~0x00100000; in gf119_disp_intr()
1123 const u32 hoff = head->id * 0x800; in gf119_disp_intr()
1124 u32 mask = 0x01000000 << head->id; in gf119_disp_intr()
1126 u32 stat = nvkm_rd32(device, 0x6100bc + hoff); in gf119_disp_intr()
1127 if (stat & 0x00000001) in gf119_disp_intr()
1129 nvkm_mask(device, 0x6100bc + hoff, 0, 0); in gf119_disp_intr()
1130 nvkm_rd32(device, 0x6100c0 + hoff); in gf119_disp_intr()
1140 nvkm_wr32(device, 0x6100b0, 0x00000000); in gf119_disp_fini()
1158 const u32 hoff = head->id * 0x800; in gf119_disp_init()
1159 tmp = nvkm_rd32(device, 0x616104 + hoff); in gf119_disp_init()
1160 nvkm_wr32(device, 0x6101b4 + hoff, tmp); in gf119_disp_init()
1161 tmp = nvkm_rd32(device, 0x616108 + hoff); in gf119_disp_init()
1162 nvkm_wr32(device, 0x6101b8 + hoff, tmp); in gf119_disp_init()
1163 tmp = nvkm_rd32(device, 0x61610c + hoff); in gf119_disp_init()
1164 nvkm_wr32(device, 0x6101bc + hoff, tmp); in gf119_disp_init()
1168 for (i = 0; i < disp->dac.nr; i++) { in gf119_disp_init()
1169 tmp = nvkm_rd32(device, 0x61a000 + (i * 0x800)); in gf119_disp_init()
1170 nvkm_wr32(device, 0x6101c0 + (i * 0x800), tmp); in gf119_disp_init()
1174 for (i = 0; i < disp->sor.nr; i++) { in gf119_disp_init()
1175 tmp = nvkm_rd32(device, 0x61c000 + (i * 0x800)); in gf119_disp_init()
1176 nvkm_wr32(device, 0x6301c4 + (i * 0x800), tmp); in gf119_disp_init()
1180 if (nvkm_rd32(device, 0x6100ac) & 0x00000100) { in gf119_disp_init()
1181 nvkm_wr32(device, 0x6100ac, 0x00000100); in gf119_disp_init()
1182 nvkm_mask(device, 0x6194e8, 0x00000001, 0x00000000); in gf119_disp_init()
1184 if (!(nvkm_rd32(device, 0x6194e8) & 0x00000002)) in gf119_disp_init()
1186 ) < 0) in gf119_disp_init()
1191 nvkm_wr32(device, 0x610010, (disp->inst->addr >> 8) | 9); in gf119_disp_init()
1194 nvkm_wr32(device, 0x610090, 0x00000000); in gf119_disp_init()
1195 nvkm_wr32(device, 0x6100a0, 0x00000000); in gf119_disp_init()
1196 nvkm_wr32(device, 0x6100b0, 0x00000307); in gf119_disp_init()
1205 const u32 hoff = head->id * 0x800; in gf119_disp_init()
1206 nvkm_mask(device, 0x616308 + hoff, 0x00000111, 0x00000010); in gf119_disp_init()
1209 return 0; in gf119_disp_init()
1224 .root = { 0,0,GF110_DISP },
1226 {{0,0,GF110_DISP_CURSOR }, nvkm_disp_chan_new, &gf119_disp_curs },
1227 {{0,0,GF110_DISP_OVERLAY }, nvkm_disp_chan_new, &gf119_disp_oimm },
1228 {{0,0,GF110_DISP_BASE_CHANNEL_DMA }, nvkm_disp_chan_new, &gf119_disp_base },
1229 {{0,0,GF110_DISP_CORE_CHANNEL_DMA }, nvkm_disp_core_new, &gf119_disp_core },
1230 {{0,0,GF110_DISP_OVERLAY_CONTROL_DMA}, nvkm_disp_chan_new, &gf119_disp_ovly },